DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Previous action: Claims 1 through 14 and 21 through 26 rejected
Present action: Claims 1 through 7 and 21 through 26 rejected. Claims 8 through 11, 13, 14, and 27 allowed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 4 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Jeong (US 2022/0367721).
Regarding claim 1.
Jeong teaches:
A semiconductor device comprising: a first memory die (fig 6,15:CS; [para 0131]) comprising: a memory cell array (fig 5,13,15:1; [para 0060,0120]) including: a first memory cell (fig 6,15:MC; [para 0052]) electrically coupled to a first word line (fig 6,13,15:WL; [para 0051,0116]);
and a second memory cell (fig 6,15:MC; [para 0052]) electrically coupled to the first word line (fig 6,13,15:WL; [para 0051,0116]); a first bit line (fig 6,13,15:BL; [para 0051,0116]) electrically coupled to the first memory cell (fig 6,13,15:WL; [para 0051,0116]);
and a first interconnect structure (fig 15:CCL; [para 0128]) electrically coupled to the first word line (fig 6,13,15:WL; [para 0051,0116]), wherein the first interconnect structure (fig 15:CCL; [para 0128]) includes a first conductive feature (fig 15:LMP; [para 0092]) electrically coupled to the first word line (fig 6,13,15:WL; [para 0051,0116]) and a second conductive feature (fig 15:LMP; [para 0122])electrically coupled to the first bit line (fig 6,13,15:BL; [para 0051,0116]), wherein the first conductive feature (fig 15:LMP; [para 0122]) is disposed within the memory cell array (fig 5,13,15:1; [para 0060,0120]) in a plan view;
and a circuitry die (fig 6,15:PS; [para 0050,0131]) comprising: a second interconnect structure (fig 15:PCL; [para 0129]), wherein the first conductive feature (fig 15:LMP; [para 0122]) of the first interconnect structure (fig 15:CCL; [para 0128]) is directly bonded to a third conductive feature (fig 15:UMP; [para 0122]) of the second interconnect structure (fig 15:PCL; [para 0129]) through metal-to-metal bonds (fig 15:LMP,UMP; [para 0122]), wherein the first conductive feature (fig 15:LMP; [para 0122]) physically contacts the third conductive feature (fig 15:UMP; [para 0122]);
and a word line driver (fig 5,6:2; [para 0053]) electrically coupled to the first word line (fig 6,13,15:WL; [para 0051,0116]) between the first memory cell (fig 6,15:MC; [para 0052]) and the second memory cell (fig 6,15:MC; [para 0052]), wherein the word line driver (fig 5,6:2; [para 0053]) is electrically coupled to the first word line (fig 6,13,15:WL; [para 0051,0116]) through the first interconnect structure (fig 15:CCL; [para 0128]) and the second interconnect structure (fig 15:PCL; [para 0129]).
Regarding claim 4.
Jeong teaches the semiconductor device of claim 1,
Jeong teaches:
wherein the second conductive feature (fig 15:LMP; [para 0130]) is disposed within the memory cell array (fig 15:CS; [para 0131]) in the plan view (fig 11).
Claim(s) 21, 23, and 26 is/are rejected under 35 U.S.C. 102a2 as being anticipated by Jeong (US 2022/0367721).
Regarding claim 21.
Jeong teaches:
A semiconductor device comprising:
a memory die (fig 6,15:CS; [para 0131]) comprising a plurality of memory cells (fig 6,15:MC; [para 0052]) arranged in a memory cell array (fig 5,13,15:1; [para 0060,0120]), wherein the memory die (fig 6,15:CS; [para 0131]) includes word lines (fig 6,13,15:WL; [para 0051,0116]) and bit lines (fig 6,13,15:BL; [para 0051,0116]), wherein the memory die (fig 6,15:CS; [para 0131])comprises bond pads (fig 15:LMP; [para 0122]), wherein the bond pads (fig 15:LMP; [para 0122]) are arranged over intersections of the word lines (fig 6,13,15:WL; [para 0051,0116]) and bit lines (fig 6,13,15:BL; [para 0051,0116]) such that the bond pads (fig 15:LMP; [para 0122]) overlap respective intersections of the word lines (fig 6,13,15:WL; [para 0051,0116]) and bit lines (fig 6,13,15:BL; [para 0051,0116]) in a plan view (fig 13), wherein the memory die is free from functional circuits for controlling reading and writing operations of the memory cells (fig 6,15; [para 0062]);
and a logic die (fig 6,15:PS; [para 0050,0131]) comprising a plurality of functional circuits (fig 15:SA; [para 0129]), wherein the logic die (fig 6,15:PS; [para 0050,0131]) is bonded to the memory die (fig 6,15:CS; [para 0131]) using dielectric-to-dielectric bonds (fig 13:170,220; [para 0128,0129]) and metal-to-metal bonds (fig 15:LMP,UMP; [para 0122]).
Regarding claim 23.
Jeong teaches the semiconductor device of claim 21, further
Jeong teaches:
a front-side of the memory die (fig 6,15:CS; [para 0131]) is bonded to a front-side of the logic die (fig 6,15:PS; [para 0050,0131]).
Regarding claim 26.
Jeong teaches the semiconductor device of claim 21, further
Jeong teaches:
the functional circuits comprise bit line drivers (fig 5,6:sense amp; [para 0054]) electrically coupled to the bit lines (fig 6,13,15:BL; [para 0051,0116]) between memory cells (fig 6,15:MC; [para 0052]) on the bit lines (fig 6,13,15:BL; [para 0051,0116]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 2, 3, and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeong (US 2022/0367721) as applied to claim 1 and further in view of Or-Bach (US 2021/0375829).
Regarding claim 2.
Jeong teaches the semiconductor device of claim 1, above
Jeong does not teach stacked die
Or-Bach teaches:
a second memory die (fig 26a:memory level 2; [para 0201])bonded (fig 27c:35; [para 0203]) to the first memory die (fig 26a:memory level 1; [para 0201]) opposite the circuitry die (fig 26a:logic level; [para 0201]),
wherein the word line driver (fig 26a:row decoder; [para 0201]) is electrically coupled to a second word line (fig 26b; [para 0201])of the second memory die (fig 26a:memory level 2; [para 0201]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a second die in order to increase the amount of memory available in the stack.
Regarding claim 3.
Jeong in view of Or-Bach the semiconductor device of claim 2,
Jeong teaches:
a front-side of the first memory die (fig 6,15:CS; [para 0131]) is bonded to a front-side of the circuitry die (fig 6,15:PS; [para 0131]) by dielectric-to-dielectric bonds (fig 15:170,270; [para 0128,0129]) and metal-to- metal bonds (fig 6,15:UMP,LMP; [para 0130]), .
Or-Bach teaches:
wherein a front-side of the first memory die (fig 26a,27c:level 1; [para 0203]) is bonded to a front-side of the circuitry die (fig 26a:logic level; [para 0201]) and wherein a front-side of the second memory die (fig 26a,27c:level 2; [para 0203]) is bonded to a backside of the first memory die (fig 26a,27c:level 1; [para 0203]) by dielectric-to-dielectric bonds and metal-to-metal bonds (fig 21h; [para 0153]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to bond metal to metal and dielectric to dielectric in order to enable numerous fine pitch connections between die.
Regarding claim 5.
Jeong in view of Or-Bach the semiconductor device of claim 1,
Or-Bach teaches:
the second conductive (fig c:landing pad; [para 0203]) feature is disposed outside the memory cell array (fig 27a:cell array; [para 0203]) in the plan view (fig 26b,27c).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeong (US 2022/0367721) in view of Or-Bach (US 2021/0375829) as applied to claim 5 and further in view of Lee (US 2023/0144938).
Regarding claim 6.
Jeong in view of Or-Bach teaches the semiconductor device of claim 5, above
Jeong teaches:
wherein the first memory die (fig 6,15:CS; [para 0131])further comprises a bit line [circuitry] (fig 6,15:S/A; [para 0059]) electrically coupled to the first bit line (fig 5,15:BL; [para 0051,0116]) and the second conductive feature (fig 15:LMP; [para 0122]), wherein the bit line [circuitry] (fig 6,15:S/A; [para 0059]) is disposed outside (fig 6,14:PS; [para 0050,0131]) the memory cell array (fig 6,13,15:1; [para 0060,0120]).
Jeong in view of Or-Bach does not teach a multiplexer
Lee teaches:
a bit line multiplexer (fig 3:mux 1; [para 0082]) electrically coupled to the first bit line (fig 3:BL1; [para 0082]), wherein the bit line multiplexer (fig 3:mux 1; [para 0082]) is disposed outside the memory cell array (fig 3:11A; [para 0073]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the bit line circuitry to include a bit line multiplexer in order direct signals from a plurality of cells thereby increasing the amount of memory that the control circuitry can control.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeong (US 2022/0367721) as applied to claim 1 and further in view of Kim (US 2023/0105461)
Regarding claim 7.
Jeong teaches the semiconductor device of claim 1, above
Jeong does not teach CFET.
Kim teaches:
the first memory die comprises a complementary field-effect transistor (CFET) memory die (fig 1:PDT1,PDT2; [para 0022]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the memory structure to comprise CFET in order to enable reduce area scaling by stacking the nmos and pmos structures
Claim(s) 22 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeong (US 2022/0367721) as applied to claim 21 and further in view of Sharma (US 2024/0008239).
Regarding claim 22.
Jeong teaches the semiconductor device of claim 21, above
Jeong teaches:
the bond pads (fig 15:LMP; [para 0122]) are electrically coupled to intermediate portions of the bit lines (fig 15:BL; [para 0128]) within the memory cell array (fig 5,13c,15:1; [para 0060,0122]) in the plan view.
Jeong does not teach electrically coupling to intermediate portions of word lines.
Sharma teaches:
electrically coupling (fig 3:222; [para 0040]) to intermediate portions of the word lines (fig 1c,3:102; [para 0028,0040]) within the memory cell array (fig 1c,3:110; [para 0026,0040]) in the plan view.
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form connections from the word drive circuitry between the memory cells in order to reduce the horizontal length of the lines and thereby enable improved density and more memory (paragraph 25).
Regarding claim 25.
Jeong teaches the semiconductor device of claim 21, above
Jeong teaches:
the functional circuits comprise word line drivers (fig 5,6:2,row decoder; [para 0053]) electrically coupled to the word lines (fig 5,6:WL; [para 0053]) .
Jeong does not teach connections to the word lines between memory cells.
Sharma teaches:
the functional circuits comprise word line drivers (fig 1c:120; [para 0026]) electrically coupled (fig 3:222; [para 0040]) to the word lines (fig 1c,3:102; [para 0028,0040]) between memory cells (fig 1c,3:110; [para 0026,0040]) on the word lines (fig 1c,3:102; [para 0028,0040]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form connections from the word drive circuitry between the memory cells in order to reduce the horizontal length of the lines and thereby enable improved density and more memory (paragraph 25).
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeong (US 2022/0367721) as applied to claim 21 and further in view of Liu (US 2023/0380137).
Regarding claim 24.
Jeong teaches the semiconductor device of claim 21, above
Jeong does not teach additional bond pads.
Liu teaches:
the memory die (fig 4c:104; [para 0069]) further comprises additional bond pads (fig 4c:4021,4054; [para 0075,0082]) disposed outside the memory cell array (fig 4c:4024; [para 0082]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide bond pads outside of the memory cell array in order to facilitate connection between the logic die and external devices (paragraph 82).
Response to Arguments
Applicant’s arguments with respect to claim(s) 21 through 26 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Prior Art
Prior art cited but not relied upon: Sharma (US 2025/0095693), Catthoor (US 2024/0119998), Or-Bach (US 2021/0375829)
Allowable Subject Matter
Claims 8 through 11, 13, 14, and 27 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 8, the prior art does not teach in combination with all other elements of the claim: a word line electrically coupled to the first memory cell; and a bit line electrically coupled to the first memory cell and the second memory cell, wherein the first functional circuit is electrically coupled to the bit line between the first memory cell and the second memory cell, and a second interconnect structure on the memory die, wherein the second interconnect structure is bonded to the first interconnect structure by metal-to-metal bonds, wherein the second interconnect structure comprises a plurality of bit line bond pads, the plurality of bit line bond pads comprising a first bit line bond pad electrically coupled to the bit line, wherein the second interconnect structure comprises a plurality of word line bond pads, the plurality of word line bond pads comprising a first word line bond pad electrically coupled to the word line, and wherein the plurality of word line bond pads are disposed within the memory cell area in a plan view.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.J.G/ Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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