DETAILED ACTION
This action is responsive to the amendment filed March 5, 2026. The amendment has been entered.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
The indicated allowability of claims 8-13 and 21-27 is withdrawn in view of Chen et al. (US 2022/0302064).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 2, 4-8, 10-13, 21-23, 25, and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2022/0302064) in view of Chiou et al. (US 2022/0068856), of record.
(Re Claim 1) Chen teaches a device comprising (see Figs. 10A-13A and supporting text):
a first integrated circuit die (900) comprising:
a first substrate (700), wherein a first angle is between a first sidewall of the first substrate and a bottom surface of the first substrate in a first cross-sectional view (right angle in Fig. 13A); and
a first interconnect structure (920) on the bottom surface of the first substrate, wherein a second angle is between a first sidewall of the first interconnect structure and the bottom surface of the first substrate in the first cross-sectional view, wherein a third angle is between a second sidewall of the first interconnect structure and the bottom surface of the first substrate in a second cross-sectional view, wherein the first angle is larger than the second angle, wherein the third angle is larger than the second angle, and wherein the second sidewall of the first interconnect structure is longer than the first sidewall of the first interconnect structure in a top-down view (see Figs. 10B-10C, the corners at 940 are angled while the sides between the corners are at 90 deg);
a first gap-fill dielectric layer (292) around the first integrated circuit die;
a second integrated circuit die (210 and 240 of 200, further discussed below) comprising:
a second substrate (210); and
a second interconnect structure (240) on a bottom surface of the second substrate, wherein the first integrated circuit die is over a top surface of the second substrate; and a second gap-fill dielectric layer (192) around the second integrated circuit die.
Chen lacks details regarding whether the die 210+240 includes an integrated circuit (¶¶69-71). A PHOSITA desiring to make and use Chen’s die package would be motivated to look to related art to teach possible improvements and modifications where Chen is silent. Related art from Chiou similarly discloses a die package and teaches the interposer die 140 may include integrated circuits (¶26). Active interposers significantly improve system performance and efficiency by integrating active logic like voltage regulators and network-on-chip routers directly into the interposer. This allows for optimized power delivery, reduced signal latency, and improved communication between multiple chips compared to traditional passive interposers that only provide metal routing. A PHOSITA would find it obvious to further include integrated circuits in Chen’s interposer die to for the advantages noted above.
(Re Claim 2) wherein the first angle is a right angle (see Figs. 10A-13A).
(Re Claim 4) wherein the first integrated circuit die has a shape of an octagon in the top-down view (Fig. 10C, the planar surface 922 is an octagon).
(Re Claim 5) wherein an angle between two neighboring sides of the octagon is between 130° and 140° (Fig. 10C, 135 deg).
(Re Claim 6) wherein the first sidewall of the first interconnect structure is continuous and has a constant slope (see Figs. 10A-13A).
(Re Claim 7) further comprising: a first dielectric layer (262), wherein the first dielectric layer extends between the first integrated circuit die and the second integrated circuit die, wherein the first dielectric layer extends between the first gap-fill dielectric layer and the second gap-fill dielectric layer, wherein the first dielectric layer is in contact with the top surface of the second substrate (Fig. 13A); and a first die connector (metal in 260/262: e.g. 268+264) extending through the first dielectric layer, wherein the first die connector electrically couples the first integrated circuit die and the second integrated circuit die (Fig. 13A).
(Re Claim 8) Chen teaches a device comprising (see Figs. 10A-13A and supporting text):
a first dielectric layer (262);
a first die connector (metal in 260/262: e.g. 268+264) extending through the first dielectric layer;
a first integrated circuit die (900) on a first side of the first dielectric layer, the first integrated circuit die comprising:
a first substrate (700); and
a first interconnect structure (920) on a first surface of the first substrate, wherein a first angle is between a chamfered sidewall (940) of the first interconnect structure and the first surface of the first substrate, wherein a second angle is between a main sidewall of the first interconnect structure and the first surface of the first substrate, the second angle being larger than the first angle (the angles at the corners 940 are less than the right angles of 700 between the sides and the first surface);
a first gap-fill dielectric (292) on the first side of the first dielectric layer and around the first integrated circuit die, wherein the first gap-fill dielectric extends along the chamfered sidewall and the main sidewall of the first interconnect structure (Figs. 10A-13A); and
a second integrated circuit die (210 and 240 of 200, discussed below) on a second side of the first dielectric layer, wherein the second integrated circuit die is electrically coupled to the first integrated circuit die by the first die connector (Fig. 13A), the second integrated circuit die comprising:
a second substrate (210); and
a second interconnect structure (242) on a first surface of the second substrate; and
a conductive via (212/214) extending through the second substrate and between the first die connector and the second interconnect structure (Fig. 13A).
Chen lacks details regarding whether the die 210+240 includes an integrated circuit (¶¶69-71). A PHOSITA desiring to make and use Chen’s die package would be motivated to look to related art to teach possible improvements and modifications where Chen is silent. Related art from Chiou similarly discloses a die package and teaches the interposer die 140 may include integrated circuits (¶26). Active interposers significantly improve system performance and efficiency by integrating active logic like voltage regulators and network-on-chip routers directly into the interposer. This allows for optimized power delivery, reduced signal latency, and improved communication between multiple chips compared to traditional passive interposers that only provide metal routing. A PHOSITA would find it obvious to further include integrated circuits in Chen’s interposer die to for the advantages noted above.
(Re Claim 10) wherein the second angle is a right angle (see Figs. 10A-13A).
(Re Claim 11) wherein the chamfered sidewall of the first interconnect structure abuts the main sidewall of the first interconnect structure (see Figs. 10A-13A).
(Re Claim 12) wherein a third angle is between the chamfered sidewall of the first interconnect structure and the main sidewall of the first interconnect structure in a top-down view, the third angle being between 130° and 140° (Fig. 10C, 135 deg).
(Re Claim 13) wherein the main sidewall of the first interconnect structure has a larger length than the chamfered sidewall of the first interconnect structure in a top-down view (Fig. 10C).
(Re Claim 21) Chen teaches a device comprising (see Figs. 10A-13A and supporting text):
a first integrated circuit die (700+920) comprising:
a first substrate (700), wherein a first angle is between a first sidewall of the first substrate and a first surface of the first substrate in a first cross-sectional view (Fig. 13A); and
a first interconnect structure (920) on the first surface of the first substrate, wherein a second angle is between a first sidewall of the first interconnect structure and the first surface of the first substrate in the first cross-sectional view, wherein a third angle is between a second sidewall of the first interconnect structure and the first surface of the first substrate in a second cross-sectional view, wherein the first angle is larger than the second angle, and wherein the third angle is larger than the second angle (see Figs 10A-13A, first and third angles are right angles, second angle is acute angle at 940);
a first encapsulant (292) around the first integrated circuit die;
a second integrated circuit die (200, discussed below) underneath the first integrated circuit die, wherein the second integrated circuit die comprises:
a second substrate (210); and
a second interconnect structure (260 or 240) on the second substrate; and
a second encapsulant (192) around the second integrated circuit die.
Chen lacks details regarding whether the die 210+240 includes an integrated circuit (¶¶69-71). A PHOSITA desiring to make and use Chen’s die package would be motivated to look to related art to teach possible improvements and modifications where Chen is silent. Related art from Chiou similarly discloses a die package and teaches the interposer die 140 may include integrated circuits (¶26). Active interposers significantly improve system performance and efficiency by integrating active logic like voltage regulators and network-on-chip routers directly into the interposer. This allows for optimized power delivery, reduced signal latency, and improved communication between multiple chips compared to traditional passive interposers that only provide metal routing. A PHOSITA would find it obvious to further include integrated circuits in Chen’s interposer die to for the advantages noted above.
(Re Claim 22) wherein the first sidewall of the first substrate adjoins the first sidewall of the first interconnect structure in the first cross-sectional view (Figs. 10A-13A).
(Re Claim 23) wherein the first angle is a right angle, and wherein the third angle is a right angle (Figs. 10A-13A, right angles, the only angled parts are the chamfered portions at 940).
(Re Claim 25) wherein the first integrated circuit die has a shape of an octagon in a top-down view (Fig. 10C, the planar surface is an octagon), wherein the octagon has a first side intersecting with a second side, and wherein a fourth angle between the first side and the second side is between 130° and 140° (corners at 135 deg).
(Re Claim 26) wherein the first side is longer than the second side (Figs. 10A-13A).
Claims 3, 9, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. and Chiou et al. as applied above and further in view of Chiu et al. (US 2017/0323840) and Tsai et al. (US 2015/0214077).
(Re Claim 3) wherein the second angle is an acute angle and is larger than 85°.
(Re Claim 9) wherein the first angle is an acute angle and is larger than 85°.
(Re Claim 24) wherein the second angle is an acute angle larger than 85°.
Chen is silent regarding an acute angle within the claimed range. A PHOSITA would be motivated to look to related art to teach suitable angles for sidewalls of interconnect structures to determine if other angles offer any advantages. Related art from Chiu discloses a working angle between 88 and 90 degrees (¶21). A PHOSITA would find Chiu’s angle obvious to try for the disclosed angle to determine if there are advantages or benefits from selecting angles within the range. Related art from Tsai recognizes selecting angles in a range of 10-90° may avoid stress concentrations (¶46) making the angle a result effective variable, obvious to optimize and ascertainable trough routine experimentation In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. and Chiou et al. as applied above and further in view of Chen et al. (US 2017/0040294, Chen’294).
(Re Claim 27) wherein first encapsulant comprises two sublayers (910+292) having different materials.
Chen discloses 910 is epoxy molding compound (EMC), however is silent regarding a material of layer 292. A PHOSITA desiring to make and use Chen’s die package would be motivated to look to related art to teach suitable materials for layer 292. Related art from Chen’294 discloses underfill 130 comprises benzoic alcohol and silica (¶42). A PHOSITA would find it obvious to select working materials from the prior art for Chen’s layer 292. By selecting the material from Chen’294, the two layers having different materials. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Response to Arguments
Applicant’s arguments have been considered but are moot in view of the new grounds of rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST).
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/ERIK T. K. PETERSON/ Primary Examiner, Art Unit 2898
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