DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Sub-Species B2 in the reply filed on 12/5/2025 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US PG Pub 2019/0326296, hereinafter Wang) in view of IMAMURA et al. (US PG Pub 2011/0210422, hereinafter Imamura) and Matsuo et al. (US PG Pub 2003/0052409, hereinafter Matsuo).
Regarding claim 17, figure 6A of Wang discloses a method for forming an integrated chip, the method comprising:
forming a transistor device (170) along a substrate (602);
forming a plurality of conductive interconnects (610) over the transistor device, wherein a first conductive interconnect of the plurality of conductive interconnects forms a first electrode layer;
depositing an insulator layer (616) over the first electrode layer; and
depositing a second electrode layer (612) over the insulator layer to form a first MIM capacitor and a second MIM capacitor (¶ 61) from the second electrode layer, the insulator layer, and the first electrode layer.
Wang does not explicitly disclose etching the second electrode layer and the insulator layer.
In the same field of endeavor, figures 12 and 13 of Imamura disclose depositing an insulator layer (27) over a first electrode layer (21);
depositing a second electrode layer (42) over the insulator layer; and
etching the second electrode layer and the insulator layer to form a MIM capacitor.
In light of such teachings, it would have been obvious to one of ordinary skill in the art at the time the invention was made to form the MIM capacitors of Want by etching the second electrode layer and the insulator layer as taught by Imamura for the purpose of for the purpose of selecting a well-known process to form self-aligned structures (choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success (KSR International Co. v. Teleflex Inc. 82 USPQ2d 1385 (2007)).
Wang does not explicitly disclose forming an under-bump metal (UBM) layer directly over the first MIM capacitor and the second MIM capacitor; and forming a metal bump directly over the UBM layer.
In the same field of endeavor, figures 2A-2E of Matsuo disclose forming an under-bump metal (UBM) layer (20), and forming a metal bump (21) directly over the UBM layer.
In light of such teachings, it would have been obvious to one of ordinary skill in the art at the time the invention was made to form a UBM layer and metal bump on the interconnect (618) of Wang) as taught by Matsuo (and thus directly over the first MIM capacitor and the second MIM capacitor) for the purpose of forming external connections with improved electrical and mechanical stability (¶ 238).
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Imamura and Matsuo, as applied to claim 17, further in view of Chen (US PG Pub 2022/0051993).
Regarding claims 19 and 20, the prior art does not explicitly disclose forming a seal ring structure surrounding the conductive interconnects, wherein the UBM layer is formed adjacent to the seal ring structure; and
dicing the integrated chip along the seal ring structure.
In the same field of endeavor, figures 1 and 2 of Chen disclose forming a seal ring structure (200) surrounding a device region (150) and dicing the device along the seal ring structure (¶ 18).
In light of such teachings, it would have been obvious to one of ordinary skill in the art at the time the invention was made to form a seal ring structure the conductive interconnects (wherein the UMB layer would be adjacent) and dicing the device along the seal ring structure as taught by *** for the purpose of forming individual devices while protecting the circuits from moisture degradation and ionic contamination (¶ 2).
Furthermore, it would have been obvious to bond the metal bump to a bond pad for the purpose of providing input/output signals to operate the device.
Allowable Subject Matter
Claims 18 and 21-23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 24-36 are allowed.
Regarding claim 24, the closest prior art of record, Wang et al. (US PG Pub 2019/0326296, hereinafter Wang), either singularly or in combination, does not disclose or suggest the combination of limitations including “forming a transistor device along a semiconductor substrate;
forming a plurality of conductive interconnects over the transistor device;
forming a seal ring structure laterally surrounding the plurality of conductive interconnects;
forming a metal-insulator-metal (MIM) capacitor array over the transistor device, the MIM capacitor array comprising a first MIM capacitor and a second MIM capacitor, wherein the second MIM capacitor is laterally spaced from the first MIM capacitor and coupled in parallel with the first MIM capacitor, and wherein the first and second MIM capacitors are laterally spaced from the seal ring structure and laterally surrounded by the seal ring structure;
forming a first under-bump metal (UBM) layer directly over the first MIM capacitor and the second MIM capacitor and laterally spaced from the seal ring structure; and
forming a first metal bump on the first UBM layer”.
Regarding claim 31, the closest prior art of record, Wang et al. (US PG Pub 2019/0326296, hereinafter Wang), either singularly or in combination, does not disclose or suggest the combination of limitations including “forming a transistor device along a substrate;
forming a first conductive interconnect over and coupled to the transistor device;
forming a first lower electrode over and coupled to the first conductive interconnect;
forming a first insulator and a second insulator on the first lower electrode;
forming a first upper electrode on the first insulator and forming a second upper electrode on the second insulator, wherein the first lower electrode, the first insulator, and the first upper electrode form a first metal-insulator-metal (MIM) capacitor, and wherein the first lower electrode, the second insulator, and the second upper electrode form a second MIM capacitor;
forming a second conductive interconnect coupled to the first upper electrode and the second upper electrode;
forming a first under-bump metal (UBM) layer over and coupled to the second conductive interconnect, wherein a perimeter of the first UBM layer surrounds a perimeter of the first MIM capacitor and a perimeter of the second MIM capacitor in top view; and
forming a first metal bump on the first UBM layer”.
Conclusion
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/YU-HSI D SUN/ Primary Examiner, Art Unit 2817