DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “another conductive structure adjacent to the conductive structure in the first back end dielectric layer; and
another gate structure, of another non-volatile memory cell structure included the semiconductor device, in the second back end dielectric layer and the third back end dielectric layer,
wherein the other gate structure is over the other conductive structure,
wherein another portion of the second back end dielectric layer is included between the other conductive structure and the other gate structure, and
wherein the gate dielectric layer extends continuously over the gate structure and the other gate structure”, as recited in claim 3.
Claims 11-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “forming another word line conductive structure in the semiconductor device;
forming, over the other word line conductive structure, another recess through the second dielectric layer and through the first dielectric layer such that a top surface of the other word line conductive structure is exposed through the other recess;
forming another gate structure, of a volatile memory cell structure of the semiconductor device, in the other recess such that the other gate structure is directly connected with the other word line conductive structure;
forming another gate dielectric layer of the volatile memory cell structure over the other gate structure;
forming another channel layer of the volatile memory cell structure over the other gate dielectric layer; and
forming a plurality of other source/drain regions of the volatile memory cell structure over the other channel layer”, as recited in claim 11.
Claims 15-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
The primary reason for the allowance of the claim is the inclusion of the limitation “a gate dielectric layer that extends continuously over the respective gate structures” as recited in independent claim 15, in all of the claims which is not found in the prior art references.
Claims 16-20 are allowed for the same reasons as claim 15, from which they depend.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2 and 4 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Gomes et al. (U.S. 2023/0197654 A1, hereinafter refer to Gomes).
Regarding Claim 1: Gomes discloses a semiconductor device (see Gomes, Fig.5 as shown below and ¶ [0002]), comprising:
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a plurality of back end dielectric layers (303/304) (see Gomes, Fig.5 as shown above);
a conductive structure (10) in a first back end dielectric layer (303/304) of the plurality of back end dielectric layers (303/304) (see Gomes, Fig.5 as shown above); and
a gate structure (318/320), of a non-volatile memory cell structure (391) included in the semiconductor device, in a second back end dielectric layer (303/304) and a third back end dielectric layer (303/304) of the plurality of back end dielectric layers (303/304) (see Gomes, Fig.5 as shown above),
wherein the gate structure (318/320) is over the conductive structure (10) (see Gomes, Fig.5 as shown above), and
wherein a portion of the second back end dielectric layer (304) is included between the conductive structure (10) and the gate structure (318/320) (see Gomes, Fig.5 as shown above).
Regarding Claim 2: Gomes discloses a semiconductor device as set forth in claim 1 as above. Gomes further teaches wherein a gate dielectric layer (320), of the non-volatile memory cell structure (391), over the gate structure (318/320) (see Gomes, Fig.5 as shown above);
a channel layer (302), of the non-volatile memory cell structure, over the gate dielectric layer (320) (see Gomes, Fig.5 as shown above); and
a plurality of source/drain regions (340), of the non-volatile memory cell structure, coupled with the channel layer (302) (see Gomes, Fig.5 as shown above and ¶ [0044]),
wherein the gate dielectric layer (320), the channel layer (302), and the plurality of source/drain regions are included in the third back end dielectric layer (303) (see Gomes, Fig.5 as shown above).
Regarding Claim 4: Gomes discloses a semiconductor device as set forth in claim 2 as above. Gomes further teaches wherein the conductive structure (10) corresponds to a word line conductive structure (10) that is coupled with the non-volatile memory cell structure (391) (see Gomes, Fig.5 as shown above);
wherein the semiconductor device further comprises:
a bit line conductive structure (348/349) coupled with a first source/drain region of the plurality of source/drain regions (see Gomes, Fig.5 as shown above); and
a select line conductive structure (348/349) coupled with a second source/drain region of the plurality of source/drain regions (see Gomes, Fig.5 as shown above).
Claim(s) 8-10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Gomes et al. (U.S. 2023/0197135 A1, hereinafter refer to Gomes ‘135).
Regarding Claim 8: Gomes’ 135 discloses a method (see Gomes’135, Fig.5 as shown below and ¶ [0004]), comprising:
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forming a word line conductive structure (10) in a semiconductor device (see Gomes’135, Fig.5 as shown above);
forming a first dielectric layer (304) over the word line conductive structure (10) (see Gomes’135, Fig.5 as shown above);
forming a second dielectric layer (303) over the first dielectric layer (304) (see Gomes’135, Fig.5 as shown above);
forming, over the word line conductive structure (10), a recess through the second dielectric layer (303) and into the first dielectric layer (304) such that a portion of the first dielectric layer (304) remains over the word line conductive structure (10) (see Gomes’135, Fig.5 as shown above);
forming a gate structure (318), of a non-volatile memory cell structure of the semiconductor device, in the recess such that the portion of the first dielectric layer (304) is included between the gate structure (318) and the word line conductive structure (10) (see Gomes’135, Fig.5 as shown above);
forming a gate dielectric layer (320) of the non-volatile memory cell structure over the gate structure (318) (see Gomes’135, Fig.5 as shown above);
forming a channel layer (302) of the non-volatile memory cell structure over the gate dielectric layer (320) (see Gomes’135, Fig.5 as shown above); and
forming a plurality of source/drain regions of the non-volatile memory cell structure over the channel layer (302) (see Gomes’135, Fig.5 as shown above and ¶ [0048]).
Regarding Claim 9: Gomes’ 135 discloses a method as set forth in claim 8 as above. Gomes ‘135 further teaches wherein forming an interconnect structure (340) over a source/drain region of the plurality of source/drain regions such that the interconnect structure (340) is coupled with the source/drain region (see Gomes’135, Fig.5 as shown above and ¶ [0066]); and
forming a bit line conductive structure (548) over the interconnect structure (340) such that the bit line conductive structure (548) is coupled with the interconnect structure (340) (see Gomes’135, Fig.5 as shown above and ¶ [0066]).
Regarding Claim 10: Gomes’ 135 discloses a method as set forth in claim 9 as above. Gomes ‘135 further teaches wherein forming another interconnect structure (340) over another source/drain region of the plurality of source/drain regions such that the other interconnect structure (340) is coupled with the other source/drain region (see Gomes’135, Fig.5 as shown above and ¶ [0066]); and
forming a select line conductive structure (349) over the other interconnect structure (340) such that the select line conductive structure (349) is coupled with the other interconnect structure (340) (see Gomes’135, Fig.5 as shown above and ¶ [0066]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Gomes et al. (U.S. 2023/0197654 A1, hereinafter refer to Gomes) as applied to claims 1 and 2 above, and further in view of Gomes et al. (U.S. 2023/0197135 A1, hereinafter refer to Gomes ‘135).
Regarding Claim 5: Gomes discloses a semiconductor device as set forth in claim 1 as above. Gomes further teaches wherein another conductive structure (10) in the first back end dielectric layer (304/303) (see Gomes, Fig.5 as shown above); and
another gate structure (318/320), of a volatile memory cell structure (391) included in the semiconductor device, in the second back end dielectric layer (303/304) and the third back end dielectric layer (303/304) (see Gomes, Fig.5 as shown above),
wherein the other gate structure (318/320) is over the other conductive structure (10) (see Gomes, Fig.5 as shown above), and
wherein the other gate structure (318/320) is in physical contact with the other conductive structure (10) (see Gomes, Fig.5 as shown above).
Gomes is silent upon explicitly disclosing separable conductive structure for a conductive structure and for another conductive structure adjacent to the conductive structure.
Before effective filing date of the claimed invention the disclosed separable conductive structure were known for forming a conductive structure and another conductive structure adjacent to the conductive structure in order to reduce the severity of supply voltage droop.
For support see Gomes’135, which teaches wherein separable conductive structure for a conductive structure (10) and for another conductive structure (10) adjacent to the conductive structure (10) (see Gomes’135, Fig.3A and ¶ [0004]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Gomes and Gomes’135 to enable the Gomes conductive structure (10) and another conductive structure (10) separable from each other as taught by Gomes’135 in order to reduce the severity of supply voltage droop.
Regarding Claim 6: Gomes as modified teaches a semiconductor device as set forth in claim 5 as above. The combination of Gomes and Gomes’135 is silent upon explicitly disclosing wherein a width of the gate structure is lesser relative to a width of the other gate structure.
However, the combination of Gomes and Gomes’135 teaches wherein a width of the gate structure (318/320) is equal to relative to a width of the other gate structure (318/320) (see Gomes, Fig.5 as shown above and see Gomes’135, Fig.3A).
Hence, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the width of the gate structure and the width of the other gate structure through routine experimentation and optimization to obtain optimal or desired device performance because the width of the gate structure and the width of the other gate structure is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Regarding Claim 7: Gomes as modified teaches a semiconductor device as set forth in claim 5 as above. The combination of Gomes and Gomes’135 further teaches wherein the volatile memory cell structure (391) comprises: a deep trench capacitor structure (20) above the other gate structure (318/320) (see Gomes, Fig.5 as shown above),
wherein the volatile memory cell structure (391) is configured to selectively store an electrical charge in the deep trench capacitor structure (20) (see Gomes, Fig.5 as shown above), and
wherein the non-volatile memory cell structure (391) is configured to selectively store an electrical charge in the gate structure (318/320) (see Gomes, Fig.5 as shown above).
Claim(s) 14 is rejected under 35 U.S.C. 103 as being unpatentable over Gomes et al. (U.S. 2023/0197135 A1, hereinafter refer to Gomes ‘135) as applied to claim 8 above, and further in view of Tsai et al. (U.S. 2022/0254897 A1, hereinafter refer to Tsai).
Regarding Claim 14: Gomes’ 135 discloses a method as applied to claim 8 above. Gomes ‘135 is silent upon explicitly disclosing wherein the first dielectric layer comprises an etch stop layer in the semiconductor device; and
wherein the etch stop layer comprises at least one of: silicon carbon nitride (SiCN), or aluminum oxide (AlOx).
Before effective filing date of the claimed invention the disclosed material were known for forming etch stop layer while preventing diffusions of metal.
For support see, Tsai, which teaches wherein the first dielectric layer (636) comprises an etch stop layer (636) in the semiconductor device (see Tsai, Fig.28 and ¶ [0105]); and
wherein the etch stop layer (636) comprises at least one of: silicon carbon nitride (SiCN), or aluminum oxide (AlOx) (see Tsai, Fig.28 and ¶ [0105]).
Gomes’135 discloses the claimed invention except for the material of etch stop layer. Hence, it would have been obvious to one having ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Gomes’135 and Tsai to enable the known etch stop materials for forming etch stop layer, since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BITEW A DINKE/Primary Examiner, Art Unit 2812