Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
This office action is in response to applicant’s communication filed on 10/20/25. Claims 14-33 are pending in this application. Claims 21-33 have been withdrawn from examination.
Information Disclosure Statement
The information disclosure statements filed on 01/05/23 and 02/28/24 have been received and are being considered.
Restriction/Election
Applicants provisionally elect claims 14-20 for examination. This office action maintains the previous restriction requirement of 0818/2025. This office action asserts that the inventions do not overlap in scope because they are directed towards different features and are classified in separate categories. The inventions could be used separately because they are directed towards different features of the device. Finally, a serious burden would result if the inventions were to be rejoined because the search would have to be conducted across divergent classifications. Thus, the restriction requirement is maintained.
Claim Rejections Under 35 U.S.C. §103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14-20 are rejected under 35 U.S.C. §103 as being unpatentable over Dewey (US 20200295003 A1) and further in view of Liao (US 20220310818 A1).
Regarding claim 14, Dewey discloses a method comprising:
forming first nanostructures and second nanostructures (see pair of 106-2)above a trench isolation region (see fig 3a); removing a dummy gate from the first nanostructures and the second nanostructures (see fig 4-9a disclosing 112/104 is removed);
after removing the dummy gate (dummy gate 112 is removed), forming a dielectric wall between the first nanostructures and the second nanostructures (see fig 15, where dielectric spacer 122 is formed), the dielectric wall 122 separated from the first nanostructures by a first opening (see fig 15a disclosing spacing between 122), the dielectric wall 122/116 separated from the second nanostructures by a second opening (see fig 15a disclosing spacing between 106’s);
depositing a gate dielectric layer on the first nanostructures and the second nanostructures(see fig 15a disclosing depositing sidewalls of 122, see fig 15b reproduced below), the gate dielectric layer at least partially filling the first opening and the second opening(see fig 15a disclosing 122 in surfaces of openings); and forming a gate electrode layer on the gate dielectric layer (see 124 on 122, fig 16), the gate electrode layer disposed above the dielectric wall (see fig 16, 124 over vertical portions of 122).
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Note that the element 122 has a horizontal portion (gate dielectric portion) and a dielectric wall, vertical wall portions. Applicant has amended claim 14 to recite that the dielectric wall is deposited using a second deposition step.
However, Sung at least at paras[0059]-[0061] discloses two separate processes for forming horizontal and vertical dielectric layers, respectively. Dewey and Sung are in the same or similar fields of endeavor. It would have been obvious to one having ordinary skill in the art at a time prior to the effective filing date of the present application to combine Sung with Dewey. Sung and Dewey may be combined by forming the dielectric layers of Dewey separately as taught in Sung, in order to facilitate interconnections, see paras [0059]-[0061].
Regarding claim 15, Dewey and Sung disclose the method of claim 14, wherein forming the dielectric wall (vertical portions of 122) comprises:
depositing a liner layer on the gate dielectric layer (see formation of 116 on 122);
depositing a dielectric material on the liner layer (see deposition of vertical layers of 122 on 116, fig 15b);
patterning the dielectric material (see 15b where 122 conformed to exposed surface pattern, see para [0044] disclosing 122 is patterned), the dielectric wall (vertical portions of 122) comprising a remaining portion of the dielectric material between the first nanostructures and the second nanostructures (see 116 with 122 between 106); and
removing portions of the liner layer (portions of 116 removed) around the first nanostructures and the second nanostructures to form the first opening and the second opening (see 116 is removed, fig 12, see para [0050] disclosing portions of 116 being removed).
Regarding claim 16, Dewey discloses the method of claim 15, wherein the gate electrode layer is formed on the dielectric wall (see formation of 124 on 122, fig 16).
Regarding claim 17, Dewey and Sung disclose the method of claim 15, wherein a portion of the liner layer 116 remains between the gate dielectric layer 122 and the dielectric wall (vertical portions of 122 see fig 15b disclosing 116 remains, see fig 16).
Regarding claim 18, Dewey and Sung disclose the method of claim 14, wherein forming the dielectric wall comprises:
depositing a liner layer on the first nanostructures, the second nanostructures, and the trench isolation region (see deposition of 116 on nanostructures 124);
depositing a dielectric material on the liner layer(122 116);
patterning the dielectric material (see para [0044], where 122 is patterned), the dielectric wall comprising a remaining portion of the dielectric material between the first nanostructures and the second nanostructures (see fig 11, disclosing 122 between 106); and
removing portions of the liner layer between the dielectric material and the first nanostructures and between the dielectric material and the second nanostructures to form the first opening and the second opening (see 122 is removed, at least partially figs 11-12).
Regarding claim 19, Dewey and Sung disclose the method of claim 18, wherein the gate dielectric layer is deposited on the dielectric wall (see fig 122 is on 116, fig 16).
Regarding claim 20, Dewey and Sung disclose the method of claim 18, wherein a portion of the liner layer 116 remains between the trench isolation region and the dielectric wall(see 116 remains, see fig 16).
Response to Arguments
Applicant has amended claims to recite additional features. This office action now cites to Sung as disclosing this feature. Applicant’s assertions are now moot.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD CHIN whose telephone number is (571)270-1827. The examiner can normally be reached M-F 9AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDWARD CHIN/Primary Examiner, Art Unit 2893
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