DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 8 and 27 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeng et al. (US 2020/0161267, as disclosed in previous office action).
As for claim 1, Jeng et al. disclose in Fig. 3 and the related text a package structure, comprising:
a first chip structure (left 140);
a second chip structure (right 140) beside the first chip structure;
an interconnection structure 120 over and contacting the first chip structure and the second chip structure (Fig. 3), wherein the interconnection structure has a plurality of dielectric layers 121/123/125/127 and a plurality of conductive features 122/124/126/184/220, and a first conductive feature 126 of the conductive features extends across a first (right) edge of the first chip structure and a second (left) edge of the second chip structure and is electrically connecting the first chip structure and the second chip structure (Fig. 3); and
a third chip structure (right 210) directly bonded to the interconnection structure through dielectric- to-dielectric bonding 121/230 and metal-to-metal bonding 184/220/218, wherein the second chip structure (right 140) is electrically connected to the third chip structure (right 210) through a second conductive feature 122 of the conductive features, the second conductive feature 122 is separated from the first conductive feature 126 by some of the dielectric layers 121/123/125/127, and the second conductive feature 122 extends across the first edge of the first chip structure, the second edge of the second chip structure, and a third (left) edge of the third chip structure (Fig. 3).
As for claim 2, Jeng et al. disclose the package structure as claimed in claim 1, further comprising: a fourth chip structure (left 210) directly bonded to the interconnection structure through dielectric- to-dielectric bonding 121/230 and metal-to-metal bonding 184/220/218, wherein the interconnection structure extends across the third edge of the third chip structure and a fourth edge of the fourth chip structure (Fig. 3).
As for claim 3, Jeng et al. disclose the package structure as claimed in claim 1, further comprising: a through-dielectric via (outer 122/124/126) penetrating at least some of the dielectric layers 121/123/125 of the interconnection structure (Fig. 3).
As for claim 4, Jeng et al. disclose the package structure as claimed in claim 1, wherein the first chip structure (left 140) has a substrate portion 142 and a device portion 142c/144, and the device portion is between the substrate portion and the interconnection structure (Fig. 3).
As for claim 8, Jeng et al. disclose the package structure as claimed in claim 1, further comprising: a plurality of conductive bumps 148 formed on the first chip structure and the second chip structure, wherein the interconnection structure 120 is between the third chip structure (right 210) and the conductive bumps 148 (Fig. 3).
As for claim 27, Jeng et al. disclose the package structure as claimed in claim 3, wherein the through-dielectric via (outer 122/124/126) vertically extends across opposite surfaces of the first conductive feature and opposite surfaces of the second conductive feature (Fig. 3).
Claim(s) 21-25 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 2014/0103488).
As for claim 21, Chen et al. disclose in Figs. 1-10 and the related text package structure, comprising:
a first chip structure 25;
a second chip structure 24 beside the first chip structure (Fig. 10);
an interconnection structure 52/54 over the first chip structure and the second chip structure (Fig. 10),
wherein a first interface between the interconnection structure and the first chip structure is substantially aligned with a second interface between the interconnection structure and the second chip structure (Fig. 10), the interconnection structure has a plurality of dielectric layers 52 and a plurality of conductive features 54, and one of the conductive features (lower 54) extends across a first edge of the first chip structure and a second edge of the second chip structure (Fig. 10); and a third chip structure 60 directly bonded to the interconnection structure through dielectric- to-dielectric bonding 52/(lower portion of 64) and metal-to-metal bonding 54/62, wherein the interconnection structure 52/54 is wider than the first chip structure in a lateral direction (Fig. 10), and the first chip structure 24 is wider than the third chip structure 60 in the lateral direction (Fig. 10).
As for claim 22, Chen et al. disclose the package structure as claimed in claim 21, wherein the third chip structure 60 has a dielectric bonding structure 64/52 and a metal bonding structure 54/62, a third interface between the dielectric bonding structure and the interconnection structure is substantially aligned with a fourth interface between the metal bonding structure and the interconnection structure (Fig. 10).
As for claim 23, Chen et al. disclose the package structure as claimed in claim 21, wherein the second chip structure 24 is electrically connected to the third chip structure 60 through a conductive path 54 formed in the interconnection structure (Fig. 10), and the conductive path extends across the first edge of the first chip structure, the second edge of the second chip structure, and a third edge of the third chip structure (Fig. 10).
As for claim 24, Chen et al. disclose the package structure as claimed in claim 21, further comprising: a protective layer (upper portion of 64) laterally surrounding the third chip structure 60, wherein a first edge of the protective layer is substantially aligned with a second edge of the interconnection structure (Fig. 10).
As for claim 25, Chen et al. disclose the package structure as claimed in claim 21, wherein the interconnection structure 52/54 extends across opposite edges of the third chip structure 60 (Fig. 10).
Claim Rejections - 35 USC § 103
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Jeng et al. (US 2020/0161267) in view of Yu et al. (US 2017/0170155).
As for claim 10, Jeng et al. disclose the package structure as claimed in claim 1, except a plurality of through-chip via 801 form in at least one of the first chip structure, the second chip structure, and a third chip structure.
Yu et al. teach in Fig. 8 and the related text a plurality of through-chip via 801 form in at least one of the first chip structure, the second chip structure, and a third chip structure 107.
Jeng et al. and Yu et al. are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Jeng et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Jeng et al. to include the limitations as taught by Yu et al. in order to interconnections of the semiconductor device
Claims 28-32 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2014/0103488) in view of Yu et al. (US 2017/0170155).
As for claim 28, Chen et al. disclose in Figs. 1-10 and the related text a package structure, comprising:
a first chip structure 24;
a second chip structure 25 beside the first chip structure;
an interconnection structure 52/54 over and contacting the first chip structure and the second chip structure (Fig. 10), wherein the interconnection structure 52/54 has a plurality of silicon-containing oxide layers 52 [0016] and a plurality of conductive features 54, and a first conductive feature (lower 54) of the conductive features overlaps a first (right) portion of the first chip structure 24 and a second (left) portion of the second chip structure 25 and is electrically connecting the first chip structure and the second chip structure (Fig. 10);
a third chip structure 58/60 directly bonded to the interconnection structure (Fig. 10), wherein the interconnection structure (lower 54) extends across opposite edges of the third chip structure (Fig. 10), the third chip structure 58/60 has a substrate (upper) portion and a device (lower) portion, and the device portion is between the substrate portion and the interconnection structure (Fig. 10).
Chen et al. do not disclose a through-chip via laterally surrounded by the substrate portion of the third chip structure.
Yu et al. teach in Fig. 8 and the related text a through-chip via 801 laterally surrounded by a substrate portion of a third chip structure 107.
Chen et al. and Yu et al. are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chen et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Chen et al. to include the limitations as taught by Yu et al. in order to interconnections of the semiconductor device.
As for claim 29, Chen et al. disclose the chip structure as claimed in claim 28, wherein the second chip structure 25 is electrically connected to the third chip structure 58 through a second conductive feature (upper 54) of the conductive features, the second conductive feature is separated from the first conductive feature by some of the silicon-containing oxide layers 52, and the second conductive feature (upper 54) extends across a first edge of the first chip structure, a second edge of the second chip structure, and a third edge of the third chip structure (Fig. 10).
As for claim 30, Chen et al. disclose the chip structure as claimed in claim 29, further comprising: a through-dielectric via (outer 54) penetrating at least some of the silicon-containing oxide layers 52 of the interconnection structure, wherein the through-dielectric via (outer 54) vertically extends across opposite surfaces of the first conductive feature and opposite surfaces of the second conductive feature (Fig. 10).
As for claim 31, Chen et al. disclose the chip structure as claimed in claim 28, wherein the interconnection structure 52/54 is wider than the first chip structure in a lateral direction (Fig. 10), and the first chip structure 24 is wider than the third chip structure 60 in the lateral direction (Fig. 10).
As for claim 32, Chen et al. disclose the chip structure as claimed in claim 28, wherein the first chip structure 24 extends across opposite edges of the third chip structure 58 (Fig. 10).
Response to Arguments
Applicant’s arguments with respect to claim(s) above have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached on Monday-Thursday (9am-4pm).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 5712721670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TRANG Q TRAN/Primary Examiner, Art Unit 2811