Prosecution Insights
Last updated: May 29, 2026
Application No. 18/150,642

Gate Isolation Regions and Fin Isolation Regions and Method Forming the Same

Non-Final OA §112
Filed
Jan 05, 2023
Priority
Jul 07, 2022 — provisional 63/367,828 +1 more
Examiner
ENAD, CHRISTINE A
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Co., Ltd.
OA Round
3 (Non-Final)
84%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
1114 granted / 1323 resolved
+16.2% vs TC avg
Moderate +10% lift
Without
With
+10.2%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
46 currently pending
Career history
1389
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
86.3%
+46.3% vs TC avg
§102
3.2%
-36.8% vs TC avg
§112
1.3%
-38.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1323 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/20/2026 has been entered. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 28-31 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Regarding claim 28, the limitations “a first outer sidewall forming a first ring” in line 11 and “a second outer sidewall forming a second ring” in line 22 contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor. The Figure 15A as pointed out in the applicant’s remark filed 2/12/2026 does not contain such limitations. Claims 29-31 are also rejected as being dependent on claim 28. Allowable Subject Matter Claims 1-4, 6-10, 21-27 are allowed over the prior art of record. The following is a statement of reasons for the indication of allowable subject matter: After further search and consideration of Applicant’s response, it is determined that the prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach or suggest “a second gate stack portion. and wherein the etching the gate stack to form the first trench comprises: forming at least one hard mask layer; and patterning the at least one hard mask layer, wherein the first trench is formed using the at least one hard mask layer as an etching mask; forming a gate isolation region filling the first trench, wherein the gate isolation region comprises: depositing a silicon nitride liner; and depositing a silicon oxide filling-region overlapping a first bottom portion of the silicon nitride liner; etching the gate stack to form a second trench, wherein a protruding semiconductor fin is revealed to the second trench, and wherein the etching the gate stack to form the second trench also comprises etching-through the at least one hard mask layer; etching the protruding semiconductor fin to extend the second trench into the bulk semiconductor substrate” as recited in independent claim 1; “performing a first planarization process to level a top surface of the gate isolation region, wherein the first planarization process is performed using a horizontal portion of the first dielectric liner as a stop layer; forming a fin isolation region penetrating through a second gate stack, and penetrating through a shallow trench isolation region underlying the second gate stack, wherein the forming the fin isolation region comprises: depositing a second dielectric liner, wherein the first dielectric liner has a different nitrogen atomic percentage than the second dielectric liner; depositing a second filling-region overlapping a second bottom portion of the second dielectric liner, wherein the first filling-region has a different oxygen atomic percentage than the second filling-region; and performing a second planarization process to level a top surface of the gate isolation region, wherein the second planarization process is performed after horizontal portions of the second dielectric liner have been removed”, as recited in independent claim 21. Claims 2-4, 6-10, 22-27 are also allowed as being directly or indirectly dependent of the allowed independent base claims. Response to Arguments Applicant’s arguments with respect to claims 28-30 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTINE A ENAD whose telephone number is (571)270-7891. The examiner can normally be reached Monday-Friday, 7:30 am -4:30 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571 272 1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTINE A ENAD/Primary Examiner, Art Unit 2811
Read full office action

Prosecution Timeline

Jan 05, 2023
Application Filed
Jul 25, 2025
Non-Final Rejection mailed — §112
Oct 27, 2025
Response Filed
Dec 17, 2025
Final Rejection mailed — §112
Feb 12, 2026
Response after Non-Final Action
Feb 20, 2026
Request for Continued Examination
Feb 28, 2026
Response after Non-Final Action
Apr 09, 2026
Non-Final Rejection mailed — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12641840
SELF-ALIGNED GATE EDGE AND LOCAL INTERCONNECT
3y 5m to grant Granted May 26, 2026
Patent 12641819
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
2y 10m to grant Granted May 26, 2026
Patent 12635162
GATE STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME
1y 11m to grant Granted May 19, 2026
Patent 12628371
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE
3y 9m to grant Granted May 12, 2026
Patent 12628579
LIGAND SELECTION FOR TERNARY OXIDE THIN FILMS
3y 10m to grant Granted May 12, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
84%
Grant Probability
94%
With Interview (+10.2%)
1y 11m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 1323 resolved cases by this examiner. Grant probability derived from career allowance rate.

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