DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/15/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 8-9, 11-13, 17, and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Yamashita (US Pub. No. 2016/0020235) in view of Shim (US Pub. No. 2024/0047501).
Regarding claim 1, in FIGs. 4A-4H, Yamashita discloses an image sensing structure comprising: a first semiconductor device (300) comprising: a top side (facing 200); a bottom side opposite to the top side of the first semiconductor device; and at least one first unit comprising: a plurality of first interconnects (310, paragraph [0050]) adjacent to the top side of the first semiconductor device; a row selector (row decoder, paragraph [0048]); and an analog-to-digital converter (ADC) (paragraph [0048]) connected to the row selector; and a second semiconductor device (200) disposed on the first semiconductor device, the second semiconductor device comprising: a top side (facing away from 300); a bottom side opposite to the top side of the second semiconductor device and facing the top side of the first semiconductor device; and at least one second unit comprising: a photodiode (500, paragraphs [0056] and [0016]) facing the top side of the second semiconductor device and configured to receive the light incident on the top side of the second semiconductor device, wherein the top side of the first semiconductor device is bonded to the bottom side of the second semiconductor device (paragraph [0053]); a transfer gate (208, paragraph [0030]) configured to transmit charges stored in the photodiode to a sensing node (206, paragraph [0038]); wherein the second semiconductor device includes a photo sensor chip and the first semiconductor device includes an application specific integrated circuit (ASIC) chip (paragraph [0047]), wherein light signals generated by the photodiode of the at least one second unit are directly transmitted to the row selector of the at least one first unit through a pixel level hybrid bonding (paragraph [0053]) at an interface between the top side of the first semiconductor device and the bottom side of the second semiconductor device, wherein the row selector selects a corresponding row for selecting a signal during a time period at a level in accordance with the voltage of the sensing node charged with an output current from the photodiode (paragraph [0018]); a source follower (136) configured to amplify a voltage of the sensing node (see FIG. 1).
Yamashita appears not to explicitly disclose that the second semiconductor device comprises the source follower.
The art however well recognized a source follower (SF) formed in a second semiconductor substrate (WFO; e.g. the same substrate containing photodiodes 210) to be suitable for use as a source follower in a an image sensing structure. See, for example, Shim, FIGs. 10A-10C, paragraphs [0027], [0036].
According to well-established patent law precedents (see, for example, M.P.E.P. § 2144.07), therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have formed the second semiconductor device to include the source follower for its recognized suitability as a source follower in a an image sensing structure.
Regarding claim 2, in FIGs. 4A-4H, Yamashita discloses that the top side of the first semiconductor device is bonded to the bottom side of the second semiconductor device through the pixel level hybrid bonding such that one first unit of the first semiconductor device corresponds to one or more second units of the second semiconductor device (pixel units 500, see FIG. 4G; paragraph [0053]).
Regarding claim 3, in FIGs. 4A-4H, Yamashita discloses that the ADC is directly electrically connected to the photo diode of the at least one second unit through the row selector and the pixel level hybrid bonding for immediate signal transfer (paragraph [0047]).
Regarding claim 8, in FIGs. 1-3 and 4A-4H, Yamashita discloses that the transfer gate (114, paragraph [0016]) is configured as a CMOS switch (interpreted as an FET transistor).
Regarding claim 9, the combination of Yamashita and Shim (see FIGs. 1-3 of 4A-4H, Yamashita) discloses that the at least one second unit of the second semiconductor device further comprises a reset transistor (116, paragraph [0016]) connected to the transfer gate, wherein the reset transistor and the transfer gate share a common n-plus doped region disposed between the reset transistor and the transfer gate (transistors are either NMOS or PMOS, paragraph [0016]).
Regarding claim 11, in FIGs. 1-3 and 4A-4H, Yamashita discloses an image sensing structure comprising: a first semiconductor device (300) comprising: a top side (facing 200); a bottom side opposite to the top side of the first semiconductor device; an analog-to-digital converter (ADC) (paragraph [0048]); and a plurality of first units, each of the plurality of first units comprising: a plurality of first interconnects (310, paragraph [0050]) adjacent to the top side of the first semiconductor device; and a row selector (row decoder, paragraph [0048]) connected to the plurality of first interconnects; wherein the analog-to-digital converter (ADC) is correspondingly connected to the plurality of first units; and a second semiconductor device (200) disposed on the first semiconductor device, the second semiconductor device comprising: a top side (facing away from 300); a bottom side opposite to the top side of the second semiconductor device and facing the top side of the first semiconductor device; and at least one second unit comprising: a photodiode (500, paragraphs [0056] and [0016]) adjacent to the top side of the second semiconductor device and configured to receive the light incident on the top side of the second semiconductor device; a transfer gate (208, paragraph [0030]) configured to transmit charges stored in the photodiode to a sensing node (206, paragraph [0038]); wherein the top side of the first semiconductor device is bonded to the bottom side of the second semiconductor device (paragraph [0053]), wherein the second semiconductor device includes a photo sensor chip and the first semiconductor device includes an application specific integrated circuit (ASIC) chip (paragraph [0047]), wherein light signals generated by the photodiode of the at least one second unit are directly transmitted to the row selector of one of the plurality of first units through a pixel level hybrid bonding (paragraph [0053]) at an interface between the top side of the first semiconductor device and the bottom side of the second semiconductor device, wherein the row selector selects a corresponding row for selecting a signal during a time period at a level in accordance with the voltage of the sensing node charged with an output current from the photodiode (paragraph [0018]); a source follower (136) configured to amplify a voltage of the sensing node (see FIG. 1).
Yamashita appears not to explicitly disclose that the second semiconductor device comprises the source follower.
The art however well recognized a source follower (SF) formed in a second semiconductor substrate (WFO; e.g. the same substrate containing photodiodes 210) to be suitable for use as a source follower in a an image sensing structure. See, for example, Shim, FIGs. 10A-10C, paragraphs [0027], [0036].
According to well-established patent law precedents (see, for example, M.P.E.P. § 2144.07), therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have formed the second semiconductor device to include the source follower for its recognized suitability as a source follower in a an image sensing structure.
Regarding claim 12, in FIGs. 1-3 and 4A-4H, Yamashita discloses that the bottom side of the second semiconductor device is bonded to the top side of the first semiconductor device through the pixel level hybrid bonding (pixel units 500, see FIG. 4G; paragraph [0053]).
Regarding claim 13, in FIGs. 1-3 and 4A-4H, Yamashita discloses that the ADC is directly electrically connected to the photo diode of the at least one second unit through the row selector and the pixel level hybrid bonding for immediate signal transfer (paragraph [0047]).
Regarding claim 17, in FIGs. 1-3 and 4A-4H, Yamashita discloses that the transfer gate (114, paragraph [0016]) is configured as a CMOS switch (interpreted as an FET transistor).
Regarding claim 21, in FIGs. 1-3 and 4A-4H, Yamashita discloses an image sensing structure comprising: a first semiconductor device (300) comprising: a top side (facing 200); a bottom side (opposite to the top side); and at least one first unit comprising: a plurality of first interconnects (310, paragraph [0050]) adjacent to the top side of the first semiconductor device; a row selector (row decoder, paragraph [0048]) electrically connected to the plurality of first interconnects; and an analog-to-digital converter (ADC) (paragraph [0048]) electrically connected to the row selector through the plurality of first interconnects; and a second semiconductor device (200) disposed on the first semiconductor device, the second semiconductor device comprising: a top side (facing away from 300); a bottom side facing the top side of the first semiconductor device; and at least one second unit comprising: a photodiode (500, paragraphs [0056] and [0016]) disposed in the second semiconductor device and configured to receive the light incident on the top side of the second semiconductor device; a transfer gate (208, paragraph [0030]) configured to transmit charges stored in the photodiode to a sensing node (206, paragraph [0038]); wherein the top side of the first semiconductor device is bonded to the bottom side of the second semiconductor device through a pixel level hybrid bonding such that one first unit of the first semiconductor device corresponds to one or more second units of the second semiconductor device (pixel units 500, see FIG. 4G; paragraph [0053]), wherein the second semiconductor device includes a photo sensor chip and the first semiconductor device includes an application specific integrated circuit (ASIC) chip (paragraph [0047]), wherein light signals generated by the photodiode of the at least one second unit are directly transmitted to the row selector of the at least one first unit through a pixel level hybrid bonding (paragraph [0053]) at an interface between the top side of the first semiconductor device and the bottom side of the second semiconductor device, wherein the row selector of the at least one first unit is directly electrically connected to the photodiode of the at least one second unit to control the light signals from the photodiode, wherein the row selector selects a corresponding row for selecting a signal during the time period at a level in accordance with the voltage of the sensing node charged with an output current from the photodiode (paragraph [0018]); a source follower (136) configured to amplify a voltage of the sensing node (see FIG. 1).
Yamashita appears not to explicitly disclose that the second semiconductor device comprises the source follower.
The art however well recognized a source follower (SF) formed in a second semiconductor substrate (WFO; e.g. the same substrate containing photodiodes 210) to be suitable for use as a source follower in a an image sensing structure. See, for example, Shim, FIGs. 10A-10C, paragraphs [0027], [0036].
According to well-established patent law precedents (see, for example, M.P.E.P. § 2144.07), therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have formed the second semiconductor device to include the source follower for its recognized suitability as a source follower in a an image sensing structure.
Regarding claim 22, in FIGs. 1-3 and 4A-4H, Yamashita discloses that the transfer gate (114, paragraph [0016]) is configured as a CMOS switch (interpreted as an FET transistor).
Claims 4-7, 14-16, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Yamashita (US Pub. No. 2016/0020235) in view of Shim (US Pub. No. 2024/0047501), and further in view of Johnson (US Pub. No. 2018/0227528).
Regarding claims 4, 14, and 23, in FIGs. 1-3 and 4A-4H, Yamashita discloses that the first unit comprises floating diffusion capacitors (134).
Yamashita appears not to explicitly disclose that the at least one (each) first unit further comprises a plurality of three dimension (3D) metal insulator metal (MIM) structures.
The art however well recognized MIM structures to be suitable for use as floating diffusion capacitors. See, for example, Johnson, paragraph [0019].
According to well-established patent law precedents (see, for example, M.P.E.P. § 2144.07), therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have formed the Yamashita disclosed floating diffusion capacitors with MIM structures for their recognized suitability as floating diffusion capacitors. In doing so, the at least one first unit further comprises a plurality of three dimension (3D) (the structures are 3-dimensional) metal insulator metal (MIM) structures.
Regarding claims 5 and 15, the combination of Yamashita, Shim, and Johnson discloses (see FIGs. 1-3 and 4A-4H of Yamashita) discloses that the plurality of 3D MIM structures are configured to store signals detected by the photodiode (they are floating diffusion capacitors).
Regarding claims 6 and 16, the combination of Yamashita, Shim, and Johnson discloses (see FIGs. 1-3 and 4A-4H of Yamashita) discloses that light signals generated by the photodiodes are correspondingly transmitted to the ADC through the plurality of first interconnects (paragraph [0071]).
Regarding claim 7, the combination of Yamashita, Shim, and Johnson discloses (see FIGs. 1-3 and 4A-4H of Yamashita) discloses that the pixel level hybrid bonding is a pixel-level joint of the at least one first unit and the at least one second unit (the first and second units of each pixel unit 500 are joined via hybrid bonding, see FIG. 4G; paragraph [0053]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yamashita (US Pub. No. 2016/0020235) in view of Shim (US Pub. No. 2024/0047501), and further in view of Kim (US Pub. No. 2006/0175536).
Regarding claim 10, the combination of Yamashita and Shim appears not to explicitly disclose that the source follower and the reset transistor share a common n-plus doped region disposed between the source follower and the reset transistor.
The art however well recognized a source follower and a reset transistor sharing a common drain (or doped region) disposed between the source follower and the reset transistor to be suitable for use as a floating diffusion/reset transistor configuration in an imager. See, for example, Kim, paragraph [0028].
According to well-established patent law precedents (see, for example, M.P.E.P. § 2144.07), therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have formed the source follower such that the source follower and the reset transistor share a common drain (or doped region) disposed between the source follower and the reset transistor.
In doing so, the at least one second unit of the second semiconductor device further comprises a source follower, wherein the source follower and the reset transistor share a common n-plus doped region (transistors are either NMOS or PMOS, paragraph [0016]) disposed between the source follower and the reset transistor.
Further, Examiner notes that a source/drain diffusion region (or doped region) can only have one of two possible dopant types (N or P). As such, there are a finite number of identified, predictable solutions, with a reasonable expectation of success.
According to well established patent law precedent (see, for example, M.P.E.P. § 2143 I (E)) therefore it would have been "obvious to try" forming the common doped region as a common n-plus doped region.
Response to Arguments
Applicant's arguments filed 1/15/2026 (“Reply”) have been fully considered but they are not persuasive. Applicant’s arguments with respect to claims 1-17 and 21-23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUCKER J WRIGHT whose telephone number is (571)270-3234. The examiner can normally be reached 8:30am-5:00pm.
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/TUCKER J WRIGHT/Primary Examiner, Art Unit 2891