Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Amendment filed on 12/30/2025 has been entered. Claims 1, 6, 8, 17 are amended. Claims 1 – 20 are pending.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 – 3, 6, 8, 9, 13, 14, 16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Liao ( Pub. No. US 20120313178 A1 ), hereinafter Liao.
PNG
media_image1.png
856
1429
media_image1.png
Greyscale
Regarding Independent Claim 1 ( Currently amended ), Liao teaches a method of manufacturing a semiconductor structure, comprising:
receiving a substrate ( Liao, FIG. 3, 200; [0020], substrate 200 ), including a fin structure ( Liao, FIG. 3, 210, 214, 212; [0019], A first transistor 210, a second transistor 212, and a third transistor 214 are formed on the substrate 200 );
forming a sacrificial gate layer ( Liao, FIG. 3, 280; [0026], sacrificial masking layer 280 ) over the fin structure ( Liao, FIG. 3, 210, 214, 212; [0019], A first transistor 210, a second transistor 212, and a third transistor 214 are formed on the substrate 200 ) and a source/drain structure ( Liao, FIG. 3, 230; [0020], first source/drain 230, second source/drain 232, third source/drain 234 ) adjacent to the sacrificial gate layer ( Liao, FIG. 3, 280; [0026], sacrificial masking layer 280 ), wherein the sacrificial gate layer ( Liao, FIG. 3, 280; [0026], sacrificial masking layer 280 ) is surrounded by a dielectric structure ( Liao, FIG. 3, 226, 242; [0020], spacer 226, inter-layer dielectric (ILD) layer 242 ), and a top surface of the sacrificial gate layer ( Liao, FIG. 3, 280 ) is aligned ( Liao, [0027], an etching back process is performed to remove a portion of the sacrificial masking layer 280 in the first gate trench 260 ) with a top surface of dielectric structure ( Liao, FIG. 3, 226, 242 ) ( During the etch back process in Liu, FIG. 3 to FIG. 4, a top surface of sacrificial masking layer 280 is aligned with a top surface of spacer 226 or inter-layer dielectric (ILD) layer 242 );
removing the sacrificial gate layer ( Liao, [0027], an etching back process is performed to remove a portion of the sacrificial masking layer 280 in the first gate trench 260 ), wherein a recess ( Liao, FIG. 3, 260; [0021], first gate trench 260 ) is defined by the dielectric structure ( Liao, FIG. 3, 226, 242; [0020], spacer 226, inter-layer dielectric (ILD) layer 242 );
forming a work function layer (Liao, FIG. 3, 208, 270; [0024], inter layer 208 is selectively formed in the first gate trench 260 and the third gate trench 264 if required; [0025], first work function metal layer 270) in the recess (Liao, FIG. 3, 260; [0021], first gate trench 260), wherein the work function layer (Liao, FIG. 3, 208, 270; [0024], inter layer 208 is selectively formed in the first gate trench 260 and the third gate trench 264 if required; [0025], first work function metal layer 270) includes an overhang portion ( Liao, FIG. 3, 272, [0025], overhang 272 ) at an opening of the recess ( Liao, FIG. 3, 260; [0021], first gate trench 260 );
reducing a thickness ( Liao, [0028], Please refer to FIG. 5. Then, another etching back process is performed to remove the first work function metal layer 270 and the inter layer 208 not covered by the sacrificial masking layer 280 ) of the work function layer ( Liao, FIG. 3, 208, 270; [0024], inter layer 208 is selectively formed in the first gate trench 260 and the third gate trench 264 if required; [0025], first work function metal layer 270 ); wherein the work function layer ( Liao, FIG. 5, on the right, 208 and 270, cover 226 and 242; [0020], spacer 226, inter-layer dielectric (ILD) layer 242; [0024], inter layer 208; [0025], first work function metal layer 270 ) covers
forming a glue layer ( Liao, FIG.3, 270; [0025], first work function metal layer 270; FIG. 7, 274, 276, 278; [0028], U-shaped work function metal layer 274; [0030], second work function metal layer 276; [0031], filling metal layer 278 ) over the work function layer ( Liao, FIG. 3, 208, 270; [0024], inter layer 208 is selectively formed in the first gate trench 260 and the third gate trench 264 if required; [0025], first work function metal layer 270 ).
Regarding Claim 2 ( Original ), Liao teaches the method as claimed in claim 1, on which this claim is dependent, Liao further teaches:
wherein the overhang portion ( Liao, FIG. 3, 272, [0025], overhang 272 ) of the work function layer ( Liao, FIG. 3, 208, 270; [0024], inter layer 208 is selectively formed in the first gate trench 260 and the third gate trench 264 if required; [0025], first work function metal layer 270 ) is removed during the reduction of the thickness of the work function layer ( Liao, [0028], Please refer to FIG. 5. Then, another etching back process is performed to remove the first work function metal layer 270 and the inter layer 208 ).
Regarding Claim 3 ( Original ), Liao teaches the method as claimed in claim 1, on which this claim is dependent, Liao further teaches:
wherein the reduction of the thickness of the work function layer ( Liao, FIG. 3, 208, 270; [0024], inter layer 208 is selectively formed in the first gate trench 260 and the third gate trench 264 if required; [0025], first work function metal layer 270 ) includes a dry etching operation ( Liao, FIG. 5, 272 removed; [0028], More important, the etching back process simultaneously removes the overhang 272 formed at the opening of the first gate trench 260 ).
Regarding Claim 6 ( Currently amended ), Liao teaches the method as claimed in claim 1, on which this claim is dependent, Liao further teaches:
wherein the glue layer ( Liao, FIG.3, 270; [0025], first work function metal layer 270; FIG. 7, 274, 276, 278; [0028], U-shaped work function metal layer 274; [0030], second work function metal layer 276; [0031], filling metal layer 278 ) and the work function layer ( Liao, FIG. 3, 208, 270; [0024], inter layer 208 is selectively formed in the first gate trench 260 and the third gate trench 264 if required; [0025], first work function metal layer 270 ) include a same material ( Liao, FIG.3, 270; first work function metal layer 270).
Regarding Independent Claim 8 ( Currently amended ), Liao teaches a method of manufacturing a semiconductor structure, comprising:
receiving a substrate ( Liao, FIG. 3, 200; [0020], substrate 200 ), including a first sacrificial layer ( Liao, FIG. 3, 280 in 260; [0026], sacrificial masking layer 280; [0021], first gate trench 260 ) surrounded by a first isolation ( Liao, FIG. 3, 226 around 260, 242 around 260; [0020], spacer 226, inter-layer dielectric (ILD) layer 242; [0021], first gate trench 260 ) and a second sacrificial layer( Liao, FIG. 3, 280 in 264; [0026], sacrificial masking layer 280; [0021], third gate trench 264 ) surrounded by a second isolation ( Liao, FIG. 3, 226 around 264, 242 around 264; [0020], spacer 226, inter-layer dielectric (ILD) layer 242; [0021], third gate trench 264 ), wherein a top surface of the first sacrificial layer ( Liao, FIG. 3, 280 in 260 ) is aligned ( Liao, [0027], an etching back process is performed to remove a portion of the sacrificial masking layer 280 in the first gate trench 260 ) with a top surface of dielectric structure ( Liao, FIG. 3, 226, 242 ) ) with a top surface of first isolation ( Liao, FIG. 3, 226 around 260, 242 around 260 ), and a top surface of the second sacrificial layer ( Liao, FIG. 3, 280 in 264 ) is aligned ( Liao, [0029], Please refer to FIG. 6. Then, a proper etchant, such as etchant includes O2, H2, and N, is used to remove the sacrificial masking layer 280 ) with a top surface of the second isolation ( Liao, FIG. 3, 226 around 264, 242 around 264 ) ( During the etch back process in Liu, FIG. 3 to FIG. 4, a top surface of sacrificial masking layer 280 is aligned with a top surface of spacer 226 or inter-layer dielectric (ILD) layer 242; During the etch back process in Liu, FIG. 5 to FIG. 6, a top surface of sacrificial masking layer 280 is aligned with a top surface of spacer 226 or inter-layer dielectric (ILD) layer 242 );
removing the first sacrificial layer and the second sacrificial layer ( Liao, [0027], an etching back process is performed to remove a portion of the sacrificial masking layer 280 in the first gate trench 260 ), wherein a first recess ( Liao, FIG. 3, 260; [0021], first gate trench 260 ) is defined by the first isolation ( Liao, FIG. 3, 226 around 260, 242 around 260; [0020], spacer 226, inter-layer dielectric (ILD) layer 242; [0021], first gate trench 260 ), a second recess ( Liao, FIG. 3, 264; [0021], third gate trench 264 ) is defined by the second isolation ( Liao, FIG. 3, 226 around 264, 242 around 264; [0020], spacer 226, inter-layer dielectric (ILD) layer 242; [0021], third gate trench 264 ), and a width of the first recess ( Liao, FIG. 3, 260; [0021], first gate trench 260 ) is less than a width of the second recess ( Liao, FIG. 3, 264; [0021], third gate trench 264 );
forming a first metal layer ( Liao, FIG. 3, 208, 270; [0024], inter layer 208 is selectively formed in the first gate trench 260 and the third gate trench 264 if required; [0025], first work function metal layer 270 ) in the first recess ( Liao, FIG. 3, 260; [0021], first gate trench 260 ) and the second recess ( Liao, FIG. 3, 264; [0021], third gate trench 264 ), wherein the first metal layer includes an overhang portion ( Liao, FIG. 3, 272, [0025], overhang 272 ) at an opening of the first recess ( Liao, FIG. 3, 260; [0021], first gate trench 260 );
reducing a thickness ( Liao, [0028], Please refer to FIG. 5. Then, another etching back process is performed to remove the first work function metal layer 270 and the inter layer 208 ) of the first metal layer ( Liao, FIG. 3, 208, 270; [0024], inter layer 208 is selectively formed in the first gate trench 260 and the third gate trench 264 if required; [0025], first work function metal layer 270 ), wherein the first metal layer ( Liao, FIG. 5, on the right, 208 and 270, cover 226 and 242; [0020], spacer 226, inter-layer dielectric (ILD) layer 242; [0024], inter layer 208; [0025], first work function metal layer 270 ) covers a top surface of the first isolation ( Liao, FIG. 5, on the right, 226 and 242; [0020], spacer 226, inter-layer dielectric (ILD) layer 242 ) after the reduction of the thickness of the first metal layer ( Liao, [0028], Please refer to FIG. 5. Then, another etching back process is performed to remove the first work function metal layer 270 and the inter layer 208 not covered by the sacrificial masking layer 280 ); and
forming a second metal layer ( Liao, FIG. 7, 274, 276; [0028], U-shaped work function metal layer 274; [0030], second work function metal layer 276 ) filling the first recess ( Liao, FIG. 3, 260; [0021], first gate trench 260 ) and conformal ( Liao, FIG. 7, 278 conformally recessed at 264; [0031], filling metal layer 278; [0021], third gate trench 264 ) to the second recess ( Liao, FIG. 3, 264; [0021], third gate trench 264 ).
Regarding Claim 9 ( Original ), Liao teaches the method as claimed in claim 8, on which this claim is dependent, Liao further teaches:
forming a third metal layer ( Liao, FIG. 7, 278; [0031], filling metal layer 278 ) over the second metal layer ( Liao, FIG. 7, 274, 276; [0028], U-shaped work function metal layer 274; [0030], second work function metal layer 276 ), wherein the third metal layer ( Liao, FIG. 7, 278; [0031], filling metal layer 278 ) is disposed over the first recess ( Liao, FIG. 3, 260; [0021], first gate trench 260 ) and in the second recess ( Liao, FIG. 3, 264; [0021], third gate trench 264 ).
Regarding Claim 13 ( Original ), Liao teaches the method as claimed in claim 8, on which this claim is dependent, Liao further teaches:
wherein the reduction of the thickness of the first metal layer ( Liao, FIG. 3, 208, 270; [0024], inter layer 208 is selectively formed in the first gate trench 260 and the third gate trench 264 if required; [0025], first work function metal layer 270 ) includes a dry etch ( Liao, FIG. 5, 272 removed; [0028], More important, the etching back process simultaneously removes the overhang 272 formed at the opening of the first gate trench 260 ), and a removal rate of the dry etch on a horizontal portion of the first metal layer ( Liao, FIG. 3, 208, 270; [0024], inter layer 208 is selectively formed in the first gate trench 260 and the third gate trench 264 if required; [0025], first work function metal layer 270 ) is greater than a removal rate of the dry etch on a vertical portion of the first metal layer ( Liao, FIG. 3, 208, 270; [0024], inter layer 208 is selectively formed in the first gate trench 260 and the third gate trench 264 if required; [0025], first work function metal layer 270 ) ( Liao, FIG. 5, 272 removed; [0028], More important, the etching back process simultaneously removes the overhang 272 formed at the opening of the first gate trench 260 ).
Regarding Claim 14 ( Original ), Liao teaches the method as claimed in claim 8, on which this claim is dependent, Liao further teaches:
forming an oxide layer ( Liao, [0030], Please refer to FIG. 7. In addition, after forming the second gate trench 262 or after forming the high-K gate dielectric layer, an inter layer (not shown) is formed in the second gate trench 262 if required … After forming the inter layer, a second work function metal layer 276 is formed in the first gate trench 260, the second gate trench 262, and the third gate trench 264 ) over the first metal layer ( Liao, FIG. 3, 208, 270; [0024], inter layer 208 is selectively formed in the first gate trench 260 and the third gate trench 264 if required; [0025], first work function metal layer 270 ) prior to ( Liao, [0030], After forming the inter layer, a second work function metal layer 276 is formed in the first gate trench 260, the second gate trench 262, and the third gate trench 264 ) the forming of the second metal layer.
Regarding Claim 16 ( Original ), Liao teaches the method as claimed in claim 8, on which this claim is dependent, Liao further teaches:
wherein the width of the first recess ( Liao, FIG. 3, 260; [0021], first gate trench 260 ) is in a range of 20 to 100 nanometers, and the width of the second recess ( Liao, FIG. 3, 264; [0021], third gate trench 264 ) is in a range of 100 to 250 nanometers ( Liao, [0019], Although the first transistor 210 and the third transistor 214 include the same conductivity type, the first transistor 210 and the third transistor 214 include different line widths. For example, the first transistor 210 is the transistor device with line width smaller than 40 nanometer(nm) such as the logic circuit device while the third transistor 214 is the transistor device with line width larger than 0.15 micrometer (µm) such as the static random access memory (SRAM) device ).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Liao, in view of Hu ( US 20190207010 A1 ), hereinafter Hu.
Regarding Claim 4 ( Original ), Liao teaches the method as claimed in claim 1, on which this claim is dependent, Liao further teaches:
wherein the thickness of the work function layer ( Liao, FIG. 3, 208, 270; [0024], inter layer 208 is selectively formed in the first gate trench 260 and the third gate trench 264 if required; [0025], first work function metal layer 270 ).
Liao fails to disclose:
wherein the thickness of the work function layer is reduced by 20% to 60%.
However, Hu teaches:
wherein the thickness of the work function layer is reduced by 20% to 60% ( US 20190207010 A1, Hu, [0006], The wet deglaze removes less than 25 percent of the silicide block layer; [0031], The wet deglaze process may remove 20 percent to 25 percent of the thickness of the silicide block layer ).
Liao and Hu are both considered to be analogous to the claimed invention because they are manufacturing a semiconductor structure. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Liao ( the work function layer ), to incorporate the teachings of Hu ( the work function layer is reduced by 20% to 60% ), to provide a specific range for the thickness of the work function layer. Doing so would provide specific dimension to manufacture the semiconductor structure and implement it accordingly.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Liao, in view of Chiu ( US 20190273145 A1 ), hereinafter Chiu.
Regarding Claim 5 ( Original ), Liao teaches the method as claimed in claim 1, on which this claim is dependent, Liao further teaches:
wherein the thickness of the work function layer ( Liao, FIG. 3, 208, 270; [0024], inter layer 208 is selectively formed in the first gate trench 260 and the third gate trench 264 if required; [0025], first work function metal layer 270 ) prior to the reduction.
Liao fails to disclose:
wherein the thickness of the work function layer prior to the reduction is in a range of 30 to 100 angstroms.
However, Chiu teaches:
wherein the thickness of the work function layer prior to the reduction is in a range of 30 to 100 angstroms ( US 20190273145 A1, Chiu, [0027], The work function metal layer 148 may have a thickness ranging from about 20 angstroms to about 100 angstroms ).
Liao and Chiu are both considered to be analogous to the claimed invention because they are manufacturing a semiconductor structure. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Liao ( the thickness of the work function layer ), to incorporate the teachings of Chiu ( the thickness of the work function layer prior to the reduction is in a range of 30 to 100 angstroms ), to provide a specific range for the work function layer prior to the reduction. Doing so would provide specific dimension to manufacture the semiconductor structure and implement it accordingly.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Liao, in view of Wu ( US 20210057280 A1 ), hereinafter Wu.
Regarding Claim 7 ( Original ), Liao teaches the method as claimed in claim 1, on which this claim is dependent, Liao further teaches:
removing ( Liao, [0028], Please refer to FIG. 5. Then, another etching back process is performed to remove the first work function metal layer 270 and the inter layer 208 ) a portion of the glue layer ( Liao, FIG.3, 270; [0025], first work function metal layer 270; FIG. 7, 274, 276, 278; [0028], U-shaped work function metal layer 274; [0030], second work function metal layer 276; [0031], filling metal layer 278 ) and a portion of the work function layer ( Liao, FIG. 3, 208, 270; [0024], inter layer 208 is selectively formed in the first gate trench 260 and the third gate trench 264 if required; [0025], first work function metal layer 270 ) in the recess,
Liao fails to disclose:
wherein the removal stops above the fin structure by 5 to 30 nanometers.
However, Wu teaches:
wherein the removal stops above the fin structure by 5 to 30 nanometers ( US 20210057280 A1, Wu, [0071], In an embodiment the materials of the first gate stack 902, the second gate stack 904, and the third gate stack 906 may be recessed a distance of between about 5 nm and about 150 nm, such as about 120 nm ).
Liao and Wu are both considered to be analogous to the claimed invention because they are manufacturing a semiconductor structure. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Liao ( removing a portion of the glue layer and a portion of the work function layer in the recess ), to incorporate the teachings of Wu ( the removal stops above the fin structure by 5 to 30 nanometers ), to provide a specific range for where to stop the removal. Doing so would provide specific dimension parameters to manufacture the semiconductor structure and implement it accordingly.
Claims 10 – 12, 15, 17 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Liao, in view of Liu ( US 20160190322 A1 ), hereinafter Liu.
Regarding Claim 10 ( Previously presented ), Liao teaches the method as claimed in claim 8, on which this claim is dependent, Liao further teaches:
forming the second metal layer ( Liao, FIG. 7, 274, 276; [0028], U-shaped work function metal layer 274; [0030], second work function metal layer 276 ) in the second recess ( Liao, FIG. 3, 264; [0021], third gate trench 264 ); and
the first metal layer ( Liao, FIG. 3, 208, 270; [0024], inter layer 208 is selectively formed in the first gate trench 260 and the third gate trench 264 if required; [0025], first work function metal layer 270 ) and the second metal layer ( Liao, FIG. 7, 274, 276; [0028], U-shaped work function metal layer 274; [0030], second work function metal layer 276 ) and the second isolation ( Liao, FIG. 3, 226 around 264, 242 around 264; [0020], spacer 226, inter-layer dielectric (ILD) layer 242; [0021], third gate trench 264 ) in the second recess ( Liao, FIG. 3, 264; [0021], third gate trench 264 ), and portions of the first metal layer ( Liao, FIG. 3, 208, 270; [0024], inter layer 208 is selectively formed in the first gate trench 260 and the third gate trench 264 if required; [0025], first work function metal layer 270 ) and the second metal layer ( Liao, FIG. 7, 274, 276; [0028], U-shaped work function metal layer 274; [0030], second work function metal layer 276 ) in the first recess ( Liao, FIG. 3, 260; [0021], first gate trench 260 ).
Liao fails to disclose:
forming a first dielectric layer over the second metal layer;
removing portions of the first metal layer and the second metal layer between the first dielectric layer and the second isolation in the second recess.
However, Liu teaches:
forming a first dielectric layer ( Liu, [0023], A thick insulator 108, e.g., silicon dioxide (SiO2), covers the gate structures 100; [0025], a contact opening 115 is formed by etching away the thick insulator 108 down to the source/drain region 112 ) over the second metal layer;
removing ( Liu, [0025], a contact opening 115 is formed by etching away the thick insulator 108 down to the source/drain region 112 ) portions of the first metal layer and the second metal layer between the first dielectric layer ( Liu, [0023], A thick insulator 108, e.g., silicon dioxide (SiO2), covers the gate structures 100; [0025], a contact opening 115 is formed by etching away the thick insulator 108 down to the source/drain region 112 ) and the second isolation in the second recess.
Liao and Liu are both considered to be analogous to the claimed invention because they are manufacturing a semiconductor structure. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Liao ( the first recess having short width, the second recess having wide width ), to incorporate the teachings of Liu ( a first dielectric layer ), to provide different structures for the first recess ( not pass through the first dielectric layer to connect the contact plugs in the next step ) and the second recess ( pass through the first dielectric layer to connect the contact plugs in the next step ). Doing so would provide different structures for the manufacturing of different width transistors and implement them accordingly.
Regarding Claim 11 ( Original ), Liao and Liu teach the method as claimed in claim 10, on which this claim is dependent, Liao and Liu further teach:
forming a fourth metal layer ( Liao, FIG. 7, 278; [0031], filling metal layer 278 ) covering tops of remaining portions of the first metal layer ( Liao, FIG. 3, 208, 270; [0024], inter layer 208 is selectively formed in the first gate trench 260 and the third gate trench 264 if required; [0025], first work function metal layer 270 ) and the second metal layer (Liao, FIG. 7, 274, 276; [0028], U-shaped work function metal layer 274; [0030], second work function metal layer 276);
forming the fourth metal layer ( Liao, FIG. 7, 278; [0031], filling metal layer 278 ); and
forming the remaining portions of the first metal layer ( Liao, FIG. 3, 208, 270; [0024], inter layer 208 is selectively formed in the first gate trench 260 and the third gate trench 264 if required; [0025], first work function metal layer 270 ) and the second metal layer ( Liao, FIG. 7, 274, 276; [0028], U-shaped work function metal layer 274; [0030], second work function metal layer 276 ).
Liao fails to disclose:
forming a second dielectric layer over the fourth metal layer;
forming contact plugs penetrating the second dielectric layer and electrically connected to the remaining portions of the first metal layer and the second metal layer.
However, Liu teaches:
forming a second dielectric layer ( Liu, [0023], A thick insulator 108, e.g., silicon dioxide (SiO2), covers the gate structures 100; [0025], a contact opening 115 is formed by etching away the thick insulator 108 down to the source/drain region 112 ) over the fourth metal layer;
forming contact plugs ( Liu, [0014], FIG. 7 is a cross-sectional view of a completed pair of transistors having large area, low resistance source/drain contacts; [0039], The large surface area contacts 182, 184 are vertical columns containing a conducting material, e.g., metal ) penetrating the second dielectric layer ( Liu, [0023], A thick insulator 108, e.g., silicon dioxide (SiO2), covers the gate structures 100; [0025], a contact opening 115 is formed by etching away the thick insulator 108 down to the source/drain region 112 ) and electrically connected to the remaining portions of the first metal layer and the second metal layer.
Liao and Liu are both considered to be analogous to the claimed invention because they are manufacturing a semiconductor structure. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Liao ( the first recess having short width, the second recess having wide width ), to incorporate the teachings of Liu ( a second dielectric layer, contact plugs ), to provide specific structure for the second recess ( contact plugs pass through the second dielectric layer to connect the remaining portions of the first metal layer and the second metal layer ). Doing so would provide specific structure for the manufacturing of wide width transistor and implement it accordingly.
Regarding Claim 12 ( Original ), Liao and Liu teach the method as claimed in claim 10, on which this claim is dependent, Liao further teaches:
wherein an entirety of the second metal layer ( Liao, FIG. 7, 274, 276; [0028], U-shaped work function metal layer 274; [0030], second work function metal layer 276 ) in the first recess ( Liao, FIG. 3, 260; [0021], first gate trench 260 ) is removed, and a portion of the second metal layer ( Liao, FIG. 7, 274, 276; [0028], U-shaped work function metal layer 274; [0030], second work function metal layer 276 ) disposed on a bottom of the second recess ( Liao, FIG. 3, 264; [0021], third gate trench 264 ) is left remaining after the removal of the portions of the first metal layer ( Liao, FIG. 3, 208, 270; [0024], inter layer 208 is selectively formed in the first gate trench 260 and the third gate trench 264 if required; [0025], first work function metal layer 270 ) and the second metal layer ( Liao, FIG. 7, 274, 276; [0028], U-shaped work function metal layer 274; [0030], second work function metal layer 276 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to create “ an entirety of the second metal layer in the first recess is removed, and a portion of the second metal layer disposed on a bottom of the second recess is left remaining after the removal ” based on “ the width of the first recess is less than the width of second recess, such that no second material is deposited on the bottom of the first recess ”, since this is within the skill level of one in the art.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Liao, in view of Lee ( US 20040150029 A1 ), hereinafter Lee.
Regarding Claim 15 ( Original ), Liao teaches the method as claimed in claim 14, on which this claim is dependent, Liao further teaches:
wherein a thickness of the oxide layer ( Liao, [0030], Please refer to FIG. 7. In addition, after forming the second gate trench 262 or after forming the high-K gate dielectric layer, an inter layer (not shown) is formed in the second gate trench 262 if required … After forming the inter layer, a second work function metal layer 276 is formed in the first gate trench 260, the second gate trench 262, and the third gate trench 264 ).
Liao fails to disclose:
wherein a thickness of the oxide layer is in a range of 0.5 to 2 nanometers.
However, Lee teaches:
wherein a thickness of the oxide layer is in a range of 0.5 to 2 nanometers ( Lee, [0108], the thickness of the first oxide layer 6 is in a range between 0.5 nm and 200 nm).
Liao and Lee are both considered to be analogous to the claimed invention because they are manufacturing a semiconductor structure. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Liao ( the thickness of the oxide layer ), to incorporate the teachings of Lee ( the thickness of the oxide layer is in a range between 0.5 nm and 200 nm ), to point out the thickness of the oxide layer is in a range of 0.5 to 2 nanometers. Doing so would provide specific dimension to manufacture the semiconductor structure and implement it accordingly.
Regarding Independent Claim 17 ( Currently amended ), Liao teaches a semiconductor structure, comprising:
a fin structure ( Liao, FIG. 3, 210, 214, 212; [0019], A first transistor 210, a second transistor 212, and a third transistor 214 are formed on the substrate 200 );
a first pair of source/drain structures ( Liao, FIG. 3, 230; [0020], first source/drain 230 ) and a second pair of source/drain structures ( Liao, FIG. 3, 234; [0020], third source/drain 234 ) disposed in the fin structure, wherein a first distance ( Liao, FIG. 3, width of 260; [0021], first gate trench 260 ) between the first pair of source/drain structures ( Liao, FIG. 3, 230; [0020], first source/drain 230 ) is less than a second distance ( Liao, FIG. 3, width of 264; [0021], third gate trench 264 ) between the second pair of source/drain structures ( Liao, FIG. 3, 234; [0020], third source/drain 234 );
a first metal layer ( Liao, FIG. 3, 208, 270; [0024], inter layer 208 is selectively formed in the first gate trench 260 and the third gate trench 264 if required; [0025], first work function metal layer 270 ) , disposed over the fin structure, between the first pair of source/drain structures ( Liao, FIG. 3, 230; [0020], first source/drain 230 ), and between the second pair of source/drain structures ( Liao, FIG. 3, 234; [0020], third source/drain 234 );
a second metal layer ( Liao, FIG. 7, 274, 276; [0028], U-shaped work function metal layer 274; [0030], second work function metal layer 276 ), disposed over the fin structure and between the second pair of source/drain structures ( Liao, FIG. 3, 234; [0020], third source/drain 234 ), wherein the second metal layer ( Liao, FIG. 7, 274, 276; [0028], U-shaped work function metal layer 274; [0030], second work function metal layer 276 ) is absent between the first pair of source/drain structures ( Liao, FIG. 3, 230; [0020], first source/drain 230 );
the fin structure and between the second pair of source/drain structures ( Liao, FIG. 3, 234; [0020], third source/drain 234 );
the first metal layer ( Liao, FIG. 3, 208, 270; [0024], inter layer 208 is selectively formed in the first gate trench 260 and the third gate trench 264 if required; [0025], first work function metal layer 270 ) and between the first pair of source/drain structures ( Liao, FIG. 3, 230; [0020], first source/drain 230 ); and
the first metal layer ( Liao, FIG. 3, 208, 270; [0024], inter layer 208 is selectively formed in the first gate trench 260 and the third gate trench 264 if required; [0025], first work function metal layer 270 ),
the second pair of source/drain structures ( Liao, FIG. 3, 234; [0020], third source/drain 234 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to create that the second metal layer is absent between the first pair of source/drain structures, based on the first distance is less than the second distance and short enough to make the first metal layer is fully filled between the first pair of source/drain structures, since this is within the skill level of one in the art.
Liao fails to disclose:
a dielectric layer, disposed over the fin structure and between the second pair of source/drain structures;
a first contact plug, disposed over and electrically connected to the first metal layer and between the first pair of source/drain structures; and
a second contact plug and a third contact plug, disposed over and electrically connected to the first metal layer and the second metal layer,
wherein each of the second contact plug and the third contact plug is disposed between the dielectric layer and one of the second pair of source/drain structures; and a distance between the second contact plug and the third contact plug is less than the second distance between the second pair of source/drain structures.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to create that a distance between the second contact plug and the third contact plug is less than the second distance between the second pair of source/drain structures, in order to reduce the parasitic resistance and therefore increase the speed of channel switch, since this is within the skill level of one in the art.
However, Liu teaches:
a dielectric layer ( Liu, [0023], A thick insulator 108, e.g., silicon dioxide (SiO2), covers the gate structures 100; [0025], a contact opening 115 is formed by etching away the thick insulator 108 down to the source/drain region 112 ), disposed over the fin structure and between the second pair of source/drain structures;
a first contact plug ( Liu, [0014], FIG. 7 is a cross-sectional view of a completed pair of transistors having large area, low resistance source/drain contacts; [0039], The large surface area contacts 182, 184 are vertical columns containing a conducting material, e.g., metal ), disposed over and electrically connected to the first metal layer ( Liu, [0038], blanket silicide 176 ) and between the first pair of source/drain structures ( Liu, [0039] FIG. 7 shows a completed transistor structure 180 having fully formed large surface area contacts 182, 184 to the source and drain regions; [0042], epitaxial layer 174 ); and
a second contact plug and a third contact plug ( Liu, [0014], FIG. 7 is a cross-sectional view of a completed pair of transistors having large area, low resistance source/drain contacts; [0039], The large surface area contacts 182, 184 are vertical columns containing a conducting material, e.g., metal ), disposed over and electrically connected to the first metal layer ( Liu, [0038], blanket silicide 176, under 182 ) and the second metal layer ( Liu, [0038], blanket silicide 176, under 184 ),
wherein each of the second contact plug and the third contact plug ( Liu, [0014], FIG. 7 is a cross-sectional view of a completed pair of transistors having large area, low resistance source/drain contacts; [0039], The large surface area contacts 182, 184 are vertical columns containing a conducting material, e.g., metal ) is disposed between the dielectric layer ( Liu, [0023], A thick insulator 108, e.g., silicon dioxide (SiO2), covers the gate structures 100; [0025], a contact opening 115 is formed by etching away the thick insulator 108 down to the source/drain region 112 ) and one of the second pair of source/drain structures.
Liao and Liu are both considered to be analogous to the claimed invention because they are manufacturing a semiconductor structure. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Liao ( a first distance between the first pair of source/drain structures is less than a second distance between the second pair of source/drain structures ), to incorporate the teachings of Liu ( a dielectric layer, a first contact plug, a second contact plug and a third contact plug ), to provide different structures for the first pair of source/drain structures ( not pass through the dielectric layer to connect the first contact plug ) and the second pair of source/drain structures ( pass through the dielectric layer to connect the second contact plug and the third contact plug ). Doing so would provide different structures for the manufacturing of different width transistors and implement them accordingly.
Regarding Claim 18 ( Original ), Liao and Liu teach the semiconductor structure as claimed in claim 17, on which this claim is dependent, Liao further teaches:
an oxide layer ( Liao, [0030], Please refer to FIG. 7. In addition, after forming the second gate trench 262 or after forming the high-K gate dielectric layer, an inter layer (not shown) is formed in the second gate trench 262 if required … After forming the inter layer, a second work function metal layer 276 is formed in the first gate trench 260, the second gate trench 262, and the third gate trench 264 ), disposed between the first metal layer ( Liao, FIG. 3, 208, 270; [0024], inter layer 208 is selectively formed in the first gate trench 260 and the third gate trench 264 if required; [0025], first work function metal layer 270 ) and the second metal layer ( Liao, FIG. 7, 274, 276; [0028], U-shaped work function metal layer 274; [0030], second work function metal layer 276 ),
wherein the oxide layer ( Liao, [0030], Please refer to FIG. 7. In addition, after forming the second gate trench 262 or after forming the high-K gate dielectric layer, an inter layer (not shown) is formed in the second gate trench 262 if required … After forming the inter layer, a second work function metal layer 276 is formed in the first gate trench 260, the second gate trench 262, and the third gate trench 264 ) is absent between the first pair of source/drain structures ( Liao, FIG. 3, 230; [0020], first source/drain 230 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to create that the oxide layer is absent between the first pair of source/drain structures, based on the first distance is less than the second distance and short enough to make the first metal layer is fully filled between the first pair of source/drain structures, since this is within the skill level of one in the art.
Regarding Claim 19 ( Original ), Liao and Liu teach the semiconductor structure as claimed in claim 17, on which this claim is dependent, Liao further teaches:
wherein a first thickness of the first metal layer ( Liao, FIG. 3, 208, 270; [0024], inter layer 208 is selectively formed in the first gate trench 260 and the third gate trench 264 if required; [0025], first work function metal layer 270 ) between the first pair of source/drain structures ( Liao, FIG. 3, 230; [0020], first source/drain 230 ) is greater than a second thickness of the first metal layer ( Liao, FIG. 3, 208, 270; [0024], inter layer 208 is selectively formed in the first gate trench 260 and the third gate trench 264 if required; [0025], first work function metal layer 270 ) between the second pair of source/drain structures ( Liao, FIG. 3, 234; [0020], third source/drain 234 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to create that a first thickness of the first metal layer between the first pair of source/drain structures is greater than a second thickness of the first metal layer between the second pair of source/drain structures, based on the first distance is less than the second distance and short enough to make the first metal layer is fully filled between the first pair of source/drain structures, since this is within the skill level of one in the art.
Regarding Claim 20 ( Original ), Liao and Liu teach the semiconductor structure as claimed in claim 17, on which this claim is dependent,
Liao fails to disclose:
wherein a distance between the second contact plug and a top of the dielectric layer is less than a distance between the second contact plug and a bottom of the dielectric layer
However, Liu teaches:
wherein a distance between the second contact plug ( Liu, [0014], FIG. 7 is a cross-sectional view of a completed pair of transistors having large area, low resistance source/drain contacts; [0039], The large surface area contacts 182, 184 are vertical columns containing a conducting material, e.g., metal ) and a top of the dielectric layer ( Liu, [0023], A thick insulator 108, e.g., silicon dioxide (SiO2), covers the gate structures 100; [0025], a contact opening 115 is formed by etching away the thick insulator 108 down to the source/drain region 112 ) is less than a distance between the second contact plug ( Liu, [0014], FIG. 7 is a cross-sectional view of a completed pair of transistors having large area, low resistance source/drain contacts; [0039], The large surface area contacts 182, 184 are vertical columns containing a conducting material, e.g., metal ) and a bottom of the dielectric layer ( Liu, [0023], A thick insulator 108, e.g., silicon dioxide (SiO2), covers the gate structures 100; [0025], a contact opening 115 is formed by etching away the thick insulator 108 down to the source/drain region 112 ).
Liao and Liu are both considered to be analogous to the claimed invention because they are manufacturing a semiconductor structure. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Liao ( the first recess having short width, the second recess having wide width ), to incorporate the teachings of Liu ( the dielectric layer, the second contact plug ), to provide specific structure for the second recess and the wide width transistor. Doing so would provide specific structure for the manufacturing of wide width transistor and implement it accordingly.
Response to Arguments
Applicant’s argument for claims 1 and 8: page 2, line 9 from bottom, cited “ As shown in FIG. 3 of Liao, the top surface of the sacrificial gate layer (280) is higher than a top surface of the alleged dielectric structure (226, 242). Liao fails to teach or suggest that the top surface of the alleged sacrificial gate layer (280) is aligned with the top surface of the alleged dielectric structure (226, 242). ”.
Examiner’s response: please refer to claims 1 and 8 in Claim Rejections - 35 USC § 102 of this office action, for instance, claim 1, cited “ … and a top surface of the sacrificial gate layer ( Liao, FIG. 3, 280 ) is aligned ( Liao, [0027], an etching back process is performed to remove a portion of the sacrificial masking layer 280 in the first gate trench 260 ) with a top surface of dielectric structure ( Liao, FIG. 3, 226, 242 ) ( During the etch back process in Liu, FIG. 3 to FIG. 4, a top surface of sacrificial masking layer 280 is aligned with a top surface of spacer 226 or inter-layer dielectric (ILD) layer 242 ); … ”. Therefore, Liao teaches that the top surface of the alleged sacrificial gate layer (280) is aligned with the top surface of the alleged dielectric structure (226, 242).
Applicant’s argument for claim 17: page 3, line 5 from bottom, cited “ However, Liu dose not cure the deficiency. Liu may teach a second contact plug and a third contact plug (182, 184), but Liu fails to teach or suggest that a distance between the second and the third contact plugs (182, 184) is less than the second distance between the second pair of source/drain structures. ”.
Examiner’s response: please refer to claim 17 in Claim Rejections - 35 USC § 103 of this office action, cited “ It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to create that a distance between the second contact plug and the third contact plug is less than the second distance between the second pair of source/drain structures, in order to reduce the parasitic resistance and therefore increase the speed of channel switch, since this is within the skill level of one in the art. ”. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to create that a distance between the second and the third contact plugs (182, 184) is less than the second distance between the second pair of source/drain structures.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is (703)756-1792. The examiner can normally be reached M -̶ F 8:00 am -̶ 6:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817