Prosecution Insights
Last updated: October 01, 2026
Application No. 18/150,903

THERMAL BARRIER STRUCTURE IN PHASE CHANGE MATERIAL DEVICE

Final Rejection §103
Filed
Jan 06, 2023
Priority
Oct 17, 2022 — provisional 63/416,645
Examiner
TAN, DAVE
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
2 (Final)
81%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
73%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
13 granted / 16 resolved
+13.3% vs TC avg
Minimal -8% lift
Without
With
+-8.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
24 currently pending
Career history
41
Total Applications
across all art units

Statute-Specific Performance

§103
76.4%
+36.4% vs TC avg
§102
20.7%
-19.3% vs TC avg
§112
2.1%
-37.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 16 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendments Acknowledgment is made of the amendment filed 04/29/2026 (“Amend.”), in which: claims 16, 19, 26, 27, 32, and 35 are amended; claims 23 and 34 are cancelled; new claims 36 and 37 are added; and the rejection of the claims are traversed. Claims 16-22, 24-33 and 35-37 are currently pending an Office action on the merits as follows. Response to Arguments Applicant’s arguments with respect to claims 16-22, 24-33 and 35-37 have been fully considered but are moot in view of the new grounds of rejection. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 16, 17, 19, 24, and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Borodulin et al, US 20140264230 in view of Czubatyj et al, US 20070048945. Regarding claim 16, Borodulin discloses : A method for forming an integrated chip, the method comprising: forming a heater structure over a semiconductor substrate(Fig. 1, #16 formed over 12); depositing a thermal barrier layer over the heater structure(Fig. 10, #82 over #16); performing a first patterning process on the thermal barrier layer to form a thermal barrier structure over the heater structure(Fig. 11, #160 on #82 [0056]); depositing a phase change element (PCE) layer over the thermal barrier structure(Fig. 14, #170 PCM deposition [0058]); and performing a second patterning process on the PCE layer to form a PCE over the thermal barrier structure(Fig. 15, removing layer #98 to be patterned to #100 of Fig. 16 and finally into #102 of Fig. 23), wherein a length of the thermal barrier structure is greater than a length of the PCE(Fig. 23, #82 shown to be a longer length than #102). Borodulin does not disclose : wherein the PCE interfaces with opposing sidewalls of the thermal barrier structure, wherein a bottom surface of the PCE is aligned with a bottom surface of the thermal barrier structure. However, in the same field of endeavor, Czubatyj teaches : wherein the PCE interfaces with opposing sidewalls of the thermal barrier structure(Fig. 2a #28 interfaces with sidewalls of #26), wherein a bottom surface of the PCE is aligned with a bottom surface of the thermal barrier structure(Bottom surface of #28 aligned with bottom surface of #26). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Czubatyj to Borodulin to prevent leakage to surrounding structures (Czubatyj [0056]). Regarding claim 17, Borodulin as modified by Czubatyj discloses : The method of claim 16. Borodulin teaches : wherein the first patterning process is different from the second patterning process(First patterning process may be anisotropic etch [0056] and second patterning process may be chemical [0060]). Regarding claim 19, Borodulin as modified by Czubatyj discloses : The method of claim 16. Borodulin teaches : further comprising: forming a first conductive structure and a second conductive structure over the semiconductor substrate(Fig. 2, #24 and #25), wherein the heater structure is spaced laterally between the first and second conductive structures(#16 between #24 and #25), wherein the heater structure [[and]]is formed concurrently with both the first and second conductive structures(#24 and #25 may be formed from one metal layer and may be formed from an ohmic contact that is in contact with #16[0038]).. Regarding claim 24, Borodulin as modified by Czubatyj discloses : The method of claim 16. Borodulin teaches : wherein the thermal barrier layer comprises a non-oxide dielectric material(#18 may be formed of SiN [0035]). Regarding claim 25, Borodulin as modified by Czubatyj discloses : The method of claim 16. Borodulin teaches : wherein a thickness of the PCE is greater than a thickness of the thermal barrier layer(#82 may have a thickness of 1 nm to 500nm [0054] while #PCM may have a thickness of 1 nm to 5 um[0058]). Claim 18 and 37 is/are rejected under 35 U.S.C. 103 as being anticipated by Borodulin et al, US 20140264230, in view Czubatyj et al, US 20070048945, in further view of Lin et al, US 20200279998. Regarding claim 18, Borodulin as modified by Czubatyj discloses : The method of claim 17. Borodulin as modified by Czubatyj does not disclose : wherein the first patterning process comprises forming a first mask over the thermal barrier layer and the second patterning process comprises forming a second mask over the PCE layer, wherein the first mask is different from the second mask. However, in the same field of endeavor, Lin teaches : wherein the first patterning process comprises forming a first mask over the thermal barrier layer and the second patterning process comprises forming a second mask over the PCE layer(Fig. 5 and 6, photolithography of #112 [0037] and Fig. 12a, #1202 to form #1218 [0048]), wherein the first mask is different from the second mask(first patterning process may be photolithography and second patterning process may be isotropic etch). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the invention to use different mask for different layers because the known technique of photolithography and isotropic etch was recognized as part of ordinary capabilities of one skilled in the art. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007). Regarding claim 37, Borodulin as modified by Czubatyj discloses : The method of claim 16. Borodulin as modified by Czubatyj does not disclose : wherein the PCE has a top surface over the thermal barrier structure and an upper surface laterally offset from an individual sidewall of the opposing sidewalls of the thermal barrier structure, wherein the upper surface is vertically below the top surface, and wherein the PCE has a curved sidewall extending from the top surface to the upper surface. However, in the same field of endeavor, Lin teaches : wherein the PCE has a top surface over the thermal barrier structure and an upper surface laterally offset from an individual sidewall of the opposing sidewalls of the thermal barrier structure, wherein the upper surface is vertically below the top surface, and wherein the PCE has a curved sidewall extending from the top surface to the upper surface(Fig. 1, #118 shown to have a sloped sidewall). Therefore, It would have been an obvious matter of design choice to include with sidewalls spacers of Lin to Borodulin and Czubatyj to decrease power consumption by modifying a phase change layer (Lin [0017]) , since such a modification would have involved a mere change in the size of component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04. Claims 20 and 21 is/are rejected under 35 U.S.C. 103 as being anticipated by Borodulin et al, US 20140264230 in view Czubatyj et al, US 20070048945, in further view Li et al, US 20220285614. Regarding claim 20, Borodulin as modified by Czubatyj discloses : The method of claim 16. Borodulin as modified by Czubatyj does not disclose : further comprising: forming a sidewall spacer structure along outer opposing sidewalls of the PCE, wherein the sidewall spacer structure continuously extends from a top surface of the thermal barrier structure to the outer opposing sidewalls of the PCE. However, in the same field of endeavor, Li teaches : further comprising: forming a sidewall spacer structure along outer opposing sidewalls of the PCE(Fig. 7a, #77 formed along #40), wherein the sidewall spacer structure continuously extends from a top surface of the thermal barrier structure to the outer opposing sidewalls of the PCE(#77 extending from a top surface of #11 along #40). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Li to Borodulin and Czubatyj to include sidewall space to a phase change memory device to provide thermal conductivity (Li, [0045]). Regarding claim 21, Borodulin as modified by Czubatyj and Li discloses : The method of claim 20. Li teaches : further comprising: forming a hard mask over the PCE, wherein outer opposing sidewalls of the hard mask are aligned with the outer opposing sidewalls of the PCE(Fig. 7, #55 aligned with #43 of #40), wherein the sidewall spacer structure extends along the outer opposing sidewalls of the hard mask(#77 extends from #11 to top surface of #55). Claim 22 is/are rejected under 35 U.S.C. 103 as being anticipated by Borodulin et al, US 20140264230 in view Czubatyj et al, US 20070048945, in further view Li et al, US 20220285614 in further view of Cheng, US 20200411087. Regarding claim 22, Borodulin as modified by Czubatyj and Li discloses : The method of claim 21. Borodulin as modified by Czubatyj and Li does not disclose : wherein an upper surface of the sidewall spacer structure is vertically below an upper surface of the hard mask. However, in the same field of endeavor, Cheng teaches : wherein an upper surface of the sidewall spacer structure is vertically below an upper surface of the hard mask(Fig. 15 #606’ shown to be below #604). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Cheng to Borodulin, Czubatyj and Li to have sidewall spacers formed below a top surface of a hard mask. Claim(s) 26-28, 31, and 36 is/are rejected under 35 U.S.C. 103 as being unpatentable over Slovin et al, US 20200058853 in view of El-Hinnawy et al, US 20200058848. Regarding claim 26, Slovin discloses : A method for forming an integrated chip, comprising: depositing a conductive layer over a semiconductor substrate(RF switch using chemically protective and thermally conductive layer on #114); etching the conductive layer to form a first conductive structure(Fig. 1a, #108), a second conductive structure(#108), and a heater structure(#102), wherein the heater structure comprises a middle segment elongated in a first cross-sectional view(#106 and #104); depositing a first dielectric layer around the heater structure and the first and second conductive structures(#110 shown to surround #104, #106, #108); depositing a thermal barrier layer over the heater structure(Fig. 2c, #116 over #102); etching the thermal barrier layer to form a thermal barrier structure over the heater structure(#116 has high etch selectivity to fluorine-based etchant and may be any size #117a, #117b, and #177c [0028-0029]) ; depositing a phase change element (PCE) layer over the thermal barrier structure and the first and second conductive structures(Fig. 3a, #118); and etching the PCE layer to form a PCE over the thermal barrier structure(#118 may be dry etched [0047]), wherein in the first cross-sectional view opposing sidewalls of the PCE are spaced laterally between first opposing sidewalls of the thermal barrier structure(Fig. 6c, #118 spaced between sidewalls of #116). Slovin does not disclose : wherein the middle segment is spaced between the first and second conductive structures in a second cross-sectional view, wherein the heater structure is laterally offset from the first and second conductive structures, wherein the second cross-sectional view is taken along a direction substantially orthogonal to a direction of the first cross-sectional view. However, in the same field of endeavor, El-Hinnawy teaches : wherein the middle segment is spaced between the first and second conductive structures in a second cross-sectional view, wherein the heater structure is laterally offset from the first and second conductive structures(Fig. 1B, #124 orthogonal to #120 and #124 and #120 may be formed of the same mask [0026]. #124 laterally offset from #120), wherein the second cross-sectional view is taken along a direction substantially orthogonal to a direction of the first cross-sectional view(View from #124 to #124 orthogonal to #120 to #120). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of El-Hinnawy to Slovin form heating elements in the same metal interlayer that are laterally offset to simplify manufacturing (El-Hinnawy [0026]). Regarding claim 27, Slovin as modified by El-Hinnawy discloses : The method of claim 26. Slovin teaches : wherein in a second cross-sectional view the PCE contacts second opposing sidewalls of the thermal barrier structure(Fig. 2a #116 can extend to any size such as #117c, Fig. 4a, #116 contacts #118). Regarding claim 28, Slovin as modified by El-Hinnawy discloses : The method of claim 26. Slovin teaches : wherein the thermal barrier layer is etched to form the first opposing sidewalls before depositing the PCE layer(#116 has high etch selectivity to fluorine-based etchant and may be any size #117a, #117b, and #117c [0028-0029], #118 is formed over #116[0036]). Regarding claim 31, Slovin as modified by El-Hinnawy discloses : The method of claim 26. Slovin teaches : wherein in a second cross-sectional view a width of the thermal barrier structure is greater than a width of the middle segment(Fig. 2a, #116 may be any size #117a, #117b, and #117c with #117a, and #117b having a greater size that #104), wherein the second cross-sectional view is orthogonal to the first cross-sectional view(Fig. 2a is a top view and Fig. 2b is a cross-sectional view). Regarding claim 36, Slovin as modified by El-Hinnawy discloses : The method of claim 26. Slovin teaches : wherein a bottom surface of the heater structure is aligned with bottom surfaces of the first and second conductive structures(Fig. 4c, #108 aligned with #104). Claims 29 and 30 is/are rejected under 35 U.S.C. 103 as being anticipated by Slovin et al, US 20200058853 in view of El-Hinnawy et al, US 20200058848 in further view of Li et al, US 20220285614. Regarding claim 29, Slovin as modified by El-Hinnawy discloses : The method of claim 26. Slovin as modified by El-Hinnawy does not disclose : further comprising: forming a hard mask on the PCE, wherein opposing sidewalls of the hard mask are spaced between the first opposing sidewalls in the first cross-sectional view. However, in the same field of endeavor, Li teaches : further comprising: forming a hard mask on the PCE(Fig. 4, #55 over #43), wherein opposing sidewalls of the hard mask are spaced between the first opposing sidewalls in the first cross-sectional view(#55 formed to be between sidewalls of #41). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Li to Slovin and El-Hinnawy to include a hard mask in a phase change memory device for selective etching of the layers below (Li, [0066]). Regarding claim 30, Slovin as modified by El-Hinnawy and Li discloses : The method of claim 29. Slovin teaches : wherein the heater structure comprises a first outer segment and a second outer segment(Fig. 1a #102 to include outer segments #108 on the left and right of #B-B), wherein the middle segment extends between the first and second outer segments(#106 extending between #108), wherein the thermal barrier structure is laterally offset from the first outer segment and the second outer segment(Fig. 2a, #116 may be size #117c which is shown to be between #102 in positions #108 of Fig. 1a). Claim(s) 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Slovin et al, US 20200058853 in view of Czubatyj et al, US 20070048945. Regarding claim 32, Slovin discloses : A method for forming an integrated chip, comprising: forming a heater structure over a semiconductor substrate(Fig. 1c, #102 over #114), wherein the heater structure comprises a first outer segment, a second outer segment, and a middle segment extending laterally between the first and second outer segments(Fig. 1a, #102 to include #108, #106 and #104), wherein a width of the middle segment is less than widths of the first and second outer segments(#108 have a larger area and may be any size or shape [0020]); forming a first conductive structure and a second conductive structure over the semiconductor substrate and on opposing sides of the middle segment(Fig. 6a, #130 formed on opposing sides of #104); depositing a thermal barrier layer over the heater structure(Fig. 6c , #116 over #102) and the first and second conductive structures(#116 over #108); performing a first etch on the thermal barrier layer to form a thermal barrier structure extending over an upper surface of the middle segment for a first lateral distance(Fig. 2a, #116 has high etch selectivity and can be any size such as #117a, #117b, or #117c where #117c is on an upper surface of #104); depositing a phase change element (PCE) layer over the thermal barrier structure(Fig. 3c, #118 over #116), wherein the first etch is performed before depositing the PCE layer(#118 formed over #116 [0036]); Slovin does not disclose : performing a second etch on the PCE layer to form a PCE extending over the upper surface of the middle segment for a second lateral distance less than the first lateral distance, wherein the PCE interfaces with a top surface of the first conductive structure and a top surface of the second conductive structure. However, in the same field of endeavor, Lin teaches : : performing a second etch on the PCE layer to form a PCE extending over the upper surface of the middle segment for a second lateral distance less than the first lateral distance(Fig. 1, #118 shown to have sloped sidewalls). Therefore, It would have been an obvious matter of design choice to have a PCE layer within a certain distance from a middle segment, since such a modification would have involved a mere change in the size of component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04. Czubatyj teaches : wherein the PCE interfaces with a top surface of the first conductive structure and a top surface of the second conductive structure(Fig. 1a, #750 on a top surface of #630a and #630b). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Czubatyj to Slovin and Lin to have a phase change layer interfacing with a top surface of contacts to provide electrical connection (Czubatyj [0035]). Claim(s) 33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Slovin et al, US 20200058853 in view of Czubatyj et al, US 20070048945 in further view of Shen et al, US 20210296580. Regarding claim 33, Slovin as modified by Czubatyj discloses : The method of claim 32. Slovin as modified by Czubatyj does not disclose : further comprising: forming a hard mask over the PCE, wherein the hard mask contacts opposing sidewalls of the PCE above the thermal barrier structure. However, in the same field of endeavor, Shen teaches : further comprising: forming a hard mask over the PCE, wherein the hard mask contacts opposing sidewalls of the PCE above the thermal barrier structure(Fig. 1, #112 disposed on #108). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Shen to Slovin and Czubatyj to include a hard mask with a PCE for selective patterning (Shen, [0042]). Claim(s) 35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Slovin et al, US 20200058853 in view of Czubatyj et al, US 20070048945 in further view of Yu et al, US 20200136033. Regarding claim 35, Slovin as modified by Czubatyj discloses : The method of claim 32. Slovin as modified by Czubatyj does not disclose : further comprising: forming a sidewall spacer around a perimeter of the PCE, wherein in a first cross- sectional view the sidewall spacer contacts an upper surface of the thermal barrier structure and has outer sidewalls aligned with outer sidewalls of the thermal barrier structure, wherein in a second cross-sectional view the sidewall spacer is laterally offset from the thermal barrier structure and has a bottom surface aligned with a bottom surface of the thermal barrier structure, wherein the first cross-sectional view is orthogonal to the second cross-sectional view. However, in the same field of endeavor, Yu teaches : further comprising: forming a sidewall spacer around a perimeter of the PCE(Fig. 2a, #126 around #120), wherein in a first cross- sectional view the sidewall spacer contacts an upper surface of the thermal barrier structure and has outer sidewalls aligned with outer sidewalls of the thermal barrier structure(#125 aligned with #112). Slovin as modified by Czubatyj and Yu teaches : wherein in a second cross-sectional view the sidewall spacer is laterally offset from the thermal barrier structure and has a lower surface aligned with a lower surface of the thermal barrier structure(Slovin, Fig. 4a, #118 to include sidewalls spacers of Yu in area #126 where the active area of #118 in #126 is aligned with #102), wherein the first cross-sectional view is orthogonal to the second cross-sectional view(Slovin, Fig. 4a, is a top view and Yu, Fig. 10, is a cross-sectional view). Therefore, It would have been an obvious matter of design choice to include with sidewalls spacers of Yu to Slovin and Czubatyj to increase performance, stability, and structural integrity of a PCM cell (Yu [0022]), since such a modification would have involved a mere change in the size of component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVE TAN whose telephone number is (571)272-6841. The examiner can normally be reached M-F: 8-4 PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /D.T./Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Jan 06, 2023
Application Filed
Jan 28, 2026
Non-Final Rejection mailed — §103
Apr 29, 2026
Response Filed
Jul 24, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12740235
DISPLAY DEVICE
3y 11m to grant Granted Sep 15, 2026
Patent 12696675
Quantum Dot Film, Method for Patterning the Quantum Dot Film and Applications thereof
3y 9m to grant Granted Jul 28, 2026
Patent 12677505
DISPLAY DEVICE USING SEMICONDUCTOR LIGHT-EMITTING ELEMENT, AND METHOD FOR MANUFACTURING SAME
3y 10m to grant Granted Jul 07, 2026
Patent 12666527
Thermal Conduction - Electrical Conduction Isolated Circuit Board with Ceramic Substrate and Power Transistor Embedded
3y 8m to grant Granted Jun 23, 2026
Patent 12658397
PHOTOCATHODE INCLUDING NANOSTRUCTURES FOR EXTENDED WAVELENGTHS
3y 6m to grant Granted Jun 16, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

3-4
Expected OA Rounds
81%
Grant Probability
73%
With Interview (-8.3%)
3y 4m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 16 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month