Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Invention III and species II in the reply filed on 11/03/2025 is acknowledged.
Applicant’s cancelation of claims 1-15, addition of claims 21-35, and amendments of claims 16 and 19 in the reply filed on 11/03/2025 is acknowledge.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 16, 17, 19, and 23-25 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Borodulin et al, US 20140264230, hereafter ‘Borodulin’.
Regarding claim 16, Borodulin discloses : A method for forming an integrated chip, the method comprising: forming a heater structure over a semiconductor substrate(Fig. 1, #16 formed over 12); depositing a thermal barrier layer over the heater structure(Fig. 10, #82 over #16); performing a first patterning process on the thermal barrier layer to form a thermal barrier structure over the heater structure(Fig. 11, #160 on #82 [0056]); depositing a phase change element (PCE) layer over the thermal barrier structure(Fig. 14, #170 PCM deposition [0058]); and performing a second patterning process on the PCE layer to form a PCE over the thermal barrier structure(Fig. 15, removing layer #98 to be patterned to #100 of Fig. 16 and finally into #102 of Fig. 23), wherein a length of the thermal barrier structure is greater than a length of the PCE(Fig. 23, #82 shown to be a longer length than #102).
Regarding claim 17, Borodulin discloses : The method of claim 16, wherein the first patterning process is different from the second patterning process(First patterning process may be anisotropic etch [0056] and second patterning process may be chemical [0060]).
Regarding claim 19, Borodulin discloses : The method of claim 16, further comprising: forming a first conductive structure and a second[[RF]]conductive structure over the semiconductor substrate(Fig. 2, #24 and #25), wherein the heater structure is spaced laterally between the first and second [[RF]]conductive structures(#16 between #24 and #25), wherein the heater structure and the first and second [[RF] ]conductive structures are formed concurrently with one another(#24 and #25 may be formed from one metal layer and may be formed from an ohmic contact that is in contact with #16[0038]).
Regarding claim 23, Borodulin discloses : The method of claim 16, wherein the PCE extends along opposing sidewalls of the thermal barrier layer(Fig. 1, #20 within the projection of sidewalls of #18), wherein a lower surface of the PCE is aligned with a lower surface of the thermal barrier layer(#20 on same plane as #18).
Regarding claim 24, Borodulin discloses : The method of claim 16, wherein the thermal barrier layer comprises a non-oxide dielectric material(#18 may be formed of SiN [0035]).
Regarding claim 25, Borodulin discloses : The method of claim 16, wherein a thickness of the PCE is greater than a thickness of the thermal barrier layer(#82 may have a thickness of 1 nm to 500nm [0054] while #PCM may have a thickness of 1 nm to 5 um[0058]).
Claims 26-28 and 31 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Slovin et al, US 20200058853, hereafter ‘Slovin’.
Regarding claim 26, Slovin discloses : A method for forming an integrated chip, comprising: depositing a conductive layer over a semiconductor substrate(RF switch using chemically protective and thermally conductive layer on #114); etching the conductive layer to form a first conductive structure(Fig. 1a, #108), a second conductive structure(#108), and a heater structure(#102), wherein the heater structure comprises a middle segment elongated in a first cross-sectional view(#106 and #104), wherein the middle segment is spaced between the first and second conductive structures(#104 and #106 shown to be in between #108); depositing a first dielectric layer around the heater structure and the first and second conductive structures(#110 shown to surround #104, #106, #108); depositing a thermal barrier layer over the heater structure(Fig. 2c, #116 over #102); etching the thermal barrier layer to form a thermal barrier structure over the heater structure(#116 has high etch selectivity to fluorine-based etchant and may be any size #117a, #117b, and #177c [0028-0029]) ; depositing a phase change element (PCE) layer over the thermal barrier structure and the first and second conductive structures(Fig. 3a, #118); and etching the PCE layer to form a PCE over the thermal barrier structure(#118 may be dry etched [0047]), wherein in the first cross-sectional view opposing sidewalls of the PCE are spaced laterally between first opposing sidewalls of the thermal barrier structure(Fig. 6c, #118 spaced between sidewalls of #116).
Regarding claim 27, Slovin discloses : The method of claim 26, wherein in a second cross-sectional view the PCE contacts second opposing sidewalls of the thermal barrier structure(Fig. 2a #116 can extend to any size such as #117c, Fig. 4a, #116 contacts #118), wherein the second cross-sectional view is orthogonal to the first cross-sectional view(Fig. 2a and Fig. 4a is a top view and Fig. #6c is a cross-sectional view).
Regarding claim 28, Slovin discloses : The method of claim 26, wherein the thermal barrier layer is etched to form the first opposing sidewalls before depositing the PCE layer(#116 has high etch selectivity to fluorine-based etchant and may be any size #117a, #117b, and #117c [0028-0029], #118 is formed over #116[0036]).
Regarding claim 31, Slovin discloses : The method of claim 26, wherein in a second cross-sectional view a width of the thermal barrier structure is greater than a width of the middle segment(Fig. 2a, #116 may be any size #117a, #117b, and #117c with #117a, and #117b having a greater size that #104), wherein the second cross-sectional view is orthogonal to the first cross-sectional view(Fig. 2a is a top view and Fig. 2b is a cross-sectional view).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 18 is/are rejected under 35 U.S.C. 103 as being anticipated by Borodulin et al, US 20140264230, hereafter ‘Borodulin’ in view of Lin et al, US 20200279998, hereafter ‘Lin’.
Regarding claim 18, Borodulin discloses : The method of claim 17.
Borodulin does not disclose : wherein the first patterning process comprises forming a first mask over the thermal barrier layer and the second patterning process comprises forming a second mask over the PCE layer, wherein the first mask is different from the second mask.
However, in the same field of endeavor, Lin teaches : wherein the first patterning process comprises forming a first mask over the thermal barrier layer and the second patterning process comprises forming a second mask over the PCE layer(Fig. 5 and 6, photolithography of #112 [0037] and Fig. 12a, #1202 to form #1218 [0048]), wherein the first mask is different from the second mask(first patterning process may be photolithography and second patterning process may be isotropic etch).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the invention to use different mask for different layers because the known technique of photolithography and isotropic etch was recognized as part of ordinary capabilities of one skilled in the art. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claims 20 and 21 is/are rejected under 35 U.S.C. 103 as being anticipated by Borodulin et al, US 20140264230, hereafter ‘Borodulin’ in view of Li et al, US 20220285614, hereafter ‘Li’.
Regarding claim 20, Borodulin discloses : The method of claim 16.
Borodulin does not disclose : further comprising: forming a sidewall spacer structure along outer opposing sidewalls of the PCE, wherein the sidewall spacer structure continuously extends from a top surface of the thermal barrier structure to the outer opposing sidewalls of the PCE.
However, in the same field of endeavor, Li teaches : further comprising: forming a sidewall spacer structure along outer opposing sidewalls of the PCE(Fig. 7a, #77 formed along #40), wherein the sidewall spacer structure continuously extends from a top surface of the thermal barrier structure to the outer opposing sidewalls of the PCE(#77 extending from a top surface of #11 along #40).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Li to Borodulin to include sidewall space to a phase change memory device to provide thermal conductivity (Li, [0045]).
Regarding claim 21, Borodulin as modified by Li discloses : The method of claim 20.
Li teaches : further comprising: forming a hard mask over the PCE, wherein outer opposing sidewalls of the hard mask are aligned with the outer opposing sidewalls of the PCE(Fig. 7, #55 aligned with #43 of #40), wherein the sidewall spacer structure extends along the outer opposing sidewalls of the hard mask(#77 extends from #11 to top surface of #55).
Claim 22 is/are rejected under 35 U.S.C. 103 as being anticipated by Borodulin et al, US 20140264230, hereafter ‘Borodulin’ in view of Li et al, US 20220285614, hereafter ‘Li’ in further view of Cheng, US 20200411087, hereafter ‘Cheng’.
Regarding claim 22, Borodulin as modified by Li discloses : The method of claim 21.
Borodulin as modified by Li does not disclose : wherein an upper surface of the sidewall spacer structure is vertically below an upper surface of the hard mask.
However, in the same field of endeavor, Cheng teaches : wherein an upper surface of the sidewall spacer structure is vertically below an upper surface of the hard mask(Fig. 15 #606’ shown to be below #604).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Cheng to Borodulin and Li to have sidewall spacers formed below a top surface of a hard mask.
Claims 29 and 30 is/are rejected under 35 U.S.C. 103 as being anticipated by Slovin et al, US 20200058853, hereafter ‘Slovin’ in view of Li et al, US 20220285614, hereafter ‘Li’.
Regarding claim 29, Slovin discloses : The method of claim 26.
Slovin does not disclose : further comprising: forming a hard mask on the PCE, wherein opposing sidewalls of the hard mask are spaced between the first opposing sidewalls in the first cross-sectional view.
However, in the same field of endeavor, Li teaches : further comprising: forming a hard mask on the PCE(Fig. 4, #55 over #43), wherein opposing sidewalls of the hard mask are spaced between the first opposing sidewalls in the first cross-sectional view(#55 formed to be between sidewalls of #41).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Li to Slovin to include a hard mask in a phase change memory device for selective etching of the layers below (Li, [0066]).
Regarding claim 30, Slovin as modified by Li discloses : The method of claim 29.
Slovin teaches : wherein the heater structure comprises a first outer segment and a second outer segment(Fig. 1a #102 to include outer segments #108 on the left and right of #B-B), wherein the middle segment extends between the first and second outer segments(#106 extending between #108), wherein the thermal barrier structure is laterally offset from the first outer segment and the second outer segment(Fig. 2a, #116 may be size #117c which is shown to be between #102 in positions #108 of Fig. 1a).
Claims 32 and 34 is/are rejected under 35 U.S.C. 103 as being anticipated by Slovin et al, US 20200058853, hereafter ‘Slovin’ in view of Borodulin et al, US 20140264230, hereafter ‘Borodulin’.
Regarding claim 32, Slovin discloses : A method for forming an integrated chip, comprising: forming a heater structure over a semiconductor substrate(Fig. 1c, #102 over #114), wherein the heater structure comprises a first outer segment, a second outer segment, and a middle segment extending laterally between the first and second outer segments(Fig. 1a, #102 to include #108, #106 and #104), wherein a width of the middle segment is less than widths of the first and second outer segments(#108 have a larger area and may be any size or shape [0020]); forming a first conductive structure and a second conductive structure over the semiconductor substrate and on opposing sides of the middle segment(Fig. 6a, #130 formed on opposing sides of #104); depositing a thermal barrier layer over the heater structure(Fig. 6c , #116 over #102); performing a first etch on the thermal barrier layer to form a thermal barrier structure extending over an upper surface of the middle segment for a first lateral distance(Fig. 2a, #116 has high etch selectivity and can be any size such as #117a, #117b, or #117c where #117c is on an upper surface of #104); depositing a phase change element (PCE) layer over the thermal barrier structure(Fig. 3c, #118 over #116), wherein the first etch is performed before depositing the PCE layer(#118 formed over #116 [0036]);
Slovin does not disclose : Performing a second etch on the PCE layer to form a PCE extending over the upper surface of the middle segment for a second lateral distance less than the first lateral distance.
However, in the same field of endeavor, Borodulin teaches : Performing a second etch on the PCE layer to form a PCE extending over the upper surface of the middle segment for a second lateral distance less than the first lateral distance(Fig. 22, #102 shown to be inside the lines of #112 and #110).
Therefore, It would have been an obvious matter of design choice to have a PCE layer within a certain distance from a middle segment, since such a modification would have involved a mere change in the size of component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04.
Regarding claim 34, Slovin as modified by Borodulin discloses : The method of claim 32.
Slovin teaches : wherein the PCE contacts an upper surface of the first conductive structure and an upper surface of the second conductive structure(Fig. 6a, #118 in contact with #130 [0060]).
Claim 33 is/are rejected under 35 U.S.C. 103 as being anticipated by Slovin et al, US 20200058853, hereafter ‘Slovin’ in view of Borodulin et al, US 20140264230, hereafter ‘Borodulin’ in further view of Shen et al, US 20210296580, hereafter ‘Shen’.
Regarding claim 33, Slovin as modified by Borodulin discloses : The method of claim 32.
Slovin as modified by Borodulin does not disclose : further comprising: forming a hard mask over the PCE, wherein the hard mask contacts opposing sidewalls of the PCE above the thermal barrier structure.
However, in the same field of endeavor, Shen teaches : further comprising: forming a hard mask over the PCE, wherein the hard mask contacts opposing sidewalls of the PCE above the thermal barrier structure(Fig. 1, #112 disposed on #108).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Shen to Slovin and Borodulin to include a hard mask with a PCE for selective patterning (Shen, [0042]).
Claim 35 is/are rejected under 35 U.S.C. 103 as being anticipated by Slovin et al, US 20200058853, hereafter ‘Slovin’ in view of Borodulin et al, US 20140264230, hereafter ‘Borodulin’ in further view of Yu et al, US 20200136033, hereafter ‘Yu’.
Regarding claim 35, Slovin as modified by Borodulin discloses : The method of claim 32.
Slovin as modified by Borodulin does not disclose : further comprising: forming a sidewall spacer around a perimeter of the PCE, wherein in a first cross- sectional view the sidewall spacer contacts an upper surface of the thermal barrier structure, wherein in a second cross-sectional view the sidewall spacer is laterally offset from the thermal barrier structure and has a lower surface aligned with a lower surface of the thermal barrier structure, wherein the first cross-sectional view is orthogonal to the second cross-sectional view.
However, in the same field of endeavor, Yu teaches : further comprising: forming a sidewall spacer around a perimeter of the PCE(Fig. 10, #126 around #120 [0019]), wherein in a first cross- sectional view the sidewall spacer contacts an upper surface of the thermal barrier structure(#126 may contact #112).
Slovin as modified by Borodulin and Yu teaches : wherein in a second cross-sectional view the sidewall spacer is laterally offset from the thermal barrier structure and has a lower surface aligned with a lower surface of the thermal barrier structure(Slovin, Fig. 4a, #118 to include sidewalls spacers of Yu in area #126 where the active area of #118 in #126 is aligned with #102), wherein the first cross-sectional view is orthogonal to the second cross-sectional view(Slovin, Fig. 4a, is a top view and Yu, Fig. 10, is a cross-sectional view).
Therefore, It would have been an obvious matter of design choice to include with sidewalls spacers of Yu to Slovin and Borodulin to increase performance, stability, and structural integrity of a PCM cell (Yu [0022]), since such a modification would have involved a mere change in the size of component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure : US 11793096 – PCM with thermally conductive material .
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/D.T./Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897