DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Acknowledgement is made of the amendment received on 12/09/2025. Claims 1-9 and 21-31 are pending in this application. Claims 1-4, 7, 21, and 25 are amended. Claim 10 is canceled. Claim 31 is new.
Claim Objections
Claims 1, 4, 10, 16 and 18 are objected to because of the following informalities:
In claim 1, lines 12-14, “wherein a difference in the first thickness and the second thickness is resulted from removing the first implantation mask and the second implantation mask” should read --wherein a difference between the first thickness and the second thickness results from removing the first implantation mask and the second implantation mask-- (emphasis added).
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “forming a first implantation mask over the pad layer and overlapping a first part of the semiconductor substrate” in lines 3-4 and “forming a second implantation mask over the pad layer and overlapping a second part of the semiconductor substrate” in lines 6-7. Thus, the first implantation mask is described as being formed over the pad layer and covering, through the pad layer, the first part of the semiconductor substrate, and the second implantation mask is described as being formed over the pad layer and covering, through the pad layer, the second part of the semiconductor substrate.
However, claim 2 further recites the limitation “performing a first implantation process to implant the first part of the semiconductor substrate with a p-type dopant to form a p-well region, … wherein the first implantation process is performed using the first implantation mask; and performing a second implantation process to implant the second part of the semiconductor substrate with an n-type dopant to form an n-well region, … wherein the second implantation process is performed using the second implantation mask” in lines 2-9 and depends from claim 1.
An implantation mask, as understood by a person of ordinary skill in the art, blocks implantation in the region it covers and permits implantation only in exposed regions. Accordingly, if the first implantation mask overlaps the first part of the semiconductor substrate, implantation would not occur in the first part, but rather in a region not covered by the first implantation mask. The same inconsistency applies to the second implantation mask and the second part.
Therefore, the claim language is internally inconsistent because the first part is described as being covered by the first implantation mask while also being implanted using the same mask. It is unclear whether the first part is covered or exposed during the implantation process. As presently written, the scope of the claimed subject matter cannot be determined with reasonable certainty.
For best understand and examination purpose, the claim will be best considered based on drawings, disclosure, and/or any applicable prior arts; and the claim limitation “forming a first implantation mask over the pad layer and overlapping a first part of the semiconductor substrate” and “forming a second implantation mask over the pad layer and overlapping a second part of the semiconductor substrate” will be interpreted as --forming a first implantation mask over the pad layer and overlapping a second part of the semiconductor substrate-- and --forming a second implantation mask over the pad layer and overlapping a first part of the semiconductor substrate-- in the instant Office Action.
Claims 3-9 are rejected due to their dependency.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 5-10 are rejected under 35 U.S.C. 103 as being unpatentable over Foote, JR. et al. (US 2011/0065256; hereinafter ‘Foote’) in view of Dietze et al. (US 2003/0097977; hereinafter ‘Dietze’) and Ema et al. (US 2005/0110071; hereinafter ‘Ema’).
Regarding claim 1, Foote teaches a method [0030] comprising:
forming a pad layer (610, FIG. 8, [0035]) over a semiconductor substrate (510);
a first portion (left portion of 610; hereinafter ‘FP’) over the first part of a semiconductor substrate (510, which underlines FP; hereinafter ‘FS’), wherein the first portion has a first thickness (thickness of FP; hereinafter ‘T1’); and
a second portion (right portion of 610; hereinafter ‘SP’) over the second part of the semiconductor substrate (510, which underlines SP; hereinafter ‘SS’), wherein the second portion has a second thickness smaller than the first thickness (thickness of SP; hereinafter ‘T2’);
annealing (oxidation process, [0038-0040]) the semiconductor substrate to form a first oxide layer (810 over FS, corresponding to FP; hereinafter ‘FO’) over the first part of the semiconductor substrate, and a second oxide layer (810 over SS, corresponding to SP; hereinafter ‘SO’)over the second part of the semiconductor substrate;
removing the pad layer (removing 610, FIG. 10, [0042])
Foote does not teach the method comprising: forming a first implantation mask over the pad layer and overlapping a first part of the semiconductor substrate; removing the first implantation mask; forming a second implantation mask over the pad layer and overlapping a second part of the semiconductor substrate; removing the second implantation mask, wherein the pad layer comprises: wherein a difference in the first thickness and the second thickness is resulted from removing the first implantation mask and the second implantation mask; removing the pad layer, the first oxide layer, and the second oxide layer; and epitaxially growing a semiconductor layer over and contacting the first part and the second part of the semiconductor substrate.
Dietze teaches a method [0008] comprising:
removing the first oxide layer, and the second oxide layer (removing oxide growth on the surface of the wafer); and
epitaxially growing a semiconductor layer over and contacting the first part and the second part of the semiconductor substrate (epitaxial deposition over a clean silicon surface of the substrate).
As taught by Dietze, one of ordinary skill in the art would utilize and modify the above teaching into Foote to obtain and achieve the method comprising: removing the pad layer, the first oxide layer, and the second oxide layer; and epitaxially growing a semiconductor layer over and contacting the first part and the second part of the semiconductor substrate as claimed, because the removal of the oxide provides a contaminant-free substrate surface with a strong crystallographic structure, thereby facilitating epitaxial deposition and resulting in a higher-quality epitaxial layer [0008].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Dietze in combination with Foote due to above reason.
Foote in view of Dietze does not teach the method comprising: forming a first implantation mask over the pad layer and overlapping a first part of the semiconductor substrate; removing the first implantation mask; forming a second implantation mask over the pad layer and overlapping a second part of the semiconductor substrate; removing the second implantation mask, wherein the pad layer comprises: wherein a difference in the first thickness and the second thickness is resulted from removing the first implantation mask and the second implantation mask.
Ema teaches a method [0194] comprising:
forming a first implantation mask (622, FIG. 23B, [0198]) over the pad layer (602, [0195]) and overlapping a first part of the semiconductor substrate (a first covered part by 622 of 600, [0195]);
forming a second implantation mask (626, FIG. 24A, [0200]) over the pad layer (602) and overlapping a second part of the semiconductor substrate (a second covered part by 626 of 600);
removing the second implantation mask (626, FIG. 24B),
wherein the pad layer (602, FIG. 26A) comprises:
wherein a difference in the first thickness (the first thickness forms on 602 by 622, FIG. 26A) and the second thickness (the second thickness forms on 602 by 626, FIG. 26B) is resulted from removing the first implantation mask and the second implantation mask (shown in FIG. 26C).
Ema does not explicitly describe removing the first implantation mask.
However, Ema discloses forming a second mask 626 after formation of the first mask 622 (FIGS. 26A and 26B). It is well understood in the art that forming a subsequent implantation mask inherently requires removal of any previously formed implantation mask, since a new mask cannot be properly formed, patterned, or aligned on top of an existing target structure.
As taught by Ema, one of ordinary skill in the art would utilize and modify the above teaching into Foote in view of Dietze to obtain and achieve the method comprising: forming a first implantation mask over the pad layer and overlapping a first part of the semiconductor substrate; removing the first implantation mask; forming a second implantation mask over the pad layer and overlapping a second part of the semiconductor substrate; removing the second implantation mask, wherein the pad layer comprises: wherein a difference in the first thickness and the second thickness is resulted from removing the first implantation mask and the second implantation mask as claimed, because high-voltage transistors requires a thicker gate insulating layer than logic transistors, thereby necessitating different insulating layer thicknesses in different regions [0012].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Ema in combination with Foote in view of Dietze due to above reason.
Regarding claim 5, Foote in view of Dietze and Ema teaches the method of claim 5, wherein the annealing is performed using a process gas comprising oxygen therein (Foote: annealing is performed using oxygen, [0038]).
Regarding claim 6, Foote in view of Dietze and Ema teaches the method of claim 1, wherein the annealing is performed when the pad layer covers the semiconductor substrate (Foote: annealing is performed when 610 covers 510, FIG. 8).
Regarding claim 9, Foote in view of Dietze and Ema teaches the method of claim 1, wherein the pad layer, the first oxide layer (Foote: 610 is SiO2, [0035]), and the second oxide layer comprise silicon oxide (810 is SiO2, [0038]).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Foote (US 2011/0065256) in view of Dietze (US 2003/0097977) and Ema (US 2005/0110071), and further in view of Kinney et al. (US 4558508; hereinafter ‘Kinney’).
Regarding claim 2, Foote in view of Dietze and Ema teaches the method of claim 1, but does not teach the method further comprising: performing a first implantation process to implant the first part of the semiconductor substrate with a p-type dopant to form a p-well region, wherein the p-type dopant penetrates through the first portion of the pad layer, and wherein the first implantation process is performed using the first implantation mask; and performing a second implantation process to implant the second part of the semiconductor substrate with an n-type dopant to form an n-well region, wherein the n-type dopant penetrates through the second portion of the pad layer, and wherein the second implantation process is performed using the second implantation mask.
Kinney teaches a method (col. 4, lines 30-32) comprising:
performing a first implantation process (step (9), FIG. 8, col. 5, lines 37-42) to implant the first part of the semiconductor substrate (right part of 12, col. 5, line 34) with a p-type dopant (boron, col. 5, line 25) to form a p-well region (28), wherein the p-type dopant penetrates through the first portion of the pad layer (10, col. 5, line 16), and wherein the first implantation process is performed using the first implantation mask (29, col. 5, lines 32-33); and
performing a second implantation process (step (11), FIG. 10, col. 5, lines 47-55) to implant the second part of the semiconductor substrate (left part of 12) with an n-type dopant (phosphorus or arsenic. col. 4, lines 66-67) to form an n-well region (26), wherein the n-type dopant penetrates through the second portion of the pad layer (32), and wherein the second implantation process is performed using the second implantation mask (14, col. 5, lines 15-16).
As taught by Kinney, one of ordinary skill in the art would utilize and modify the above teaching into Foote in view of Dietze and Ema to obtain and achieve the method further comprising: performing a first implantation process to implant the first part of the semiconductor substrate with a p-type dopant to form a p-well region, wherein the p-type dopant penetrates through the first portion of the pad layer, and wherein the first implantation process is performed using the first implantation mask; and performing a second implantation process to implant the second part of the semiconductor substrate with an n-type dopant to form an n-well region, wherein the n-type dopant penetrates through the second portion of the pad layer, and wherein the second implantation process is performed using the second implantation mask as claimed, because forming dual wells results in adjacent regions of opposite conductivity, which allows independent control of the well profiles and exploitation of their different process responses (col. 3, lines 19-31).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kinney in combination with Foote in view of Dietze and Ema due to above reason.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Foote (US 2011/0065256) in view of Dietze (US 2003/0097977) and Ema (US 2005/0110071), and further in view of Wieczorek et al. (US 2003/0157772; hereinafter ‘Wieczorek’).
Regarding claim 3, Foote in view of Dietze and Ema teaches the method of claim 1, but does not teach the method wherein the second thickness is smaller than the first thickness by the difference in a range between about 0.1 nm and about 3 nm.
Wieczorek teaches a method [0056] wherein the second thickness is smaller than the first thickness by the difference in a range between about 0.1 nm and about 3 nm (dual oxide thickness difference is controllable to 0.2-1.0 nm through process-induced oxide modification and subsequent thinning steps).
As taught by Wieczorek, one of ordinary skill in the art would utilize and modify the above teaching into Foote in view of Dietze and Ema to obtain and achieve the method wherein the second thickness is smaller than the first thickness by a difference in a range between about 0.1 nm and about 3 nm as claimed, because it has been held that where the criticality of the claimed range is not shown and the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Wieczorek in combination with Foote in view of Dietze and Ema due to above reason.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Foote (US 2011/0065256) in view of Dietze (US 2003/0097977) and Ema (US 2005/0110071), and further in view of Nishiguchi et al. (US 2016/0326668; hereinafter ‘Nishiguchi’) and Sommer et al. (29th European Photovoltaic Solar Energy Conference and Exhibition, 830-832, 2014).
Regarding claim 4, Foote in view of Dietze and Ema teaches the method of claim 1, but does not teach the method further comprising, after the semiconductor layer is grown, inspecting the semiconductor layer using Atomic Force Microscope (AFM) image to determine positions of defects of the semiconductor layer, wherein the defects and the first portion and the second portion of the semiconductor substrate are distinguishable from the AFM image.
Nishiguchi teaches a method [0072] further comprising, after the semiconductor layer is grown (after production of sample, [0074]), inspecting the semiconductor layer using Atomic Force Microscope (AFM) image to determine positions of defects of the semiconductor layer (inspecting using AFM, [0078-0079]).
As taught by Kinney, one of ordinary skill in the art would utilize and modify the above teaching into Foote in view of Dietze and Ema to obtain and achieve the method further comprising, after the semiconductor layer is grown, inspecting the semiconductor layer using Atomic Force Microscope (AFM) image to determine positions of defects of the semiconductor layer as claimed, because AFM is a metrology tool that measures the surface morphology of semiconductor layers at nanometer resolution, thereby enabling inspection of surface defects and determination of their positions [0018].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Nishiguchi in combination with Foote in view of Dietze and Ema due to above reason.
Foote in view of Dietze, Ema, and Sommer does not teach the method further comprising, the defects and the first portion and the second portion of the semiconductor substrate are distinguishable from the AFM image.
Sommer teaches a method (ABSTRACT) further comprising, the defects and the first portion and the second portion of the semiconductor substrate are distinguishable from the AFM image (the defects, the p-type, and n-type of the sample are distinguishable from the AFM image, Figures 3 and 6).
As taught by Sommer, one of ordinary skill in the art would utilize and modify the above teaching into Foote in view of Dietze, Ema, and Nishiguchi to obtain and achieve the method further comprising, after the semiconductor layer is grown, inspecting the semiconductor layer using Atomic Force Microscope (AFM) image to determine positions of defects of the semiconductor layer as claimed, because KPFM is a known AFM-based technique capable of spatially resolving surface potential variations corresponding to local doping levels and p-n junction sharpness, and thus routinely used to distinguish p-type and n-type regions and access lateral dopant distribution (1. INTRODUCTION).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Sommer in combination with Foote in view of Dietze, Ema, and Nishiguchi due to above reason.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Foote (US 2011/0065256) in view of Dietze (US 2003/0097977) and Ema (US 2005/0110071), and further in view of Trivedi (US 2005/0020088).
Regarding claim 7, Foote in view of Dietze and Ema teaches the method of claim 1, further comprising forming a first groove in the pad layer (Foote: the upper surface of 610 has a groove, FIG. 8; hereinafter ‘FG’), wherein the first part of the semiconductor substrate (FS) has a first planar top surface (a first planar top surface of FS; hereinafter ‘FST’) contacting the pad layer (610), and the second part of the semiconductor substrate (SS) has a second planar top surface (a first planar top surface of SS; hereinafter ‘SST’) contacting the pad layer (160).
Foote in view of Dietze and Ema does not teach the method further comprising, the first groove extends down into the semiconductor substrate from the first planar top surface and the second planar top surface.
Trivedi teaches a method (FIG. 3, [0027]) further comprising, the first groove (the groove of 31, [0031]) extends down into the semiconductor substrate (10) from the first planar top surface (the right top surface of 10) and the second planar top surface (the left top surface of 10).
As taught by Trivedi, one of ordinary skill in the art would utilize and modify the above teaching into Foote in view of Dietze, and Ema to obtain and achieve the method further comprising, the first groove extends down into the semiconductor substrate from the first planar top surface and the second planar top surface as claimed, because it provides sufficient isolation and reduces leakage between adjacent well regions [0032, 0041, 0047].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Trivedi in combination with Foote in view of Dietze, and Ema due to above reason.
Regarding claim 8, Foote in view of Dietze, Ema, and Trivedi teaches the method of claim 7, further comprising forming a first groove (Foote: the upper surface of 610 has a groove, FIG. 8; hereinafter ‘FG’).
Claims 21 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Kinney (US 4558508) in view of Trivedi (US 2005/0020088).
Regarding claim 21, Kinney teaches a method (col. 4, lines 30-32) comprising:
performing an implantation process (step (9), FIG. 8, col. 5, lines 37-42) to form a first p-well region (28) in a semiconductor substrate (12, col. 5, line 34), wherein the first p-well region comprises a first planar top surface (an upper surface of 28; hereinafter ‘28T’); and
performing an implantation process (step (11), FIG. 10, col. 5, lines 47-55) to form a first n-well region (26) in the semiconductor substrate,
wherein at a time after both of the first p-well region and the first n- well region are formed, the first n-well region comprises a second planar top surface (an upper surface of 26; hereinafter ‘20T’) lower than the first planar top surface by a step height (26T is lower than 28T by 30, FIG. 10), and
wherein the first p-well region and the first n-well region join with each other to form a vertical interface (a vertical interface between 28 and 26).
Kinney does not teach the method comprising: wherein the semiconductor substrate comprises a groove between, and extending lower than, the first planar top surface and the second planar top surface, and wherein the groove comprises a first end joined to the first planar top surface and a second end joined to the second planar top surface.
Trivedi teaches a method (FIGS. 4-6, [0027]) comprising, wherein the semiconductor substrate (10, [0032]) comprises a groove (20) between, and extending lower than, the first planar top surface (the planar top surface of 55, [0034]; hereinafter ‘55T’) and the second planar top surface (the planar top surface of 54; hereinafter ‘54T’), and wherein the groove (20) comprises a first end (the first sidewall of 20 adjoining 55T) joined to the first planar top surface (55T) and a second end (the second sidewall of 20 adjoining 54T) joined to the second planar top surface (54T).
As taught by Trivedi, one of ordinary skill in the art would utilize and modify the above teaching into Foote in view of Kinney to obtain and achieve the method comprising: wherein the semiconductor substrate comprises a groove between, and extending lower than, the first planar top surface and the second planar top surface, and wherein the groove comprises a first end joined to the first planar top surface and a second end joined to the second planar top surface as claimed, because it provides sufficient isolation and reduces leakage between adjacent well regions [0032, 0041, 0047].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Trivedi in combination with Kinney due to above reason.
Regarding claim 25, Kinney in view of Trivedi teaches the method of claim 21 further comprising:
implanting to form a second p-well region (Kinney: a second p-well region formed beneath 42, FIG. 14, col. 6, line 14; hereinafter ‘28R’) in the semiconductor substrate, wherein the second p-well region comprises a third top surface (top surface of 28R); and
implanting to form a second n-well region (a second n-well region formed beneath 40; hereinafter ‘20R’) in the semiconductor substrate,
wherein the second p-well region and the second n-well region join with each other to form an additional vertical interface (a vertical interface between 28R and 26R), and
wherein an additional groove (a groove between 28R and 26R) is formed over and extending to the additional vertical interface (shown in FIG. 14).
Claims 22-24 are rejected under 35 U.S.C. 103 as being unpatentable over Kinney (US 4558508) in view of Trivedi (US 2005/0020088), and further in view of Zhu et al. (US 2023/0187497, cited as equivalent to CN 111584486A; hereinafter ‘Zhu’).
Regarding claim 22, Kinney in view of Trivedi teaches the method of claim 21, but does not teach the method further comprising: forming a dielectric isolation region extending into both of the first p-well region and the first n-well region, wherein the dielectric isolation region overlaps the vertical interface; epitaxially growing a first plurality of semiconductor nanostructures overlapping the first p-well region; forming a first gate stack extending into gaps between the first plurality of semiconductor nanostructures; epitaxially growing a second plurality of semiconductor nanostructures overlapping the first n-well region; and forming a second gate stack extending into gaps between the second plurality of semiconductor nanostructures.
Zhu teaches a method [0011] further comprising:
forming a dielectric isolation region (1049 is a dielectric material, FIG. 13, [0054, 0073]) extending into both of the first p-well region (1003, [0036]) and the first n-well region (1007, [0037]), wherein the dielectric isolation region overlaps the vertical interface (shown in FIG. 13);
epitaxially growing a first plurality of semiconductor nanostructures (1009 and 1013 are nanosheets, FIG. 13, [0041-0042]) overlapping the first p-well region (shown in FIG. 13);
forming a first gate stack (1071 and 1073, FIG. 23, [0092]; hereinafter ‘FGS’) extending into gaps between the first plurality of semiconductor nanostructures (FGS extending into gaps between 1009 and 1013);
epitaxially growing a second plurality of semiconductor nanostructures (1005, 1011, and 1015 are nanosheets) overlapping the first n-well region (shown in FIG. 13); and
forming a second gate stack (1071 and 1075; hereinafter ‘SGS’) extending into gaps between the second plurality of semiconductor nanostructures (FGS extending into gaps between 1011 and 1015).
As taught by Zhu, one of ordinary skill in the art would utilize and modify the above teaching into Kinney in view of Trivedi to obtain and achieve the method further comprising: forming a dielectric isolation region extending into both of the first p-well region and the first n-well region, wherein the dielectric isolation region overlaps the vertical interface; epitaxially growing a first plurality of semiconductor nanostructures overlapping the first p-well region; forming a first gate stack extending into gaps between the first plurality of semiconductor nanostructures; epitaxially growing a second plurality of semiconductor nanostructures overlapping the first n-well region; and forming a second gate stack extending into gaps between the second plurality of semiconductor nanostructures as claimed, because that configuration-combining a dielectric-filled trench at the P/N well boundary, epitaxial stacks with plural nanosheets, and a gate extending into the inter-sheet gaps to surround the channel-is the typical nanosheet GAA integration scheme and a routine design choice.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Zhu in combination with Kinney in view of Trivedi due to above reason.
Regarding claim 23, Kinney in view of Trivedi teaches the method of claim 21, but does not teach the method further comprising: epitaxially growing a first semiconductor layer over and contacting the first p-well region; and epitaxially growing a second semiconductor layer over and contacting the first n-well region.
Zhu teaches a method [0011] further comprising:
epitaxially growing a first semiconductor layer (1009, 1011, and 1013, FIGS. 7 and 10, [0064]; hereinafter ‘FSL’) over and contacting the first p-well region (FSL over and contacting 1003 by 1029 and the left 1005, [0037, 0050]); and
epitaxially growing a second semiconductor layer (1005, 1009, 1011, 1013, and 1015; hereinafter ‘SSL’) over and contacting the first n-well region (SSL over and contacting 1007).
As taught by Zhu, one of ordinary skill in the art would utilize and modify the above teaching into Kinney in view of Trivedi to obtain and achieve the method further comprising: epitaxially growing a first semiconductor layer over and contacting the first p-well region; and epitaxially growing a second semiconductor layer over and contacting the first n-well region as claimed, because selective epitaxial growth directly on the exposed well surface leverages the single-crystal well as a seed to yield lattice-continuous, low-defect layers with predictable electrical and thermal performance [0050].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Zhu in combination with Kinney in view of Trivedi due to above reason.
Regarding claim 24, Kinney in view of Trivedi and Zhu teaches the method of claim 23, Kinney in view of Trivedi does not teach the method wherein the first semiconductor layer comprises a first silicon layer and a silicon germanium layer over and contacting the first silicon layer, and wherein the second semiconductor layer comprises a second silicon layer over and contacting the first n-well region.
Zhu teaches the method wherein the first semiconductor layer comprises a first silicon layer (1009 is Si, [0042]) and a silicon germanium layer (1011 is SiGe) over and contacting the first silicon layer (shown in FIG. 10), and wherein the second semiconductor layer comprises a second silicon layer (1005 is Si) over and contacting the first n-well region (shown in FIG. 10).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Zhu to obtain and achieve the method wherein the first semiconductor layer comprises a first silicon layer and a silicon germanium layer over and contacting the first silicon layer, and wherein the second semiconductor layer comprises a second silicon layer over and contacting the first n-well region as claimed, because Si provides higher electron mobility for n-type devices while SiGe enhances hole mobility for p-type device, and arranging these materials in stacked and contacting layers directly supports complementary device performance [0041-0043].
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Kinney (US 4558508) in view of Trivedi (US 2005/0020088), and further in view of Xu et al. (US 2022/0182043; hereinafter ‘Xu’).
Regarding claim 26, Kinney in view of Trivedi teaches the method of claim 21, further comprising: wherein the top surfaces of the p-well regions are higher than the top surfaces of the n-well regions (Kinney: 28T is higher than 26T, FIG. 10).
Kinney in view of Trivedi does not explicitly teach the method further comprising: forming a plurality of p-well regions; and forming a plurality of n-well regions, each between and joining one of the plurality of p- well regions.
Xu teaches a method (Fig. 1, [0013]) further comprising: forming a plurality of p-well regions (108 and 116, [0014]); and forming a plurality of n-well regions (112 and 120), each between and joining one of the plurality of p-well regions (shown in Fig. 1).
As taught by Xu, one of ordinary skill in the art would utilize and modify the above teaching into Kinney in view of Trivedi to obtain and achieve the method further comprising: forming a plurality of p-well regions; and forming a plurality of n-well regions, each between and joining one of the plurality of p- well regions as claimed, because providing multiple wells enables placement of multiple devices/circuits, thereby increasing the results achievable in parallel compared with a single well structure [0002].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Xu in combination with Kinney in view of Trivedi due to above reason.
Claims 27-31 are rejected under 35 U.S.C. 103 as being unpatentable over Kinney (US 4558508) in view of Xu et al. (US 2022/0182043; hereinafter ‘Xu’).
Regarding claim 27, Kinney teaches a method (col. 4, lines 30-32) comprising:
implanting (step (9), FIG. 8, col. 5, lines 37-42) to form a p-well region (28) in a semiconductor substrate (12, col. 5, line 34), wherein the p-well region comprise first top surface (an upper surface of 28; hereinafter ‘28T’);
implanting (step (11), FIG. 10, col. 5, lines 47-55) to form the n-well regions (26) in the semiconductor substrate,
wherein a n-well region comprises second top surface (an upper surface of 26; hereinafter ‘26T’) lower than the first top surface (26T is lower than 28T, FIG. 10); and
forming a groove (a groove between 28 and 26), between the p-well region and the n-well region (shown in FIG. 10), wherein the groove extends down into the p-well region and the n-well region (the groove extends down into 28 and 26), and bottom of the groove are lower than both of the first top surface and the second top surface (a bottom of groove is lower than 28T and 26T, FIG. 10).
Kinney does not teach the method further comprising: forming a plurality of p-well regions, a plurality of n-well regions, and a plurality of grooves.
Xu teaches a method (Fig. 1, [0013]) further comprising: forming a plurality of p-well regions (108 and 116, [0014]; hereinafter ‘PP’); and forming a plurality of n-well regions (112 and 120; hereinafter ‘PN’), and a plurality of grooves (grooves between PP and PN; hereinafter ‘PG’).
As taught by Xu, one of ordinary skill in the art would utilize and modify the above teaching into Kinney to obtain and achieve the method further comprising: forming a plurality of p-well regions, a plurality of n-well regions, and a plurality of grooves as claimed, because providing multiple wells enables placement of multiple devices/circuits, thereby increasing the results achievable in parallel compared with a single well structure [0002].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Xu in combination with Kinney due to above reason.
Regarding claim 28, Kinney in view of Xu teaches the method of claim 27, wherein each of the grooves is tapered, with upper portions wider than respective lower portions (Kinney: the groove is tapered, with upper portion wider that lower portion, FIG. 10).
Regarding claim 29, Kinney in view of Xu teaches the method of claim 27, Kinney does not teach the method wherein the plurality of p-well regions and the plurality of n-well regions form parallel strips in a top view of the plurality of p-well regions.
Xu teaches the method wherein the plurality of p-well regions and the plurality of n-well regions form parallel strips in a top view of the plurality of p-well regions (PP and PN form parallel strips, Fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Xu to obtain and achieve the method wherein the plurality of p-well regions and the plurality of n-well regions form parallel strips in a top view of the plurality of p-well regions as claimed, because it impedes lateral charge-carrier propagation across adjacent wells-such propagation could otherwise upset multiple storage nodes and corrupt the stored data [0013-0015, 0038].
Regarding claim 30, Kinney in view of Xu teaches the method of claim 27, Kinney does not teach the method wherein the first top surfaces are coplanar with each other, and the second top surfaces are coplanar with each other.
Xu teaches the method wherein the first top surfaces are coplanar with each other (the top surfaces of PP are coplanar with each other, Fig. 1), and the second top surfaces are coplanar with each other (the top surfaces of PN are coplanar with each other).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Xu to obtain and achieve the method wherein the first top surfaces are coplanar with each other, and the second top surfaces are coplanar with each other as claimed, because respective P-wells and N-wells formed using the same implantation and annealing conditions in a common substrate would inherently have substantially uniform and coplanar top surfaces within each conductive type.
Regarding claim 31, Kinney in view of Xu teaches the method of claim 27, further comprising:
performing a first implantation process (Kinney: step (9), FIG. 8, col. 5, lines 37-42) to form the plurality of p-well regions (28), and wherein when the first implantation process is performed, the first top surfaces (an upper surface of 28; hereinafter ‘28T’) contact a pad layer (10, col. 5, line 16); and
performing a second implantation process (step (11), FIG. 10, col. 5, lines 47-55) to form the plurality of n-well regions (26), and wherein when the second implantation process is performed, the first top surfaces (28T) contact the pad layer (10).
Response to Arguments
Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Applicant submits, in pages 9-10 of Remark, that “Since in figure 10 of Kenny, a groove is at bottoms of regions 26 and 28. Examiner has viewed figure 10 upside down. Viewing figure 10 upside down, however, will render the claim element "wherein the plurality of n-well regions comprise second top surfaces lower than the first top surfaces" not to be met since the after turned upside down, the top surfaces of regions 26 and 28 are at the same level. Accordingly, regardless of how figure 10 of Kinney is viewed, Kinney fails to disclose all claim elements of claim 27. Xu fails to cure the deficiency of Kinney. Claim 27 is thus allowable over Kinney and Xu.”.
The examiner respectfully disagrees.
Claim 27 does not recite any absolute orientation or directional limitation for the groove or the wells. The claim merely requires a relative positional relationship between the first top surfaces and the second top surfaces. The claim does not require that “top” correspond to any particular global direction, nor does it restrict how the reference figure must be oriented.
Kinney’s Figure 10 clearly discloses a relative height difference between regions 26 and 28, such that one region has a top surface lower than the other. This relative structural relationship is present irrespective of how the figure is visually oriented. Applicant’s argument improperly introduces a directional limitation that is not recited in the claim.
Accordingly, the examiner maintains that Kinney discloses the claimed relative top surface relationship, and applicant’s orientation-based argument is not persuasive.
Details included in the above rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 3/2/26