DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 15-17, 19-33, and 35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ok et al. (9,595,592 B1) (“Ok”), in view of Wu et al. (US 2020/0105593 A1) (“Wu”), in view of Yamazaki (US 2016/0247928 A1) (“Yamazaki”).
Regarding claim 15, Ok teaches at least in figures 1-11:
forming a channel layer (106) that includes a semiconductor material (106 is a semiconductor layer);
forming a gate stack (detailed below; hereinafter “A”) including a gate electrode (306) and a gate dielectric (310) such that the gate dielectric (310) is disposed between the gate electrode (306) and the channel layer (106);
Forming source/drain contacts (1102).
Ok does not teach:
forming blocking layers on the channel layer such that the blocking layers are spaced apart from each other;
forming buffer layers on the blocking layers, the buffer layers including a material that receives hydrogen; and
forming source/drain contacts respectively on the buffer layers,
wherein the semiconductor material includes indium zinc oxide, indium gallium oxide, indium gallium zinc oxide, tungsten-doped indium oxide, tungsten-doped indium zinc oxide, indium gallium zinc tin oxide, zinc oxide, indium tin oxide, gallium oxide, indium oxide, or combinations thereof, and
wherein a lower surface of one of the source/drain contacts is located at a level higher than a level of an upper surface of the gate dielectric.
Wu teaches at least in figures 1-2G, and Examiner figure 1 below:
forming blocking layers (300/410) on the channel layer (120/140) such that the blocking layers (300/410) are spaced apart from each other (they are so spaced);
forming buffer layers (500) on the blocking layers (300/410), the buffer layers including a material that receives hydrogen (¶ 0042-43, where 500 is reacted with oxygen, and then can absorb hydrogen); and
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forming source/drain contacts (700) respectively on the buffer layers (500), and
wherein a lower surface of one of the source/drain contacts (bottom of 700) is located at a level (dashed line in Examiner figure 1) higher than a level of an upper surface of the gate dielectric (as shown in Examiner figure 1 “an upper surface” of 172 is below the dashed line).
It would have been obvious to one of ordinary skill in the art to combine Ok with Wu because Wu teaches a means to improve the operating characteristics of conductors (i.e. source/drain contacts) especially at ultra small cross-sectional area. ¶ 0015. This means that Wu teaches a means for further miniaturization of the semiconductor devices.
The combination of Ok and Wu do not teach:
wherein the semiconductor material includes indium zinc oxide, indium gallium oxide, indium gallium zinc oxide, tungsten-doped indium oxide, tungsten-doped indium zinc oxide, indium gallium zinc tin oxide, zinc oxide, indium tin oxide, gallium oxide, indium oxide, or combinations thereof.
Yamazaki teaches:
wherein the semiconductor material includes indium zinc oxide, indium gallium oxide, indium gallium zinc oxide, tungsten-doped indium oxide, tungsten-doped indium zinc oxide, indium gallium zinc tin oxide, zinc oxide, indium tin oxide, gallium oxide, indium oxide, or combinations thereof (¶¶ 0007-11, where one can replace the silicon semiconductor layer with an IGZO semiconductor layer).
It would have been obvious to one of ordinary skill in the art to replace the silicon semiconductor layer with the IGZO semiconductor of Yamazaki as Yamazaki teaches that IGZO can be a replacement for silicon, ¶¶ 0007-08, and by replacing silicon for IGZO one can gain the benefit of extremely low leakage current in an off state, and be able to obtain a high-field effect mobility transistor, ¶ 0011. Thus, it would have been obvious to one of ordinary skill in the art to replace one material for a functionally equivalent material and to gain benefits in the swapping of said materials.
Regarding claim 16, Wu teaches at least in figures 1-2G:
wherein the blocking layers (300/410) include titanium nitride, tantalum nitride, titanium, nickel, aluminum, ruthenium, or combinations thereof (¶ 0038).
Regarding claim 17, Wu teaches at least in figures 1-2G:
The prior art does not teach the material of the claim.
However, the prior art teaches a material suitable to perform the same function as the claimed material. See claim 1. Under MPEP 2144.07, because the prior art teaches a material capable of performing the same function it would be suitable for the same intended purpose as the claimed material. Under Sinclair & Carroll Co. v.Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) this supports a prima facie case of obviousness.
Regarding claim 19, Wu teaches at least in figures 1-2G:
wherein the blocking layers (300/410), the buffer layers (500) and the source/drain contacts (700) are formed, after forming the channel layer (120/140), by:
forming a dielectric layer (Wu 160/200; Ok 402) on the channel layer (120/140);
forming trenches in the dielectric layer to expose the channel layer (shown in figure 2A);
forming blocking layers respectively in the trenches; forming buffer layers respectively on the blocking layers and respectively in the trenches (shown in figure 2D); and
forming the source/drain contacts (shown at least in figure 2G) respectively in the trenches so as to permit each of the source/drain contacts to be surrounded by a respective one of the buffer layers and a respective one of the blocking layers (this is shown in figure 2G).
Regarding claim 20, Ok teaches at least in figures 1-11:
wherein the gate stack is formed, after forming the channel layer (figure 2 the channel layer is formed; figure 3 the gate stack is formed), by:
forming a gate dielectric material layer on the channel layer; forming a gate material layer on the gate dielectric material layer; and conducting a patterning process on the gate material layer and the gate dielectric material layer so as to form the gate electrode and the gate dielectric (Col 5 at lines 20-35; This is the tried-and-true, well-known, basic process taught in college, way to form a gate stack for a planar device).
Regarding claim 21, Ok teaches at least in figures 1-11:
Claim 21 is different from claim 15 in that the channel layer is formed on a first dielectric layer, and arguably the channel layer interfaces the blocking layer.
Ok teaches:
forming a first dielectric layer (104);
forming a channel layer (106) on the first dielectric layer (104).
Therefore, the prior art teaches claim 21.
Wu teaches:
The channel layer (120) interfaces the blocking layer (at least 410 of 300/410) (The term “interfaces” can be where two elements communicate or interact with each other, or are connected together. It does not mean that the elements have to be directly contacting to each other. The term “interfaces” allows for a plurality of elements to be between the two elements interfacing together. As shown above Wu teaches this as at least 410 of 300/410 interfaces with the channel 120 by means of the plurality of elements between them.).
Regarding claim 22, Ok teaches at least in figures 1-11:
wherein formation of the channel layer (106) includes:
forming a channel material layer on the dielectric layer, and patterning the channel material layer, so as to form the channel layer (Co. 4 at lines 17-53).
Regarding claim 23, Ok teaches at least in figures 1-11:
Claim 23 contains the same subject matter as claim 20 above, and is rejected for the same reasons as claim 20 above.
Regarding claim 24, Ok teaches at least in figures 1-11:
Claim 24 contains the subject matter that reads on claim 19 above, and is rejected for the same reasons as claim 19 above.
Regarding claims 25-27, Ok teaches at least in figures 1-11:
The limitations of claims 25-27 are shown in figures 2B-2G.
Regarding claims 28-29, Ok teaches at least in figures 1-11:
wherein the portions of the metal layer, the portions of the buffer material layer, and the portions of the blocking material layer are removed simultaneously (¶ 0057, where CMP is used to remove all the layers in figure 2G at the same time. Further, CMP is a planarization technique as already known to Applicant, and disclosed in Wu.).
Regarding claim 30,
Claim 30 is different from claim 21 in that claim 30 requires a first dielectric material layer, and a second dielectric material layer. As Examiner understand it the first dielectric material layer is the supplemental dielectric layer 27 shown in Applicant’s figures, and the second dielectric material layer is element 28.
Ok teaches:
forming a first dielectric material layer (206/208/210) on the first dielectric layer (104),
the first dielectric material layer (206/208/210) laterally covering the channel layer (106),
wherein the first dielectric material layer (206/208/210) has a side surface (A), and
the channel layer (106) has a side surface which interfaces (A) the side surface of the first dielectric material layer (206/208/210) and (the and here refers to the channel layer and not the interface) [the channel layer] (106) which has a height (C/D) the same as a height of the side surface of the first dielectric material layer (B/D) (See Examiner figure 2); and
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forming a second dielectric material layer (402) on the channel layer (106),
the first dielectric material layer (206/208/210) and the gate stack (A),
wherein the second dielectric material layer (402) is formed after formation of the first dielectric material layer (206/208/210) (the second dielectric material layer is formed after the first dielectric material layer as it is formed on top of it).
Therefore, the prior art in teaches the limitations of claim 30.
Regarding claim 31, Ok teaches at least in figures 1-11:
Claim 31 contains the same subject matter as claim 20 above, and is rejected for the same reasons as claim 20 above.
Regarding claim 32, Ok teaches at least in figures 1-11:
Claim 32 contains the subject matter that reads on claim 19 above, and is rejected for the same reasons as claim 19 above.
The amendments to claim 32 are shown in figures 3-5.
Regarding claim 33, Ok teaches at least in figures 1-11:
The limitations of claim 33 are shown in figures 2B-2G.
Regarding claim 34, Ok teaches at least in figures 1-11:
wherein the second dielectric material layer (402) interfaces the channel layer (A) (this is shown in at least figure 11).
Response to Arguments
Applicant's arguments filed April 14, 2026 have been fully considered but they are not persuasive.
Regarding claim 15,
As shown in the analysis of claim 15 above, the claim does limit the gate dielectric to have only one upper surface. Thus, there can be multiple upper surfaces. Because of this, as shown in Examiner figure 1, the prior art teaches this limitation.
Regarding claim 21,
Applicant asserts the prior art does not teach the “channel layer interfaces the blocking layers”. This is unpersuasive for the reasons explained in the analysis of claim 21 above. As previously stated, the term “interfaces” is very broad, and allows for a plurality of layers to be the “interface” layers. The claim does not require direct connection. Therefore, this limitation was, and is, taught by the prior art.
Regarding claim 30,
Applicant asserts the prior art does not teach the side surface of the channel layer interfaces with the side surface of the first dielectric material layer, and the channel layer has the same height as the first dielectric material layer. This is unpersuasive for the reasons stated in the analysis of claim 30 above. It would appear that Applicant is interpreted the clause “and which has a height the same as a height of the side surface of the first dielectric material layer” to mean the side surface of the first dielectric material layer. However, another reading of the clause in conjunction with the entire limitation is that the “and” refers back to the channel layer and not the side surface of the first dielectric material layer. Based upon this reading the prior art continues to read upon the claim.
Conclusion
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/VINCENT WALL/Primary Examiner, Art Unit 2898
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