DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
No amendments were submitted in the applicant’s response dated 16 December 2025. Claims 6, 7, and 13 were previously withdrawn and claims 16-20 were cancelled.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 8, 10-12, 14, and 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al (US 20210028217 A1, hereinafter “Cho”), in view of Fujimagari (WO 2020100520 A1, hereinafter “Fujimagari”).
Regarding Claim 1 – Cho discloses a semiconductor device, comprising: a primary circuit chip (200 [0031]); an image sensor chip (100 [0031]) having a backside illuminated (BSI) surface (SCa [0027]) and a frontside surface (location of 107 [0038]) opposed to the BSI surface, the image sensor chip being disposed on the primary circuit chip with the frontside surface facing the primary circuit chip (107 facing 207 [0050]).
Cho fails to disclose an auxiliary chip disposed on the BSI surface of the image sensor chip and connected to the primary circuit chip through the image sensor chip.
However, Fujimagari discloses an auxiliary chip (60 [0044]) disposed on the BSI surface of the image sensor chip (10 [0044]) and connected to the primary circuit chip (50 [0044]) through the image sensor chip (by way of via 72 [0045]).
Fujimagari is analogous to Cho because both involve sensor chip stacks with backside illumination. Fujimagari teaches placing the auxiliary chip 60 on the backside surface, on pad 34, thereby decoupling the connection pattern of the auxiliary chip from the wiring pattern on the front surface, and enabling the formation of vias in any position. This decoupling allows a desired wiring pattern to be formed on the front surface for area efficiency (explained for first embodiment, Fujimagari [0040], and applied to second embodiment with auxiliary chip with same benefit [0047]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Fujimagari and Cho to place an auxiliary chip on the light receiving side of the sensor chip to enable circuit area efficiency.
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Regarding Claim 2 – Cho modified by Fujimagari discloses all the limitations of claim 1.
The combination of Cho and Fujimagari further discloses a color filter array (CFA) (CFA, Cho [0032]) and microlens array (MLA, Cho [0031]) disposed on the BSI surface adjacent to the auxiliary chip (MLA on 100, Cho [0031]).
Regarding Claim 3 – Cho modified by Fujimagari discloses all the limitations of claim 2.
The combination of Cho and Fujimagari further discloses at least one glass support (DM [0027]) disposed on the BSI surface and adjacent to the auxiliary chip (Cho Fig. 2); and glass (400 [0027]) disposed on the at least one glass support and positioned above the CFA and the microlens array (Cho Fig. 2), and defining a cavity (GAP [0027]) between the glass, the at least one glass support, and the BSI surface, with the CFA and the microlens array disposed within the cavity (Cho Fig. 2).
Regarding Claim 8 – Cho modified by Fujimagari discloses all the limitations of claim 1.
The combination of Cho and Fujimagari further discloses at least one solder bump (SP, Cho [0033]) with the primary circuit chip disposed thereon (Cho Fig. 2); and a through Silicon via (TSV) (TSV, Cho [0033]) with a redistribution layer (RDL) (RDL, Cho [0033]) formed therein that extends through the primary circuit chip (Cho [0033]) and connects the auxiliary chip to the at least one solder bump (TSV 72 connects aux. chip 60 to primary chip 50 RDL in Fujimagari [0045] and TSV connects primary chip 200 RDL further to bump SP in Cho [0033]).
Regarding Claim 10 – Cho modified by Fujimagari discloses all the limitations of claim 1.
The combination of Cho and Fujimagari further discloses the auxiliary chip includes at least one of a dynamic random access memory (DRAM) chip or an artificial intelligence (AI) chip (Fujimagari allows for broad range of options for the functional chip, Fujimagari [0046], and Cho specifically mentions an auxiliary chip, memory chip 300, may be DRAM, Cho [0069]).
Regarding Claim 11 – Cho discloses a semiconductor device, comprising: a primary circuit chip (200 [0031]); an image sensor chip (100 [0031]) having a backside illuminated (BSI) surface (SCa [0027]) and a frontside surface (location of 107 [0038]) opposed to the BSI surface, the image sensor chip being disposed on the primary circuit chip with the frontside surface facing the primary circuit chip (107 facing 207 [0050]); a color filter array (CFA) (CFA, Cho [0032]) and microlens array (MLA, Cho [0031]) disposed on the BSI surface (MLA on 100, Cho [0031]); and glass (400 [0027]) positioned above the CFA and the microlens array (Fig. 2).
Cho fails to disclose an auxiliary chip disposed on the BSI surface of the image sensor chip and adjacent to the CFA and microlens array and connected to the primary circuit chip through the image sensor chip.
However, Fujimagari discloses an auxiliary chip (60 [0044]) disposed on the BSI surface of the image sensor chip (10 [0044]) and adjacent to the CFA (CFA, annotated Fujimagari Fig. 4) and microlens array (MLA, annotated Fujimagari Fig. 4) and connected to the primary circuit chip (50 [0044]) through the image sensor chip (by way of via 72 [0045]).
Fujimagari is analogous to Cho because both involve sensor chip stacks with backside illumination. Fujimagari teaches placing the auxiliary chip 60 on the backside surface, on pad 34, thereby decoupling the connection pattern of the auxiliary chip from the wiring pattern on the front surface, and enabling the formation of vias in any position. This decoupling allows a desired wiring pattern to be formed on the front surface for area efficiency (explained for first embodiment, Fujimagari [0040], and applied to second embodiment with auxiliary chip with same benefit [0047]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Fujimagari and Cho to place an auxiliary chip on the light receiving side of the sensor chip to enable circuit area efficiency.
Regarding Claim 12 – Cho modified by Fujimagari discloses all the limitations of claim 11.
The combination of Cho and Fujimagari further discloses at least one glass support (DM, Cho [0027]) disposed on the BSI surface (SCa, Cho [0027] and Fig. 2) and adjacent to the auxiliary chip (in the periphery of sensor chip, Fujimagari Fig. 4), with the glass (400, Cho [0027]) disposed thereon.
Regarding Claim 14 – Cho modified by Fujimagari discloses all the limitations of claim 11.
The combination of Cho and Fujimagari further discloses at least one solder bump (SP, Cho [0033]) with the primary circuit chip disposed thereon (Cho Fig. 2); and a through Silicon via (TSV) (TSV, Cho [0033]) with a redistribution layer (RDL) (RDL, Cho [0033]) formed therein that extends through the primary circuit chip (Cho [0033]) and connects the auxiliary chip to the at least one solder bump (TSV 72 connects aux. chip 60 to primary chip 50 RDL in Fujimagari [0045] and TSV connects primary chip 200 RDL further to bump SP in Cho [0033]).
Regarding Claim 21 – Cho discloses a semiconductor device, comprising: a primary circuit chip (200 [0031]); an image sensor chip (100 [0031]) disposed on the primary circuit chip (in contact [0031]) ; a color filter array (CFA) (CFA [0032]) and microlens array (MLA [0031]) disposed on the image sensor chip (MLA on 100 [0031]); and glass (400 [0027]) positioned above the CFA and the microlens array (Fig. 2).
Cho fails to disclose an auxiliary chip disposed on the image sensor chip and adjacent to the CFA and microlens array and connected to the primary circuit chip through the image sensor chip.
However, Fujimagari discloses an auxiliary chip (60 [0044]) disposed on the BSI surface of the image sensor chip (10 [0044]) and adjacent to the CFA (CFA, annotated Fujimagari Fig. 4) and microlens array (MLA, annotated Fujimagari Fig. 4) and connected to the primary circuit chip (50 [0044]) through the image sensor chip (by way of via 72 [0045]).
Fujimagari is analogous to Cho because both involve sensor chip stacks with backside illumination. Fujimagari teaches placing the auxiliary chip 60 on the backside surface, on pad 34, thereby decoupling the connection pattern of the auxiliary chip from the wiring pattern on the front surface, and enabling the formation of vias in any position. This decoupling allows a desired wiring pattern to be formed on the front surface for area efficiency (explained for first embodiment, Fujimagari [0040], and applied to second embodiment with auxiliary chip with same benefit [0047]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Fujimagari and Cho to place an auxiliary chip on the light receiving side of the sensor chip to enable circuit area efficiency.
Regarding Claim 22 – Cho modified by Fujimagari discloses all the limitations of claim 21.
The combination of Cho and Fujimagari further discloses the image sensor chip has a backside illuminated (BSI) surface (top surface SCa [0031]) and a frontside surface opposed to the BSI surface (bottom surface includes interconnects to attach to primary circuit chip [0050]), the image sensor chip is disposed on the primary circuit chip with the frontside surface facing the primary circuit chip (107 facing 207 [0050]), and the auxiliary chip is disposed on the BSI surface of the image sensor chip (Fujimagari [0044] and Fig. 4).
Regarding Claim 23 – Cho modified by Fujimagari discloses all the limitations of claim 21.
The combination of Cho and Fujimagari further discloses at least one glass support (DM, Cho [0027]) disposed on the image sensor chip and adjacent to the auxiliary chip (in the periphery of sensor chip, Fujimagari Fig. 4), wherein the glass is disposed on the at least one glass support and positioned above the CFA and the microlens array (Cho [0027] and Fig. 2), and defines a cavity between the glass (GAP, Cho [0027]), the at least one glass support, and the image sensor chip, with the CFA and the microlens array disposed within the cavity (Cho Fig. 2).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Cho et al (US 20210028217 A1, hereinafter “Cho”), in view of Fujimagari (WO 2020100520 A1, hereinafter “Fujimagari”), and further in view of Kim (US 20210050377 A1, hereinafter “Kim1”).
Regarding Claim 4 – Cho modified by Fujimagari discloses all the limitations of claim 3.
The combination of Cho and Fujimagari fails to disclose the at least one glass support is anti-reflective.
However, Kim discloses the at least one glass support (JS, Kim1 [0023]) is anti-reflective (Kim1 [0023]).
Kim presents a very similar semiconductor sensor device to Cho’s device with glass, a glass support, and an air gap above the inner sensor. Kim teaches the glass support (JS) maybe anti-reflective to prevent reflected light being incident on the pixel region (Kim1 [0023]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to use anti-reflective material in the glass support for the well-known advantage of preventing reflected incident light from reaching the image sensor.
Claims 5 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al (US 20210028217 A1, hereinafter “Cho”), in view of Fujimagari (WO 2020100520 A1, hereinafter “Fujimagari”), and further in view of Okada (WO 2012165647 A1, hereinafter “Okada”).
Regarding Claim 5 – Cho modified by Fujimagari discloses all the limitations of claim 3.
The combination of Cho and Fujimagari fails to disclose the at least one glass support extends around a perimeter of the BSI surface with at least one pressure release opening formed therein and sized to release air pressure from the cavity while preventing moisture from entering the cavity.
However, Okada discloses the at least one glass support (5, Okada [0019] and Figs. 1A-1C) extends around a perimeter of the BSI surface (Okada Fig. 1A) with at least one pressure release opening (8, Okada [0019] and Figs. 1A and 1C) formed therein and sized to release air pressure from the cavity while preventing moisture from entering the cavity (moisture released when internal pressure greater than external before sealing again, Okada [0028] and [0033]).
Okada is analogous to Cho and Fujimagari, because he discloses a semiconductor sensor device with an air gap. Okada discloses a vent hole for the advantage of releasing of moisture vapor while preventing moisture from the outside from coming into the air gap (Okada [0011]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Okada, Cho, and Fujimagari to implement a vent hole in the semiconductor sensor device, allowing air pressure to escape the air gap while not allowing moisture contamination in.
Regarding Claim 24 – Cho modified by Fujimagari discloses all the limitations of claim 23.
The combination of Cho and Fujimagari fails to disclose the at least one glass support extends around a perimeter of the image sensor chip with at least one pressure release opening formed therein and sized to release air pressure from the cavity while preventing moisture from entering the cavity.
However, Okada discloses the at least one glass support (5, Okada [0019] and Figs. 1A-1C) extends around a perimeter of the BSI surface (Okada Fig. 1A) with at least one pressure release opening (8, Okada [0019] and Figs. 1A and 1C) formed therein and sized to release air pressure from the cavity while preventing moisture from entering the cavity (moisture released when internal pressure greater than external before sealing again, Okada [0028] and [0033]).
Okada is analogous to Cho and Fujimagari, because he discloses a semiconductor sensor device with an air gap. Okada discloses a vent hole for the advantage of releasing of moisture vapor while preventing moisture from the outside from coming into the air gap (Okada [0011]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Okada, Cho, and Fujimagari to implement a vent hole in the semiconductor sensor device, allowing air pressure to escape the air gap while not allowing moisture contamination in.
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Claims 9, 15, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al (US 20210028217 A1, hereinafter “Cho”), in view of Fujimagari (WO 2020100520 A1, hereinafter “Fujimagari”), and further in view of Kim et al (US 20220367553 A1, hereinafter “Kim2”).
Regarding Claim 9 – Cho modified by Fujimagari discloses all the limitations of claim 1.
The combination of Cho and Fujimagari fails to disclose the auxiliary chip is connected to the primary circuit chip through the image sensor chip using a through Silicon via (TSV) with a hybrid bond.
However, Kim2 discloses the auxiliary chip (third semiconductor chip 400’, Kim2 [0128]) is connected to the primary circuit chip (first semiconductor chip 200, Kim2 [0022]) and the image sensor chip (second semiconductor chip 300, Kim2 [0022]) using a through Silicon vias (TSV) (230, Kim2 [0066]) with hybrid bonds (424, Kim2 [0128]). These can be arranged with the third chip on the sensor chip as taught by Fujimagari.
Kim2 is analogous to Cho and Fujimagari in that a sensor device is presented as a stack of interconnected chips. Kim2 teaches connecting multiple chips with hybrid bonding for the advantages of structural stability and improved electrical properties (Kim2 [0130-0131]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Kim2, Cho, and Fujimagari for the well-known benefits of structural stability and improved electrical properties.
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Regarding Claim 15 – Cho modified by Fujimagari discloses all the limitations of claim 11.
The combination of Cho and Fujimagari fails to disclose the auxiliary chip is connected to the primary circuit chip through the image sensor chip using a through Silicon via (TSV) with a hybrid bond.
However, Kim2 discloses the auxiliary chip (third semiconductor chip 400’, Kim2 [0128]) is connected to the primary circuit chip (first semiconductor chip 200, Kim2 [0022]) and the image sensor chip (second semiconductor chip 300, Kim2 [0022]) using a through Silicon vias (TSV) (230, Kim2 [0066]) with hybrid bonds (424, Kim2 [0128]). These can be arranged with the third chip on the sensor chip as taught by Fujimagari.
Kim2 is analogous to Cho and Fujimagari in that a sensor device is presented as a stack of interconnected chips. Kim2 teaches connecting multiple chips with hybrid bonding for the advantages of structural stability and improved electrical properties (Kim2 [0130-0131]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Kim2, Cho, and Fujimagari for the well-known benefits of structural stability and improved electrical properties.
Regarding Claim 25 – Cho modified by Fujimagari discloses all the limitations of claim 21.
The combination of Cho and Fujimagari fails to disclose the auxiliary chip is connected to the primary circuit chip through the image sensor chip using a through Silicon via (TSV) with a hybrid bond.
However, Kim2 discloses the auxiliary chip (third semiconductor chip 400’, Kim2 [0128]) is connected to the primary circuit chip (first semiconductor chip 200, Kim2 [0022]) and the image sensor chip (second semiconductor chip 300, Kim2 [0022]) using a through Silicon vias (TSV) (230, Kim2 [0066]) with hybrid bonds (424, Kim2 [0128]). These can be arranged with the third chip on the sensor chip as taught by Fujimagari.
Kim2 is analogous to Cho and Fujimagari in that a sensor device is presented as a stack of interconnected chips. Kim2 teaches connecting multiple chips with hybrid bonding for the advantages of structural stability and improved electrical properties (Kim2 [0130-0131]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Kim2, Cho, and Fujimagari for the well-known benefits of structural stability and improved electrical properties.
Response to Arguments
Applicant's arguments filed 16 December 2025 have been fully considered but they are not persuasive. The applicant asserts that Cho teaches away from the inclusion of TSVs through the sensor chip, and placement of an auxiliary chip on the backside illuminated surface of the sensor chip. The examiner respectfully disagrees that Cho teaches away from the above-described modification of Cho by Fujimagari.
Argument A – Cho discourages the modification of a via extending through the image sensor chip to connect an auxiliary chip disposed on the BSI surface.
Regarding Argument A – Cho teaches TSV connections may be formed in the logic chip 200 ([0033]), and may extend into the sensor chip 100 ([0041]). Further, Cho teaches a through electrode TSV may not extend into the substrate portion of the sensor chip in the case that the sensor pixels are placed in the center region. The word –may-- in this case can be interpreted as --might not--, indicating the possibility still exists that a TSV could extend through the substrate portion of the sensor chip. After the example of a TSV not extending through the sensor substrate in the pixel region, Cho states the inventive concept is not limited to this feature ([0042]). Although Cho goes on to use an example of some or all of the TSVs being disposed in a region overlapping the pixel region in a plan view ([0042]), this does not preclude the case that a TSV extends through the sensor substrate outside the pixel region, as Fujimagari teaches. In addition, Cho’s Fig. 2 can be interpreted as displaying space for the auxiliary chip adjacent to the microlens array, in the vicinity of the glass supports as in the instant application. The combination of Cho and Fujimagari referenced above is a combination of known elements from the prior art, making it a prior prima facie case of obviousness. See MPP 2143(I)(A).
Argument B – The applicant states that Cho discloses a conductive pad for connecting to an external memory chip should not be placed adjacent to a CFA/microlens array, citing the embodiment of Fig. 8 as an example.
Regarding Argument B – The conductive pad referred to by Cho is for wire bonding from the sensor chip, which is outside the embodiment of the combination of Cho and Fujimagari referenced above. Cho, in fact, goes on to reiterate that using TSVs and ball bonds instead of wire bonding improves the signal transfer speed of the device. However, the embodiment of figure 8 as referenced in paragraphs [0067-0070] is different from the embodiment used in the above office action, and not representative. It shows the auxiliary chip placed on the opposite side of the stack compared with the claimed invention, and is not referenced in the office action. “(T)he prior art’s mere disclosure of more than one alternative does not constitute a teaching away from any of these alternatives because such disclosure does not criticize, discredit, or otherwise discourage the solution claimed…." In re Fulton, 391 F.3d 1195, 1201, 73 USPQ2d 1141, 1146 (Fed. Cir. 2004). See MPEP 2141.02(VI).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 7:30a-5p Eastern, alternating Fridays out of office.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898