DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 15, 16, 19-22 and 24-27 have been considered but are moot on grounds of new rejection and interpretation of the current prior art.
Applicant’s arguments, see pages 1-2, filed March 5, 2026, with respect to claim 8 have been fully considered and are persuasive. The rejection of claims 8-12 and 14 has been withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 15, 16 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (Chen’415) (DE 10 2020128415 A1).
In regards to claim 15, Chen’415 (Figs. 1A-8 and associated text) discloses a method of manufacturing a semiconductor device comprising: bonding a first semiconductor die (items 22) to a first carrier substrate (items 20), the first semiconductor die (items 22) comprising: a first interconnect structure (items 30), a first semiconductor substrate (items 24) over the first interconnect structure (items 30); and through substrate vias (items 26) extending from the first interconnect structure (items 30) through the first semiconductor substrate (items 24); bonding a second semiconductor die (items 46) to the first semiconductor die (items 22), the second semiconductor die (items 46) comprising: a second interconnect structure (items 50), and a second semiconductor substrate (items 48) over the second interconnect structure (items 50); encapsulating the second semiconductor die (items 46) in a molding compound (items 56); depositing a silicon layer (item 58, silicon oxide, silicon nitride, silicon oxynitride or the like) over the molding compound (items 56) and the second semiconductor die (items 46); bonding a second carrier substrate (items 60) to the silicon layer (item 58, silicon oxide, silicon nitride, silicon oxynitride or the like); and performing a debonding process to release the first carrier substrate (items 20) from the first semiconductor die (items 22). Examiner notes that Applicant has not defined what “a silicon layer” layer is. Therefore the Examiner takes the position the any layer that contains silicon can be construed as “a silicon layer”.
In regards to claim 16, Chen’415 (Figs. 1A-8 and associated text) discloses following the debonding process, exposing a conductive contact pad (item 40) of the first interconnect structure (item 30); and forming an under-bump metallization (item 63) in contact with the conductive contact pad (item 40).
In regards to claim 19, Chen’415 (Figs. 1A-8 and associated text) discloses wherein the bonding the second semiconductor die (item 46) to the first semiconductor die (item 22) further comprises bonding contact pads (item 54) of the second interconnect structure (item 50) to metal bond pads (item 45), the metal bond pads (item 45) being in direct physical contact with the through substrate vias (item 26) and electrically coupling the first semiconductor die (item 22) to the second semiconductor die (item 46).
In regards to claim 21, Chen’415 (Figs. 1A-8 and associated text) discloses a method of manufacturing a semiconductor device, the method comprising: bonding a first semiconductor package (item 22) to a second semiconductor package (item 46) using a bonding layer (items 44 plus 45, 52 plus 54 or 44 plus 45 plus 52 plus 54) between the first semiconductor package (item 22) and the second semiconductor package (item 46), the first semiconductor package (item 22) comprising a first interconnect structure (item 30) on a first semiconductor substrate (item 24) and through substrate vias (item 26) electrically coupled to the first interconnect structure (item 30) extending through the first semiconductor substrate (item 24), the second semiconductor package (item 46) comprising a second semiconductor substrate (item 48) and a second interconnect structure (item 50) on the second semiconductor substrate (item 48); after bonding the first semiconductor package (item 22) to the second semiconductor package (item 46), forming a silicon layer (item 58) on a side of the second semiconductor package (items 46) that is opposite to the first semiconductor package (item 22); and bonding a heat dissipation structure (item 60) to the silicon layer (item 58). Examiner notes that Applicant has not defined what “a silicon layer” layer is. Therefore the Examiner takes the position the any layer that contains silicon can be construed as “a silicon layer”.
In regards to claim 25, Chen’415 (Figs. 1A-8 and associated text) discloses wherein the second semiconductor package (item 46) further comprises an insulating buffer layer (item 61) on the second semiconductor substrate (item 48), the insulating buffer layer (item 61) being in direct physical contact with the silicon layer (item 58).
In regards to claim 27, Chen’415 (Figs. 1A-8 and associated text) discloses wherein the first semiconductor package (item 22) is directly bonded to the second semiconductor package (item 46) by a bonding layer (items 44 plus 45, 52 plus 54 or 44 plus 45 plus 52 plus 54), the bonding layer (items 44 plus 45, 52 plus 54 or 44 plus 45 plus 52 plus 54) comprising active bonding pads (items 45, 54) and dummy pads (outermost item 45).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (Chen’415) (DE 10 2020128415 A1).
In regards to claim 22, Chen’415 does not specifically disclose wherein the silicon layer has a thickness in a range from 1mm to 6 mm.
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include a silicon layer having a thickness in a range from 1mm to 6 mm, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)). Examiner note that the Applicant has not given any criticality as to where the specific values within this range yields and unexpected result or advantage.
Claim(s) 20 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (Chen’415) (DE 10 2020128415 A1) in view of Chou (US 2012/0049299 A1).
In regards to claim 20, Chen’415 does not specifically disclose wherein bonding the second carrier substrate comprises bonding a metal layer directly to the silicon layer, wherein the metal layer contacts the second carrier substrate.
Chou (paragraph 31, Fig. 3 and associated text) discloses wherein bonding the second carrier substrate (item 320) comprises bonding a metal layer (item 324) directly to the silicon layer (item 306), wherein the metal layer (item 324) contacts the second carrier substrate (item 320).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Chou for the purpose of adequate bonding layers a metal-to-semiconductor bond (paragraph 31).
In regards to claim 24, Chen’415 does not specifically disclose wherein the heat dissipation structure includes a metal bonding layer, wherein bonding the heat dissipation structure includes directly bonding the metal bonding layer to the silicon layer.
Chou (paragraph 31, Fig. 3 and associated text) discloses wherein the heat dissipation structure (item 320 plus 324) includes a metal bonding layer (item 324, paragraph 31), wherein bonding the heat dissipation structure (item 320 plus 324) includes directly bonding the metal bonding layer (item 324) to the silicon layer (item 306).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Chou for the purpose of adequate bonding layers a metal-to-semiconductor bond (paragraph 31).
Claim(s) 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (Chen’415) (DE 10 2020128415 A1) in view of Cheng et al. (Cheng) (US 2021/0183844 A1).
In regards to claim 26, Chen’415 does not specifically disclose wherein the second semiconductor package further comprises a plurality of dummy dies, the dummy dies adjacent to the second semiconductor substrate.
Cheng (Figs. 3A-3D and associated text) wherein the second semiconductor package (item 150) further comprises a plurality of dummy dies (item 130), the dummy dies (item 130) adjacent to the second semiconductor substrate (substrate of item 120).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Cheng for the purpose of improving the mechanical strength of the package (paragraph 14).
Allowable Subject Matter
Claims 8-12 and 14 are allowed.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm.
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 April 16, 2026
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