DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on 11/11/25 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 21-28 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
With respect to claim 21, it is claimed a structure wherein a first substrate has a first interconnect OVER it, and then a first bonding layer OVER the first interconnect structure, wherein a portion of the first substrate OVERHANGS the first bonding layer. See Applicant’s Figure 16 marked up below, using the definition of the layers found in the specification as taught. Note that the layers are inverse of what is claimed. What is claimed is not taught in the specification nor the figures, namely, the layers claimed are not disclosed to be OVER each other, in fact, the disclosure teaches the opposite of this order. It is believed that the claim should read in this specific order for the written description requirement to be met: a first bonding layer; a first interconnect structure over the first bonding layer; a first substrate over the first interconnect layer, wherein a first portion of the first substrate overhangs the first bonding layer.
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Claims 22-28 depend upon rejected claim 21 and do not overcome this deficiency and thus stand rejected.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al US 2022/0367407.
Pertaining to claim 1, Lin teaches an integrated circuit package comprising:
a first integrated circuit die 52 comprising:
a first substrate 64;
a first interconnect structure 54 on a front side of the first substrate; and
a first bonding layer (top portion of 52 see [0016] where the reference describes element 52 to include devices ie integrated circuits and they are surrounded by an ILD layer, which can be considered the “bonding layer” as that is what goes on to interface with layer 164) on the first interconnect structure 54, the first interconnect structure 54 being between the first bonding layer (top portion of 52 see [0016] as stated above) and the first substrate 64;
an insulating layer along sidewalls of the first integrated circuit die see [0016] which describes ILD layer surrounding devices; and
a second integrated circuit die 152 bonded to the first integrated circuit die 52, the second integrated circuit die comprising:
a second substrate 154;
a second interconnect structure (connection elements marked up in Figure 20 below within layer 158) on a front side of the second substrate; and
a second bonding layer 164 on the second interconnect structure, the second interconnect structure being between the second bonding layer 164 and the second substrate 154, wherein a first surface of the first bonding layer 52S is in direct contact with a first surface of the second bonding layer 164, wherein a sidewall of the first bonding layer 52S and the first surface of the second bonding layer 164 form a first acute angle See Figure 20 marked up below.
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Pertaining to claim 6, Lin teaches the integrated circuit package of claim 1, wherein a portion of the first substrate 64 adjacent the front side of the first substrate is recessed from a sidewall of the first interconnect structure 54 see Figure 20 a portion of which marked up below.
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Pertaining to claim 21, Lin teaches an integrated circuit package comprising:
a first integrated circuit die 52 comprising:
a first substrate 64;
a first interconnect structure 54 over the first substrate; and
a first bonding layer (top portion of 52 see [0016] where the reference describes element 52 to include devices ie integrated circuits and they are surrounded by an ILD layer, which can be considered the “bonding layer” as that is what goes on to interface with layer 164) over the first interconnect structure 54, wherein a first portion of the first substrate overhangs the first bonding layer;
an encapsulant encircling the first integrated circuit die see [0016] which describes ILD layer surrounding devices; and
a second integrated circuit die 152 bonded to the first integrated circuit die 52, the second integrated circuit die comprising:
a second substrate 154;
a second interconnect structure (connection elements marked up in Figure 20 below within layer 158) over the second substrate; and
a second bonding layer 164 over the second interconnect structure, the second interconnect structure being between the second bonding layer 164 and the second substrate 154, wherein a first surface of the first bonding layer 52S is bonded to a first surface of the second bonding layer 164
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 7 and 8 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tsai et al US 2023/0411326 .
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Pertaining to claim 7, Tsai teaches an integrated circuit package comprising:
a first integrated circuit die 200 comprising:
a first bonding layer 112;
a first substrate 204b; and
a first interconnect structure 212 between the first bonding layer 112 and the first substrate 204b, wherein the first interconnect structure comprises a first surface facing the first substrate See Figure 4; and
an encapsulant 120/124 (can be a two part two material encapsulant) along sidewalls of the first integrated circuit die 200, wherein the encapsulant contacts the first surface of the first interconnect structure 210. See Figure 6 marked up below
Pertaining to claim 8, Tsai teaches the integrated circuit package of claim 7, wherein the first bonding layer 112 extends laterally beyond a sidewall of the first substrate 204b and wherein a distal portion of the first substrate overhangs the first bonding layer See Figure 6 marked up below.
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Allowable Subject Matter
Claims 2-5, 9-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Pertaining to claims 2 and 12, the prior art does not teach wherein the acute angle is less than 30 degrees, teaching instead an acute angle between 80 and 90 degrees
Pertaining to claim 3, the prior art does not teach nor suggest either alone or in combination using recast material on sidewalls of the first substrate, interconnect structure and bonding layer (See Applicants Figure 12).
Pertaining to claim 9, the prior art does not teach nor suggest alone nor in combination wherein the first bonding layer comprises a sidewall adjacent to the first interconnect structure, wherein the first bonding layer comprises a second surface facing the first substrate, and wherein the sidewall of the first bonding layer and a line perpendicular to the second surface of the first bonding layer form a first acute angle in combination with the encapsulant layer as claimed in claim 7.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS J TOBERGTE whose telephone number is (571)272-6458. The examiner can normally be reached M-F 7:30-4:30.
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/NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817