Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-10, in the reply filed on 10/08/2025 is acknowledged. Additionally, new claims 21-30 have been elected.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 28-30 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. It is not clear how the step following “depositing a first metal layer” are tied to the first metal layer, since top portion and sidewall portions do not refer back to the first metal layer.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 2025/0353735 (735). Although the claims at issue are not identical, they are not patentably distinct from each other.
Regarding claim 1, (735) discloses a method comprising: forming an interconnect structure over a semiconductor substrate, wherein the interconnect structure comprises a plurality of dielectric layers, and wherein the interconnect structure and the semiconductor substrate are comprised in a wafer; forming a plurality of metal pads over the interconnect structure; forming a plurality of through-holes penetrating through the wafer, wherein the plurality of through-holes comprise: top portions penetrating through the interconnect structure; and middle portions underlying and joining to the top portions, wherein the middle portions are wider than respective ones of the top portions; and forming a first metal layer electrically connected to the plurality of metal pads, wherein the first metal layer extends into the top portions of the plurality of through-holes (claim 3).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 21 and 28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al., US 2015/0175406.
Regarding claim 1, Lin discloses (fig. 1 and related text) a method comprising: forming an interconnect structure (118) over a semiconductor substrate (120, [0016]), wherein the interconnect structure (110) comprises a plurality of dielectric layers (117, IMD), and wherein the interconnect structure and the semiconductor substrate (120) are comprised in a wafer (140); forming a plurality of metal pads (127) over the interconnect structure (110); forming a plurality of through-holes penetrating through the wafer, wherein the plurality of through-holes (124/125) comprise: top portions (top portions of 118) penetrating through the interconnect structure (110); and middle portions (closer to 127) underlying and joining to the top portions (124/125 are joined top to bottom), wherein the middle portions are wider (124/125 are wider going from 118 towards 127) than respective ones of the top portions (124/125 closer to 118) ; and forming a first metal layer (the meta inside via 124/125) electrically connected to the plurality of metal pads (127), wherein the first metal layer extends into the top portions of the plurality of through-holes (the metal inside 124/125 near 118, fig. 1).
Regarding claim 21, Lin discloses (fig. 1 and related text) a method comprising: forming an interconnect structure (110) over a semiconductor substrate (120), wherein the interconnect structure comprises a plurality of dielectric layers (IMD, 117); forming a plurality of metal pads (127) over the interconnect structure (110), wherein the plurality of metal pads (127) are electrically connected to the interconnect structure (through 118); forming a plurality of through-holes (124/125, eventually filed with metal layer) penetrating through the interconnect structure (110) and the semiconductor substrate (120, [0016]), wherein the plurality of through-holes comprise (124/125): top portions (portions of 124/125 near 118) penetrating through the interconnect structure (110); and middle portions (portions of 124/125 closer to 127) underlying and joining to the top portions (fig. 1), wherein the middle portions are wider than respective top portions (refer to fig. 1); and depositing a first metal layer (metal layer filling the via 124/125), wherein the first metal layer is electrically connected to the plurality of metal pads (127), and wherein the first metal layer extends into the top portions of the plurality of through-holes (the metal layer is formed inside 124/125).
Regarding claim 28, as best the examiner is able to ascertain the claimed invention, Lin discloses a method comprising: forming a plurality of dielectric layers (117, IMD) over a semiconductor substrate (120); forming a plurality of through-holes (via 124/125) penetrating through the plurality of dielectric layers (117) and the semiconductor substrate (120), wherein the plurality of through-holes comprises: top portions (portions of 124/125 closer to 118) penetrating through the plurality of dielectric layers (IMD); and middle portions (portions of 124/125 closer to 127) under and joining to the top portions (fig. 1), wherein bottom widths of the top portions (portion of 124/125 closer to 127) are greater than top widths of the middle portions; and depositing a first metal layer (filling via 124/125) comprising: a top portion (top portion of the metal inside 124/125) overlapping the plurality of dielectric layers; and sidewall (portion of the metal inside 124/125) portions extending into the top portions of the plurality of through-holes (extend inside 124/125).
Allowable Subject Matter
Claims 2-10 and 22-27 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL A GEBREMARIAM whose telephone number is (571)272-1653. The examiner can normally be reached 8:30-4PM.
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/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811