DETAILED ACTION
This Office action responds to Applicant’s amendments filed on 12/11/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The present Office action is made with all previously suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-16, and 21-22.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, and 9 rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2021/0407942) in view of West (US 2021/0305178).
Regarding claim 1, Yu shows (see, e.g., Yu: figs. 1A-1B, and 2-6) all aspects of the instant invention including a method of forming a semiconductor package, comprising:
Forming first active components 54 on a first semiconductor wafer 50
Forming over the first active components 54, using a dual damascene process, a first interconnect structure 60 including first stacked layers of metal lines 62/65A/67A/65B/67B embedded within respective dielectric layers 63A/63B (see, e.g., Yu: par. [0022])
Further forming, using a dual damascene process, a conductive via 66 and a bonding contact pad 66 (both are denoted by the element 66, being parts common to the same element), the bonding contact pad 66 being embedded at least partially in a first bonding dielectric layer 64/68 (see, e.g., Yu: par. [0032] – [0033]), the conductive via 66 electrically connecting the bonding contact pad 66 and a top metal line 62 of the first stacked layers 62/65A/67A/65B/67B
Forming on a second semiconductor wafer 70 a second interconnect structure 80 comprising second stacked layers of second metal lines 92/80 embedded in respective second dielectric layers 80
Further forming, using a single damascene process, a bonding via 96 at least partially embedded in a second bonding dielectric layer 94/98 (see, e.g., Yu: par. [0040] and par. [0033]; Yu shows in par. [0033] that elements 66 and 96 can be made with both (single) damascene process and dual damascene process)
wherein:
The bonding via 96 has a bottom surface physically contacting a topmost one of the second metal lines 92/80, a topmost surface, and side walls connecting the bottom surface and the top surface
Aligning the bonding via 96 and the bonding contact pad 66 to form a bonding interface (see, e.g., Yu: par. [0042])
Bringing the first bonding dielectric layer 64/68 into contact with the second bonding dielectric layer 94/98 (see, e.g., Yu: par. [0042])
Bonding the first bonding dielectric layer 64/68 to the second bonding dielectric layer 94/98 (see, e.g., Yu: par. [0042])
Bonding the bonding via 96 to the bonding contact pad 66 (see, e.g., Yu: par. [0041])
Yu, however, fails (see, e.g., Yu: figs. 1A-1B, and 2-6) to specify that the bonding via 96 has a width of the bonding via 96, measured in a direction perpendicular to the major plane of the first semiconductor wafer 50 that is free from steps from the topmost surface to the bottommost surface.
West, in a similar device to Yu, shows (see, e.g., West: fig. 1) that that bonding via 154/164/174 has a width of the bonding via 154/164/174, measured in a direction perpendicular to the major plane of the first semiconductor wafer 101 that is free from steps from the topmost surface to the bottommost surface. West, further shows that the bonding vias that the bonding vias 154/164/174 that has a width of the bonding via 154/164/174, measured in a direction perpendicular to the major plane of the first semiconductor wafer 101 that is free from steps from the topmost surface to the bottommost surface serve as conductive vias in the multilevel metallization structures and provide a Faraday cages around isolation elements (see, e.g., West: par. [0025], and [0018]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include bonding via of West that the bonding via that has a width of the bonding via, measured in a direction perpendicular to the major plane of the first semiconductor wafer that is free from steps from the topmost surface to the bottommost surface, in method of Yu, to serve as conductive vias in the multilevel metallization structures and provide a Faraday cages around isolation elements.
Also, Yu fails (see, e.g., Yu: figs. 1A-1B, and 2-6) to shows that the bonding via 96 has a width of the bonding via 96, measured in a direction perpendicular to the major plane of the first semiconductor wafer 50 that is free from steps from the topmost surface to the bottommost surface. However, it is noted that the specification fails to provide teachings about the criticality of having the bonding via free from steps from the topmost surface to the bottommost surface, as claimed in the instant application.
Therefore, absent any criticality, this limitation is only considered to be an obvious modification of the shape of the bonding via structure 96 disclosed by Yu as the courts have held that a change in shape or configuration, without any criticality, is within the level of skill in the art, and the particular bonding via free from steps from the topmost surface to the bottommost surface claimed by applicant is nothing more than one of numerous contour shapes that a person having ordinary skill in the art will find obvious to provide using routine experimentation as a matter of choice or based on its suitability for the intended use of the invention. See In re Daily, 149 USPQ 47 (CCPA 1976).
Furthermore, the claimed bonding via free from steps from the topmost surface to the bottommost surface is known in the art: West, in the same field of endeavor, teaches (see, e.g., West: fig. 1) that the bonding via free from steps from the topmost surface to the bottommost surface.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the bonding via free from steps from the topmost surface to the bottommost surface of Yu, because the bonding via free from steps from the topmost surface to the bottommost surface is known in the semiconductor art to have free-from-steps profile for its use as bonding vias similarly used for in instant invention and West, as suggested by West, and implementing a known structure shape for its conventional use/purpose would have been a common sense choice by the skilled artisan. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Yu in view of West shows (see, e.g., West: fig. 1) that the bonding via 154/164/174 has a first contact surface area at the bonding interface, and the bonding contact pad 152/162/172 has a second contact surface area greater than the first contact surface area at the bonding interface.
Regarding claim 2, Yu in view of West shows (see, e.g., Yu: figs. 1A-1B, and 2-6) that the top metal line 62 of the first stacked layers 62/65A/67A/65B/67B is embedded within the first bonding dielectric layer 64/68.
Regarding claim 3, Yu in view of West shows (see, e.g., Yu: figs. 1A-1B, and 2-6) that the top metal line 62 of the first stacked layers 62/65A/67A/65B/67B is embedded within an interconnect structure dielectric layer 64/68 and further wherein the first bonding dielectric layer 64/68 is deposited on the interconnect structure dielectric layer 64/68.
Regarding claim 9, Yu in view of West shows (see, e.g., Yu: figs. 1A-1B, and 2-6) that the bonding contact pad 66 is bonded to the bonding via 96 simultaneously with bonding the first bonding dielectric layer 64/68 to the second bonding dielectric layer 94/98 (see, e.g., Yu: par. [0041]).
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of West in further view of Ishikawa (US 2022/0336394).
Regarding claims 4 and 5, Yu in view of West shows (see, e.g., Yu: figs. 1A-1B, and 2-6) most aspects of the instant invention including a bonding via 96 and a bonding contact pad 66.
Yu in view of West, however, fails (see, e.g., Yu: figs. 1A-1B, and 2-6) to specify that the bonding via 96 has a first dimension in a direction perpendicular to the major plane of the first semiconductor wafer, the bonding contact pad 66 has a second dimension in the direction perpendicular to the major plane of the first semiconductor wafer, and wherein a ratio of the first dimension to the second dimension is at least 2:1 and wherein a ratio of the first dimension to the second dimension is at least 20:1.
Ishikawa, in a similar device to Yu in view of West, shows (see, e.g., Ishikawa: fig. 40A-40C) that the second metallic bonding structure 728 is provided by forming a stepped cavity in which the bonding via 728P has a first dimension vd1’ in a direction perpendicular to the major plane of the first semiconductor wafer, and the bonding contact pad 728V has a second dimension vd2’ in the direction perpendicular to the major plane of the first semiconductor wafer (see, e.g., Ishikawa: par. [0439], and [0447]). Ishikawa shows that the first vertical dimension vd1′ is greater than the second vertical dimension vd2′, giving a ratio of vd1′/ vd2′ > 1.
Ishikawa also shows that the metallic surfaces of the bonding pads are vertically recessed prior to bonding because the bonding pads thermally expand during the bonding process, and precise recess depth control is desired to ensure that the thermally expanded metallic surfaces and the surfaces of the pad-level dielectric layers line up at a horizontal bonding interface (see, e.g., Ishikawa: par. [0150]). Ishikawa teaches that if the recess depth of the bonding pads is too great, bonding between the bonding pads is hampered because the facing pairs of bonding pads do not contact each other (i.e., a void is formed between the bonding pads) while the pad-level dielectric layers are bonded to each other (see, e.g., Ishikawa: par. [0150]). Ishikawa further shows that if the recess depth of the bonding pad is too small, facing pairs of bonding pads protrude above the physically exposed surfaces of the pad-level dielectric layers and degrade bonding between the pad-level dielectric layers (i.e., a void is formed between the dielectric layers) (see, e.g., Ishikawa: par. [0150]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the first dimension of the bonding via and the second dimension of the bonding contact pad of Ishikawa in method of Yu in view of West, to precisely control the recess depth, which is desired to ensure that the thermally expanded metallic surfaces and the surfaces of the pad-level dielectric layers line up at a horizontal bonding interface.
However, the differences in the ratios of first dimension of the bonding via to the second dimension of the bonding contact pad will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see next paragraph below) of the mentioned ratios, and Ishikawa has identified such ratios as a result-effective variables subject to optimization, it would have been obvious to one of ordinary skill in the art to use these ratio values in the method of Yu in view of West.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed ratio values or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claims 6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of West in further view of Chiu (US 9299649).
Regarding claim 6, Yu in view of West shows (see, e.g., Yu: figs. 1A-1B, and 2-6) most aspects of the instant invention including a bonding via 96 and a bonding contact pad 66.
Yu in view of West, however, fails (see, e.g., Yu: figs. 1A-1B, and 2-6) to specify that the bonding contact pad 66 has a shape, from a top-down view, selected from the group consisting of round and rectangular, and further wherein the bonding via 96 has a second shape, from a top-down view, selected from the group consisting of round and rectangular. Chiu, in a similar method to Yu in view of West, shows (see, e.g., Chiu: figs. 2A-2B) that the bonding contact pad 36 has a shape, from a top-down view, selected from the group consisting of round and rectangular, and further wherein the bonding via 40 has a second shape, from a top-down view, selected from the group consisting of round and rectangular. Chiu also teaches that the bonding contact pad 36 and the bonding via 40 is part of an aligned interconnecting structure that electrically connects various devices and substrates (see, e.g., Chiu: col.3/II.17-25, and col.5/II.1-9).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the rectangular bonding via and the rectangular bonding contact pad of Chiu in method of Yu in view of West, to manufacture a part of an aligned interconnecting structure that electrically connects various devices and substrates.
Yu in view of West in view of Chiu also shows (see, e.g., Chiu: figs. 2A-2B) that the bonding via 40 has a cross-sectional shape selected from the group consisting of tapered and non-tapered.
Regarding claim 8, Yu in view of West shows (see, e.g., Yu: figs. 1A-1B, and 2-6) most aspects of the instant invention including a bonding via 96.
Yu in view of West, however, fails (see, e.g., Yu: figs. 1A-1B, and 2-6) to specify that the bonding via 96 a plurality of bonding vias. Chiu, in a similar method to Yu in view of West, shows (see, e.g., Chiu: figs. 2A-2B) that the bonding via 40 has a plurality of bonding vias 40A/40B. Chiu also teaches that the plurality of bonding vias 40A/40B is part of an aligned interconnecting structure that electrically connects various devices and substrates (see, e.g., Chiu: col.3/II.17-25, and col.5/II.1-9) and to improve the integration density that comes from repeated reductions in minimum feature size, which allows more components to be integrated into a given area (see, e.g., Chiu: col.1/II.6-13)
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the rectangular bonding via and the rectangular bonding contact pad of Chin in method of Yu in view of West, to manufacture a part of an aligned interconnecting structure that electrically connects various devices and substrates, and to improve the integration density that comes from repeated reductions in minimum feature size, which allows more components to be integrated into a given area.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of West in further view of Abraham (US 2018/0331058).
Regarding claim 7, Yu in view of West shows (see, e.g., Yu: figs. 1A-1B, and 2-6) most aspects of the instant invention including a first semiconductor wafer 50 and a second semiconductor wafer 70.
Yu in view of West, however, fails (see, e.g., Yu: figs. 1A-1B, and 2-6) to teach the method step of at least one of backside thinning the first semiconductor wafer, backside thinning the second semiconductor wafer, and backside thinning both the first and the second semiconductor wafer.
Abraham, in a similar device to Yu in view of West, teaches (see, e.g., figs. 1-6) a method step of thinning a wafer (see, e.g., par. [0046]). Abraham also that the thickness of the wafers that have circuitry elements (see, e.g., [0028]) defines the length of the through-substrate-via, which in generally configured along with the via diameter to provide a certain aspect ratio of the through-substrate-via (see, e.g., [0046]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the method step of Abraham of thinning a wafer in the method of Yu in view of West to define the length of the through-substrate-via, which in generally configured along with the via diameter to provide a certain aspect ratio of the through-substrate-via.
Claims 10, 12, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2021/0407942) in view of Chen (US 2015/0171050).
Regarding claim 10, Yu shows (see, e.g., Yu: figs. 1A-1B, and 2-6) most aspects of the instant invention including a method of forming a semiconductor package, comprising:
Forming on a first semiconductor wafer 50 a bonding contact pad 66 embedded within a first bonding dielectric layer 64/68, and an underlying via 67B, the bonding contact pad 66 extending a first dimension in a first direction perpendicular to the first semiconductor wafer 50 and a second dimension in a second direction parallel to the plane of the first semiconductor wafer 50, wherein topmost surface of the bonding contact pad 66 has a first contact surface area
Forming on a second semiconductor wafer 70 a second bonding dielectric layer 94/98 having embedded therein a bonding via 96, the bonding via 96 extending a third dimension in the first direction and extending a fourth dimension in the second direction, wherein the third dimension is at least twice the fourth dimension
wherein:
A topmost surface of the bonding via 96 has a second contact area
The first contact surface area is greater than the second contact surface area
Planarizing the first bonding dielectric layer 64/68, the bonding contact pad 66, or both, so that a topmost surface of the bonding contact pad 66 is substantially planar with a topmost surface of the first bonding dielectric layer 64/68 (see, e.g., Yu: par. [0033])
Aligning the bonding via 96 and the bonding contact pad 66 (see, e.g., Yu: par. [0042])
Bonding the bonding via 96 to the bonding contact pad 66 (see, e.g., Yu: par. [0041])
Yu, however, fails (see, e.g., Yu: figs. 1A-1B, and 2-6) to specify that the second dimension is at least twice the second dimension is at least twice the first dimension and the third dimension is at least twice the fourth dimension. Chen, in a similar device to Yu, shows (see, e.g., Chen: figs. 7) that the second metallic bonding structure 118 is provided with a bonding via 118 that has a first dimension H2 in a direction perpendicular to the major plane of the first semiconductor wafer and a second dimension W1 in a second direction parallel to the plane of the first semiconductor wafer, and the bonding contact pad 118 that has a third dimension H3 in the direction perpendicular to the major plane of the first semiconductor wafer and a fourth direction W2 parallel to the plane of the first semiconductor plane (see, e.g., Chen: par. [0034] – [0035]). Horizontal dimensions W1 and W2 may be a length/width, diameter, or the like depending on a top-down shape of conductive pad 118 (see, e.g., Chen: par. [0034]). Chen further shoes that the horizontal dimensions W1 and W2 are between about 0.1 µm and about 10 µm, and vertical dimensions H2 and H3 may be between about 0.1 µm and about 1 µm. (see, e.g., Chen: par. [0034] – [0035]). Thus, there is a combination of dimensions where the second dimension is at least twice the first dimension, and the third dimension is at least twice the fourth dimension.
Chen also shows that in simulations where conductive pad 118 comprises copper and the dimensions of W1, W2, H2, and H3 are 1 µm, 0.5 µm, 0.5 µm, and 1 µm, respectively, the thermal stress at the surface of conductive pad 118 is
4.938
x
10
-
5
Newtons. However, in simulations where the dimensions of W1, W2, H2, and H3 were 1 µm, 0 µm, 0.5 µm, and 0 µm, respectively, (e.g., where the metallic material was uniformly distributed), the surface stress of the conductive pad was higher at
5.977
x
10
-
5
Newtons (see, e.g., Chen: par. [0036)]). Chen also shows that the reduction of surface stress reduces the probability of forming voids, particularly in corner regions 118B, during subsequent bonding processes. Chen further shows that the shape and dimensions of conductive pad 118 reduces the overall surface stress of conductive pad 118 (see, e.g., Chen: par. [0036)]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the first and second dimensions of the bonding via and the third and fourth dimensions of the bonding contact pad of Chen in method of Yu, to reduce the overall surface stress of conductive pad.
However, the differences in the dimensions of the bonding via and the bonding contact pad will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see next paragraph 22) of the mentioned dimensions, and Chen has identified such dimensions as a result-effective variables subject to optimization, it would have been obvious to one of ordinary skill in the art to use these dimension values in the method of Yu.
Regarding claim 12, Yu in view of Chen shows (see, e.g., Yu: figs. 1A-1B, and 2-6) that bonding contact pad 66 and the underlying via are formed together in a dual damascene process, and further wherein the bonding via 96 is formed in a single damascene process (see, e.g., Yu: par. [0040] and par. [0033]; Yu shows in par. [0033] that elements 66 and 96 can be made with both (single) damascene process and dual damascene process).
Regarding claim 16, Yu in view of Chen shows (see, e.g., Yu: figs. 1A-1B, and 2-6) that the underlying via 67B is also embedded within the first bonding dielectric layer64/68.
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Chen in further view of Ishikawa (US 2022/0336394).
Regarding claims 13 and 14, Yu in view of Chen shows (see, e.g., Yu: figs. 1A-1B, and 2-6) most aspects of the instant invention including a bonding via 96 and a bonding contact pad 66.
Yu in view of Chen, however, fails (see, e.g., Yu: figs. 1A-1B, and 2-6) to specify that the bonding via 96 has a first dimension in a direction perpendicular to the major plane of the first semiconductor wafer, the bonding contact pad 66 has a second dimension in the direction perpendicular to the major plane of the first semiconductor wafer, and wherein a ratio of the first dimension to the second dimension is at least 2:1 and wherein a ratio of the first dimension to the second dimension is at least 20:1.
Ishikawa, in a similar device to Yu in view of Chen, shows (see, e.g., Ishikawa: fig. 40A-40C) that the second metallic bonding structure 728 is provided by forming a stepped cavity in which the bonding via 728P has a first dimension vd1’ in a direction perpendicular to the major plane of the first semiconductor wafer, and the bonding contact pad 728V has a second dimension vd2’ in the direction perpendicular to the major plane of the first semiconductor wafer (see, e.g., Ishikawa: par. [0439], and [0447]). Ishikawa shows that the first vertical dimension vd1′ is greater than the second vertical dimension vd2′, giving a ratio of vd1′/ vd2′ > 1.
Ishikawa also shows that the metallic surfaces of the bonding pads are vertically recessed prior to bonding because the bonding pads thermally expand during the bonding process, and precise recess depth control is desired to ensure that the thermally expanded metallic surfaces and the surfaces of the pad-level dielectric layers line up at a horizontal bonding interface (see, e.g., Ishikawa: par. [0150]). Ishikawa teaches that if the recess depth of the bonding pads is too great, bonding between the bonding pads is hampered because the facing pairs of bonding pads do not contact each other (i.e., a void is formed between the bonding pads) while the pad-level dielectric layers are bonded to each other (see, e.g., Ishikawa: par. [0150]). Ishikawa further shows that if the recess depth of the bonding pad is too small, facing pairs of bonding pads protrude above the physically exposed surfaces of the pad-level dielectric layers and degrade bonding between the pad-level dielectric layers (i.e., a void is formed between the dielectric layers) (see, e.g., Ishikawa: par. [0150]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the first dimension of the bonding via and the second dimension of the bonding contact pad of Ishikawa in method of Yu in view of Chen, to precisely control the recess depth, which is desired to ensure that the thermally expanded metallic surfaces and the surfaces of the pad-level dielectric layers line up at a horizontal bonding interface.
However, the differences in the ratios of first dimension of the bonding via to the second dimension of the bonding contact pad will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see next paragraph below) of the mentioned ratios, and Ishikawa has identified such ratios as a result-effective variables subject to optimization, it would have been obvious to one of ordinary skill in the art to use these ratio values in the method of Yu in view of Chen.
Claim 15 a rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Chen in view of Chiu (US 9299649).
Regarding claim 15, Yu in view of Chen shows (see, e.g., Yu: figs. 1A-1B, and 2-6) most aspects of the instant invention including a bonding via 96 and a bonding contact pad 66.
Yu in view of Chen, however, fails (see, e.g., Yu: figs. 1A-1B, and 2-6) to specify that the bonding contact pad 66 has a shape, from a top-down view, selected from the group consisting of round and rectangular, and further wherein the bonding via 96 has a second shape, from a top-down view, selected from the group consisting of round and rectangular. Chiu, in a similar method to Yu in view of Chen, shows (see, e.g., Chiu: figs. 2A-2B) that the bonding contact pad 36 has a shape, from a top-down view, selected from the group consisting of round and rectangular, and further wherein the bonding via 40 has a second shape, from a top-down view, selected from the group consisting of round and rectangular. Chiu also teaches that the bonding contact pad 36 and the bonding via 40 is part of an aligned interconnecting structure that electrically connects various devices and substrates (see, e.g., Chiu: col.3/II.17-25, and col.5/II.1-9).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the rectangular bonding via and the rectangular bonding contact pad of Chiu in method of Yu in view of Chen, to manufacture a part of an aligned interconnecting structure that electrically connects various devices and substrates.
Yu in view of in view of Chiu also shows (see, e.g., Chiu: figs. 2A-2B) that the bonding via 40 has a cross-sectional shape selected from the group consisting of tapered and non-tapered.
Claims 21-22, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2021/0407942) in view of Chen (US 2015/0171050) in further view of West (US 2021/0305178).
Regarding claim 21, Yu shows (see, e.g., Yu: figs. 1A-1B, and 2-6) most aspects of the instant invention including a method of forming a semiconductor package, comprising:
Forming a plurality of transistor elements 54 on a substrate 52
Electrically connecting respective ones of the transistor elements 54 by forming over the substrate 53 an interconnect structure 60 by performing the steps of:
Depositing over the plurality of transistors 54 a stack of dielectric layers 63A/63B
Embedding conductive lines 65A/67A/65B/67B within respective ones of the stack of dielectric layers 63A/63B, wherein the conductive lines 65A/67A/65B/67B are configured to conduct current in a first direction parallel to a major surface of the substrate 52
Electrically inter-connecting respective conductive lines 65A/67A/65B/67B with conductive vias, the conductive vias 65A/67A/65B/67B being configured conduct current in a second direction perpendicular to the major surface of the substrate 52
Depositing a bonding dielectric layer 64/68 at the top of the interconnect structure 50
At least partially embedding within the bonding dielectric layer 64/68 a contact pad 66, the contact pad 66 being electrically connected to at least one of the conductive vias 62/65A, the contact pad 66 having a first dimension, parallel to the major surface of the substrate 52, and having a second dimension, perpendicular to the major surface of the substrate 52, the contact pad further having topmost surface having a first surface area
Forming over a second substrate 72, a second interconnect structure 70, the second interconnect structure 70 including a second bonding dielectric layer 94/98 having at least partially embedded therein a bonding conductive via 96, the bonding conductive via 96 being configured to conduct current flow in a third direction perpendicular to a major surface of the second substrate 72, the bonding conductive via 96 having a third dimension parallel to the major surface of the second substrate 72 and a fourth dimension, perpendicular to the major surface of the second substrate 72
Bonding the bonding dielectric layer 64/68 to the second bonding dielectric layer 94/98 and bonding the contact pad 66 to the topmost surface of the bonding conductive via 96
Yu, however, fails (see, e.g., Yu: figs. 1A-1B, and 2-6) to specify that the second dimension is at least twice the first dimension and the fourth dimension is at least twice the third dimension. Chen, in a similar device to Yu, shows (see, e.g., Chen: figs. 7) that the second metallic bonding structure 118 is provided with a bonding via 118 that has a first dimension H2 in a direction perpendicular to the major plane of the first semiconductor wafer and a second dimension W1 in a second direction parallel to the plane of the first semiconductor wafer, and the bonding contact pad 118 that has a third dimension H3 in the direction perpendicular to the major plane of the first semiconductor wafer and a fourth direction W2 parallel to the plane of the first semiconductor plane (see, e.g., Chen: par. [0034] – [0035]). Horizontal dimensions W1 and W2 may be a length/width, diameter, or the like depending on a top-down shape of conductive pad 118 (see, e.g., Chen: par. [0034]). Chen further shoes that the horizontal dimensions W1 and W2 are between about 0.1 µm and about 10 µm, and vertical dimensions H2 and H3 may be between about 0.1 µm and about 1 µm. (see, e.g., Chen: par. [0034] – [0035]). Thus, there is a combination of dimensions where the second dimension is less the first dimension, and the fourth dimension is greater than the third dimension.
Chen also shows that in simulations where conductive pad 118 comprises copper and the dimensions of W1, W2, H2, and H3 are 1 µm, 0.5 µm, 0.5 µm, and 1 µm, respectively, the thermal stress at the surface of conductive pad 118 is
4.938
x
10
-
5
Newtons. However, in simulations where the dimensions of W1, W2, H2, and H3 were 1 µm, 0 µm, 0.5 µm, and 0 µm, respectively, (e.g., where the metallic material was uniformly distributed), the surface stress of the conductive pad was higher at
5.977
x
10
-
5
Newtons (see, e.g., Chen: par. [0036)]). Chen also shows that the reduction of surface stress reduces the probability of forming voids, particularly in corner regions 118B, during subsequent bonding processes. Chen further shows that the shape and dimensions of conductive pad 118 reduces the overall surface stress of conductive pad 118 (see, e.g., Chen: par. [0036)]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the first and second dimensions of the bonding via and the third and fourth dimensions of the bonding contact pad of Chen in method of Yu, to reduce the overall surface stress of conductive pad.
However, the differences in the dimensions of the bonding via and the bonding contact pad will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see next paragraph 22) of the mentioned dimensions, and Chen has identified such dimensions as a result-effective variables subject to optimization, it would have been obvious to one of ordinary skill in the art to use these dimension values in the method of Yu.
Yu in view of Chen, however, fails (see, e.g., Yu: figs. 1A-1B, and 2-6) to specify that the bonding via 96 has a width of the bonding via 96, measured in a direction perpendicular to the major plane of the first semiconductor wafer 50 that is free from steps (substantially parallel sidewalls) from the topmost surface to the bottommost surface.
West, in a similar device to Yu in view of Chen, shows (see, e.g., West: fig. 1) that that bonding via 154/164/174 has a width of the bonding via 154/164/174, measured in a direction perpendicular to the major plane of the first semiconductor wafer 101 that is free from steps (substantially parallel sidewalls) from the topmost surface to the bottommost surface. West, further shows that the bonding vias that the bonding vias 154/164/174 that has a width of the bonding via 154/164/174, measured in a direction perpendicular to the major plane of the first semiconductor wafer 101 that is free from steps (substantially parallel sidewalls) from the topmost surface to the bottommost surface serve as conductive vias in the multilevel metallization structures and provide a Faraday cages around isolation elements (see, e.g., West: par. [0025], and [0018]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include bonding via of West that the bonding via that has a width of the bonding via, measured in a direction perpendicular to the major plane of the first semiconductor wafer that is free from steps (substantially parallel sidewalls) from the topmost surface to the bottommost surface, in method of Yu in view of Chen, to serve as conductive vias in the multilevel metallization structures and provide a Faraday cages around isolation elements.
Also, Yu in view of Chen fails (see, e.g., Yu: figs. 1A-1B, and 2-6) to shows that the bonding via 96 has a width of the bonding via 96, measured in a direction perpendicular to the major plane of the first semiconductor wafer 50 that is free from steps (substantially parallel sidewalls) from the topmost surface to the bottommost surface. However, it is noted that the specification fails to provide teachings about the criticality of having the bonding via free from steps (substantially parallel sidewalls) from the topmost surface to the bottommost surface, as claimed in the instant application.
Therefore, absent any criticality, this limitation is only considered to be an obvious modification of the shape of the bonding via structure 96 disclosed by Yu in view of Chen as the courts have held that a change in shape or configuration, without any criticality, is within the level of skill in the art, and the particular bonding via free from steps (substantially parallel sidewalls) from the topmost surface to the bottommost surface claimed by applicant is nothing more than one of numerous contour shapes that a person having ordinary skill in the art will find obvious to provide using routine experimentation as a matter of choice or based on its suitability for the intended use of the invention. See In re Daily, 149 USPQ 47 (CCPA 1976).
Furthermore, the claimed bonding via free from steps from the topmost surface to the bottommost surface is known in the art: West, in the same field of endeavor, teaches (see, e.g., West: fig. 1) that the bonding via free from steps from (substantially parallel sidewalls) the topmost surface to the bottommost surface.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the bonding via free from steps (substantially parallel sidewalls) from the topmost surface to the bottommost surface of Yu in view of Chen, because the bonding via free from steps (substantially parallel sidewalls) from the topmost surface to the bottommost surface is known in the semiconductor art to have free-from-steps profile for its use as bonding vias similarly used for in instant invention and West, as suggested by West, and implementing a known structure shape for its conventional use/purpose would have been a common sense choice by the skilled artisan. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Yu in view of Chen in view of West shows (see, e.g., West: fig. 1) that the bonding conductive via 154/164/174 having a top surface having a second area is less than the first surface area, and a bottom surface in contact with an underlying conductive line.
Regarding claim 22, Yu in view of Chen in view of West shows (see, e.g., Yu: figs. 1A-1B, and 2-6) that the bonding dielectric layer 64/68 is deposited on a topmost dielectric layer of the stack of dielectric layers 63A/63B, and further wherein the second bonding dielectric layer 94/98 is deposited on a topmost second dielectric layer of the second interconnect structure 70.
Regarding claim 11, Yu in view of Chen shows (see, e.g., Yu: figs. 1A-1B, and 2-6) the method step of forming a conductive line over the second semiconductor wafer 72 (see, e.g., Yu: par. [0034]) and further wherein the bonding via 96 has a bottom surface contacting the conductive line.
Yu in view of Chen, however, fails (see, e.g., Yu: figs. 1A-1B, and 2-6) to specify that the bonding via 96 has a width of the bonding via 96, measured in a direction perpendicular to the major plane of the first semiconductor wafer 50 that is free from steps (continuous via) from the topmost surface to the bottommost surface.
West, in a similar device to Yu in view of Chen, shows (see, e.g., West: fig. 1) that that bonding via 154/164/174 has a width of the bonding via 154/164/174, measured in a direction perpendicular to the major plane of the first semiconductor wafer 101 that is free from steps (continuous via) from the topmost surface to the bottommost surface. West, further shows that the bonding vias that the bonding vias 154/164/174 that has a width of the bonding via 154/164/174, measured in a direction perpendicular to the major plane of the first semiconductor wafer 101 that is free from steps (continuous via) from the topmost surface to the bottommost surface serve as conductive vias in the multilevel metallization structures and provide a Faraday cages around isolation elements (see, e.g., West: par. [0025], and [0018]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include bonding via of West that the bonding via that has a width of the bonding via, measured in a direction perpendicular to the major plane of the first semiconductor wafer that is free from steps (continuous via) from the topmost surface to the bottommost surface, in method of Yu in view of Chen, to serve as conductive vias in the multilevel metallization structures and provide a Faraday cages around isolation elements.
Also, Yu in view of Chen fails (see, e.g., Yu: figs. 1A-1B, and 2-6) to shows that the bonding via 96 has a width of the bonding via 96, measured in a direction perpendicular to the major plane of the first semiconductor wafer 50 that is free from steps (continuous via) from the topmost surface to the bottommost surface. However, it is noted that the specification fails to provide teachings about the criticality of having the bonding via free from steps (continuous via) from the topmost surface to the bottommost surface, as claimed in the instant application.
Therefore, absent any criticality, this limitation is only considered to be an obvious modification of the shape of the bonding via structure 96 disclosed by Yu in view of Chen as the courts have held that a change in shape or configuration, without any criticality, is within the level of skill in the art, and the particular bonding via free from steps (continuous via) from the topmost surface to the bottommost surface claimed by applicant is nothing more than one of numerous contour shapes that a person having ordinary skill in the art will find obvious to provide using routine experimentation as a matter of choice or based on its suitability for the intended use of the invention. See In re Daily, 149 USPQ 47 (CCPA 1976).
Furthermore, the claimed bonding via free from steps from the topmost surface to the bottommost surface is known in the art: West, in the same field of endeavor, teaches (see, e.g., West: fig. 1) that the bonding via free from steps from (continuous via) the topmost surface to the bottommost surface.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the bonding via free from steps (continuous via) from the topmost surface to the bottommost surface of Yu in view of Chen, because the bonding via free from steps (continuous via) from the topmost surface to the bottommost surface is known in the semiconductor art to have free-from-steps profile for its use as bonding vias similarly used for in instant invention and West, as suggested by West, and implementing a known structure shape for its conventional use/purpose would have been a common sense choice by the skilled artisan. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Response to Arguments
Applicants’ arguments have been considered but are moot in view of the previous grounds of rejection. Examiner has read and considered Applicants’ arguments, and finds them to be unpersuasive. Applicant’s arguments involve discussing why the previously cited prior art documents fail to disclose the amended limitation. Examiner believes that Yu in view West or Yu in view of Chen in view of West also discloses the amended limitations. The applicability of Yu reference, West reference, and Chen reference to the amended limitation is indicated in the claim rejections above.
The applicants argue:
Yu fails to anticipates or otherwise render obvious that "… the bonding via has a width of the bonding via, measured in a direction perpendicular to the major plane of the first semiconductor wafer that is free from steps from the topmost surface to the bottommost surface …”, as recited in exemplary claim 1. Similar limitations are also specified in claims 10, and 21.
The examiner responds:
In view of the new grounds of rejection, Yu in view of West, shows (see, e.g., West: fig. 1) that that bonding via 154/164/174 has a width of the bonding via 154/164/174, measured in a direction perpendicular to the major plane of the first semiconductor wafer 101 that is free from steps from the topmost surface to the bottommost surface. West, further shows that the bonding vias that the bonding vias 154/164/174 that has a width of the bonding via 154/164/174, measured in a direction perpendicular to the major plane of the first semiconductor wafer 101 that is free from steps from the topmost surface to the bottommost surface serve as conductive vias in the multilevel metallization structures and provide a Faraday cages around isolation elements (see, e.g., West: par. [0025], and [0018]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include bonding via of West that the bonding via that has a width of the bonding via, measured in a direction perpendicular to the major plane of the first semiconductor wafer that is free from steps from the topmost surface to the bottommost surface, in method of Yu, to serve as conductive vias in the multilevel metallization structures and provide a Faraday cages around isolation elements.
Also, Yu fails (see, e.g., Yu: figs. 1A-1B, and 2-6) to shows that the bonding via 96 has a width of the bonding via 96, measured in a direction perpendicular to the major plane of the first semiconductor wafer 50 that is free from steps from the topmost surface to the bottommost surface. However, it is noted that the specification fails to provide teachings about the criticality of having the bonding via free from steps from the topmost surface to the bottommost surface, as claimed in the instant application.
Therefore, absent any criticality, this limitation is only considered to be an obvious modification of the shape of the bonding via structure 96 disclosed by Yu as the courts have held that a change in shape or configuration, without any criticality, is within the level of skill in the art, and the particular bonding via free from steps from the topmost surface to the bottommost surface claimed by applicant is nothing more than one of numerous contour shapes that a person having ordinary skill in the art will find obvious to provide using routine experimentation as a matter of choice or based on its suitability for the intended use of the invention. See In re Daily, 149 USPQ 47 (CCPA 1976).
Furthermore, the claimed bonding via free from steps from the topmost surface to the bottommost surface is known in the art: West, in the same field of endeavor, teaches (see, e.g., West: fig. 1) that the bonding via free from steps from the topmost surface to the bottommost surface.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the bonding via free from steps from the topmost surface to the bottommost surface of Yu, because the bonding via free from steps from the topmost surface to the bottommost surface is known in the semiconductor art to have free-from-steps profile for its use as bonding vias similarly used for in instant invention and West, as suggested by West, and implementing a known structure shape for its conventional use/purpose would have been a common sense choice by the skilled artisan. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Conclusion
This action is made final. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire three months from the mailing date of this action. In the event a first reply is filed within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIBERIU DAN ONUTA whose telephone number is (571) 270-0074 and between the hours of 9:00 AM to 5:00 PM (Eastern Standard Time) Monday through Friday or by e-mail via Tiberiu.Onuta@uspto.gov. If attempts to reach the examiner by telephone or email are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (in USA or Canada) or 571-272-1000.
/TIBERIU DAN ONUTA/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814