DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see arguments, filed 02/02/2026, with respect to rejection under 35 USC 103 of claims 8-15 and 21-25 have been fully considered and are persuasive. The 35 USC 103 claim rejections have been withdrawn.
Applicant’s arguments, see arguments, filed 02/02/2026 with respect to rejection under 35 USC 103 of claims 1-7 have been fully considered and are not persuasive, the amendments made do not overcome the prior art of record.
Applicant argues that Chen in view of Bergendahl, Lin, and Lin 2013 does not teach the amended limitations. The examiner respectfully disagrees Chen in view of Bergendahl, Lin, and Lin 2013 teaches the amended limitations as shown below. More specifically the combination of Bergendahl teaches depositing the liner (40a and/or 40b fig. 13) before the dielectric fill (55 fig. 14), the combination of Lin 2013 teaches the treatment first treatment process (120 fig. 3) after depositing a dielectric material (110 fig. 3) and patterning the dielectric material after the first treatment process (150 fig. 3), and base reference Chen sufficiently discloses after patterning the nitrogen rich layer, etching the second gate region to remove the second gate region of the first transistor [figs 10A and fig. 11, 52 is patterned before the etch further disclosed Column 10 lines 58-61 “The one or more mask layers are patterned to have the mask opening 54 to thereby form the mask 52”].
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 4 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over US 11114549 B2 Chen et al hereafter “Chen” in further view of US 20180069000 A1 Bergendahl et al hereafter “Bergendahl”, US 20210126110 A1 Lin et al hereafter “Lin”, and US 20130072028 A1 Lin et al hereafter “Lin 2013”
Claim 1 Chen A method comprising:
forming a recess (the recess filled by gate-cut fill structure 50 fig. 9A) between a first gate region [see annotation below] and a second gate region [see annotation below] of a first transistor [the structure of a first transistor is sufficiently by the device illustrated in fig. 9A], the recess electrically separating the first gate region from the second gate region [sufficiently illustrated fig. 9A] ;
depositing a dielectric liner (comprising 52 fig. 10A ) over an upper surface of the first gate region and the second gate region [illustrated fig. 10A in conjunction with Column 10 lines 58-61 “The one or more mask layers are patterned to have the mask opening 54 to thereby form the mask 52. The one or more mask layers may be patterned using photolithography and etch processes, as previously described” which sufficiently discloses that a portion of 52 is removed (patterned and/or etched) to form 54 within fig. 10A];
depositing a dielectric fill material (50 fig. 10A) in the recess;
the dielectric fill material forms part of a nitrogen rich layer [met under broadest reasonable interpretation u and/or MPEP 2112, comprising 50 and 42 fig. 10A and embodiment is Sufficiently disclosed wherein 50 and 42 comprise nitrogen rich silicon in “silicon nitride” and/or “silicon carbon nitride” column 10 lines 48-67 and column 10 lines 10-15, note: the silicon nitride constitutes a nitrogen rich layer];
patterning the nitrogen rich layer to use as an etch mask [disclosed Column 10 lines 58-61 “The one or more mask layers are patterned to have the mask opening 54 to thereby form the mask 52”];
after patterning the nitrogen rich layer, etching the second gate region to remove the second gate region of the first transistor [sufficiently illustrate as 54 and/or 60 fig. 11A d].
Depositing the dielectric liner comprises CVD [embodiment sufficiently disclosed column 10 lines 50-60]; and
Depositing the dielectric fill material comprises CVD [embodiment sufficiently disclosed column 10 lines 6-18];
Chen does not teach depositing the dielectric liner in the recess; after depositing the dielectric liner, depositing the dielectric fill material in the recess and over the upper surface of the first gate region and the second gate region; after depositing the dielectric fill material, treating the dielectric fill material by a first treatment process, the first treatment process altering a portion of the dielectric fill material to form the nitrogen rich layer in the dielectric fill material and after treating the dielectric fill material, patterning the nitrogen rich layer.
Bergendahl teaches depositing a dielectric liner (comprising 40a and 40b fig. 12) in a recess (“gate cut trench” 5 fig. 12) and over the upper surface of a gate region (comprising 25’, 28,’ and/or 28”) [sufficiently illustrated fig. 12];
After depositing the dielectric liner, depositing a dielectric fill material (55 fig. 14) in the recess and over the upper surface of the gate region [sufficiently illustrated fig. 12-14].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the process of Chen with the process of Bergendahl such that the process comprises “depositing a dielectric liner in the recess and over an upper surface of the first gate region and the second gate region” and “ After depositing the dielectric liner, depositing a dielectric fill material in the recess and over the upper surface of the first gate region and the second gate region” for the benefit obstructing shorting of the gate structures with the dielectric layers [sufficiently disclosed paragraph 0035 Bergendahl “GS. 4A-4C depict a misaligned power rail 10 being formed in a gate cut trench 5, in which shorting to the substrate and the gate structures 25a, 25b is obstructed by an etch stop layer 40a, 40b that is positioned in the gate cut trench 5”] and/or to utilize a conformal mask layer and dictate the depth of other components elements on higher layers [sufficiently disclosed Paragraph 0069 Bergendahl] and/or changes in relative shape are prima facie type obviousness [See MPEP 2144.04 IV. B.].
Lin teaches CVD and thermal nitriding of silicon as alternative processes for forming a mask layer [Sufficiently disclosed Paragraph 0017 “hard mask layer 30 is formed by thermal nitriding of silicon, or Plasma Enhanced Chemical Vapor Deposition (PECVD)”]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the CVD process of forming the first mask layer as taught by Chen in view Bergendahl with the deposition of silicon and treating it with a thermal nitriding process as Lin teaches such that there is “treating the dielectric fill material by a first treatment process” as using CVD and using thermal nitriding of silicon are art recognized equivalent process for achieving a mask layer and/or a nitride rich silicon layer [see MPEP 2144.06].
Lin 2013 teaches after depositing a dielectric material (110 fig. 3), performing a thermal nitriding process treatment on the dielectric material with a twostep nitridation process (120 fig. 3) that result in a nitrogen concentration profile (29 fig. 2) wherein there is a nitrogen rich region [see annotation below] interposed between an upper portion [see annotation below] and a lower portion [see annotation below] and after treating the dielectric fill material, patterning the nitrogen rich layer (150 fig. 3, wherein the SiON layer comprises the nitrogen rich layer).
It would have been obvious to one of ordinary skill in the art to substitute the thermal nitriding process of Chen in view of Bergendahl and Lin with the two step thermal nitriding process of Lin 2013 such that the first treatment process is “after depositing the dielectric material” and includes “altering a portion of the dielectric fill material to form a nitrogen rich layer in the dielectric fill material” and “after treating the dielectric fill material, patterning the nitrogen rich layer” to improve the k-value of the mask layer [Lin 2013 paragraph 17] and/or to improve the electrical performance of the device and/or a dielectric layer [sufficiently disclosed Lin 2013 paragraph 0016].
PNG
media_image1.png
465
896
media_image1.png
Greyscale
Chen Annotated fig. 9A: highlighting a first gate stack, a second gate stack, and a recess
PNG
media_image2.png
401
472
media_image2.png
Greyscale
Annotated fig. 2 Lin 2013: highlighting a nitrogen rich region
Claim 3 Chen in view of Bergendahl, Lin and Lin 2013 teach the method of claim 1, wherein the first treatment process includes an ammonia soak [in view of Lin 2013 and sufficiently disclosed Lin 2013 paragraph 0024 in the embodiment of ammonia thermal nitridation “NH3 thermal nitridation” wherein the dielectric fill is at exposed to and/or soaked in ammonia under broadest reasonable interpretation].
Claim 4 Chen in view of Bergendahl, Lin and Lin 2013 teach as shown above the method of claim 1, wherein etching the second gate region forms a second recess (comprising 54 and/or 60 fig. 11A Chen) adjacent the first gate region, further comprising:
forming an isolation region (comprising 66 fig. 17A) in the second recess [sufficiently illustrated fig. 15A to fig. 17A].
Claim 7 Chen in view of Bergendahl, Lin and Lin 2013 teach as shown above the method of claim 1, further comprising:
after the first treatment process, annealing the dielectric fill material (met in view of the two-step nitration process of Lin 2013, fig. 1 “post-annealing process”), the nitrogen rich layer being buried beneath an upper surface of the dielectric fill material (met in view of the two-step nitration process of Lin 2013, illustrated fig. 2, see annotation in claim 1).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Bergendahl, Lin and Lin 2013 as shown in claim 1 and in further view US 20120329239 A1 Kammler et al hereafter “Kammler”
Claim 2 Chen in view of Bergendahl, Lin and Lin 2013 teach as shown above the method of claim 1, wherein the nitrogen rich layer is formed below an upper surface of the dielectric fill material [met in view of Lin 2013, sufficiently illustrated Lin 2013 fig. 2], further comprising:
Chen in view of Bergendahl, Lin and Lin 2013 do not teach planarizing the upper surface of the dielectric fill material to expose the nitrogen rich layer.
Kammler teaches a chemical mechanical planarization process that planarizes an upper portion of a mask to expose a nitrogen rich region. [sufficiently disclosed Paragraph 0017 in “The oxide material can be planarized, for example by the process of chemical mechanical planarization (CMP). The CMP process continues until the patterned layer of silicon nitride 206 is reached, with the silicon nitride acting as a stop for the CMP.” The oxide material is “the upper portion” and the silicon nitride is “the nitrogen rich region”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the process of Chen in view of Lin and Lin 2013 by adding the cmp process as taught by Kammler such that “planarizing the upper surface of the dielectric fill material to expose the nitrogen rich layer” occurs for the benefit of removing any undesired materials and/or by products from the mask layer such as oxide material [sufficiently disclosed paragraph 0006 Kammler “A CMP operation is performed to remove oxide material overlying the layer of silicon nitride”]
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Bergendahl, Lin and Lin 2013 as shown in claim 1 and in further view of US 20190378903 A1 Jeon et al here after “Jeon”
Claim 5 Chen in view of Bergendahl, Lin and Lin 2013 teach as shown above the method of claim 1, the dielectric fill material is between the first gate region and the second gate region [sufficiently illustrated fig. 9A].
Chen in view of Bergendahl, Lin and Lin 2013 do not teach wherein depositing the dielectric fill material forms an air gap in the dielectric fill material between the first gate region and the second gate region.
Jeon teaches forming a gate cut comprises depositing a dielectric fill material (172 fig. 28) forms an air gap (180 fig. 28) in the dielectric fill material between a first gate region (comprising 160A, 150A, 130A fig. 28) and a second gate region (comprising 160B, 150B, 130B fig. 28).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the processes Chen in view of Bergendahl, Lin and Lin 2013 in view of Jeon such that “depositing the dielectric fill material forms an air gap in the dielectric fill material between the first gate region and the second gate region” to reduce capacitance and/or insulate the first gate region and the second region more effectively [Jeon Paragraph 0036 and 0037].
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Bergendahl, Lin and Lin 2013 as shown in claim 1 and in further view of US 9954076 B2 Yu et al here after “Yu”
Claim 6 Chen in view of Bergendahl, Lin and Lin 2013 The method of claim 1, wherein forming the recess comprises etching through a metal gate electrode (48 fig. 9A) [sufficiently disclosed Column 10 lines 1-8 “The trenches can extend to a depth to and/or into the corresponding isolation regions 26, e.g., through the gate electrodes 48, one or more optional conformal layers 46, and gate dielectric layer 44. The etch process may include a RIE, NBE, ICP etch, the like, or a combination thereof. The etch process may be anisotropic. An insulating material for the gate cut-fill structures 50 is deposited in the trenches that cut the replacement gate structures”]; and a first shallow trench isolation region (26 fig. 9A) disposed below the metal gate electrode [sufficiently illustrated fig. 9A].
Chen in view of Bergendahl, Lin and Lin 2013 do not teach forming the recess comprises etching into the first shallow trench isolation region.
Yu teaches forming a gate-cut region by forming a recess (130 fig. 6A) extends into a shallow trench isolation region (50 fig. 6A) below a metal gate stack (comprising at least 110 and 105 fig. 6A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the to change the size of the recess Chen in view of Bergendahl, Lin and Lin 2013 teach in view of the recess Yu teaches such that “the recess extends into a shallow trench isolation region below the metal gate stack” as part of the etching process as changes in size and/or shape is prima facie type obviousness [See MPEP 2144.04 IV B.] and/or as a part of routine optimization of the isolation between adjacent conductive structures is prima facie type obviousness [See MPEP 2144.05 II. A].
Allowable Subject Matter
Claims 8-15 and 21-25 allowed.
The following is an examiner’s statement of reasons for allowance:
Claim 8 and dependent claims recites the limitation “wherein an unaltered layer of the first mask remains under the nitrogen rich region” in view of the rest of the claim.
Claim 21 and dependent claims additional recite the limitation “wherein the modified layer extends into the recess” in view of the rest of the claim
Prior art of record does not teach the limitations as claimed nor has the examiner found an obvious reason to modify the prior art of record such that the limitations are met.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to William C Trice whose telephone number is (703)756-1875. The examiner can normally be reached M-F 8:30am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/WCT/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
Prosecution Insights