DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Remarks, filed 01 December 2025, with respect to claim 13 have been fully considered and are persuasive. The 35 U.S.C. § 103 rejection of claim 13 has been withdrawn.
Applicant's arguments filed 01 December 2025 with respect to the 35 U.S.C. § 102 rejection claims 23 and 29 have been fully considered but they are not persuasive.
Regarding claim 23, the applicant argued that Yu does not teach the limitation of claim 30, which is added to claim 23. Specifically, the applicant points to Yu ¶ [0003] stating that the drawings are not to scale and hence the relative widths of the power rails and an interconnect of a front-side interconnect are not disclosed. The examiner respectfully disagree and finds that Yu ¶ [0048] further supports the prior rejection of claim 30. Please refer to the 35 U.S.C. § 102 rejection below for more details. Furthermore, in Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
Regarding claim 29, the examiner finds that Yu teaches the amended claim limitations. Specifically, the aspects related to Yu’s package-on-package technology (see ¶ [0002], and Figs. 46-65) was used in the 35 U.S.C. § 102 rejection below.
In summary, the application is not in a condition for an allowance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 23, 29-31, and 34 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu (US 2021/0407942 A1).
Regarding claim 23, Yu teaches a method (Figs. 1-19B) comprising:
forming a power distribution interposer (75; plain meaning of interposer is a structure placed in between two other objects or in an intervening position; as shown in Fig. 19B, 75 is in between 215 and 122; hence 75 is an interposer; see also ¶ 0060: 75 is a power rail chip) comprising:
a first bonding layer (98, see ¶ 0041 and Fig. 6);
a first die connector (96) in the first bonding layer; and
a back-side interconnect structure (100A&100B&72, see ¶ 0014, ¶ 0076 and abstract: 100B is on the back side of wafer 70) comprising a power rail (112, see ¶ 0046-0048 and Fig. 9) connected to the first die connector (Fig. 19B shows power path 212 showing 112 of 100B connected to 96); and
forming an integrated circuit die (215) comprising:
a second bonding layer (68, see ¶ 0041 and Fig. 6);
a second die connector (66) in the second bonding layer; and
a device layer (53) on the second bonding layer (Fig. 19B shows 53 on 68), the device layer comprising a contact (58, see Fig. 6 and ¶ 0019; note top chip 215 in Fig. 19B is the same as wafer 50 in Fig. 6) and a transistor (54, see ¶ 0018), the transistor comprising a first source/drain region (¶ 0019) and a second source/drain region (¶ 0019: each transistor has a source and a drain), the contact connecting a back-side (bottom side 54 in Fig. 19B; as shown in Fig. 19B, this is the bottom side of the active surface 53) of the first source/drain region to the second die connector (as shown in Fig. 6 & 19B; contact 58 connects transistor 54 to 66 ; ¶ 0019: 58 connects the source/drain regions of 54 ); and
a front-side interconnect structure (Fig. 19B: 282&290; Fig. 19B shows 282&290 located at the top side of active layer 53, hence it is a front-side interconnect), the front-side interconnect structure comprising an interconnect (282) that is connected to a front-side (top side) of the second source/drain region; a width of the power rail being greater than a width of the interconnect (¶ 0048 teaches power rail 112 being greater than any other interconnect structures: “the widths, lengths and/or thicknesses of the conductive lines 112 of the PDN layer 100B may also be larger than widths, lengths and/or thicknesses of respective conductive vias and lines of other interconnect structures such as… the semi-global interconnect 190…”; in the same paragraph, Yu teaches: “This may enable the conductive features of the PDN layer 100B to transmit power more efficiently without damage to the conductive features of the PDN layer 100B”); and
bonding (¶ 0041) the integrated circuit die to the power distribution interposer, the second bonding layer directly bonded (¶ 0041: bumpless bonds with no mention of adhesives; hence, directly bonded) to the first bonding layer by dielectric-to-dielectric bonds (¶ 0041: dielectric bonds between 68 and 98), the second die connector directly bonded to the first die connector by metal-to-metal bonds (¶ 0041: Cu-Cu bonds between 66 and 96).
Regarding claim 29, Yu teaches a method (Figs. 25-35) comprising:
forming a die structure (400) by:
forming a power distribution interposer (470&100B&100A; plain meaning of interposer is a structure placed in between two other objects or in an intervening position; as shown in Fig. 35, 470&100B&100A is in between 550 and 455 and as shown in Fig. 34, 470&100B&100A spans horizontally two support two 550s; hence it is an interposer; see also ¶ 0072: 470 is a power rail die) comprising a back-side interconnect structure (100A&100B; see ¶ 0081: 100B is on the backside of 470), the back-side interconnect structure comprising power rails (112, see ¶ 0046-0048, ¶ 0072 and Fig. 9) and data rails (¶ 0046: data signals may be routed through 100B)
attaching a plurality of integrated circuit dies (two 550s, see Figs. 31-32 and ¶ 0077-0078) to the power distribution interposer (Fig. 32 and ¶ 0078 shows 550 attached to 470&100B&100A), each of the integrated circuit dies comprising a device layer (153) and a front-side interconnect structure (190&172; Fig. 35 show these are located on top of device layer 153, hence are front-side structures), the device layer disposed between the front-side interconnect structure and the power distribution interposer (Fig. 35 shows 153 in between 190&172 and 470&100B&100A), the power rails being connected to transistors (54, see ¶ 0018, see also Fig. 6) in the device layer (using contact 58 in layer 153; see also Fig. 6) of each of the integrated circuit dies (Fig. 49 and ¶ 0060, ¶ 0094 shows device stack 200, with 200 being the singulated structure in Fig. 35, to be later integrated into a package component as shown in Figs. 46-65; hence the power rail is used to connect to each of the integrated circuit dies), and the data rails interconnecting the transistors of one of the integrated circuit dies (¶ 0046: 100B may also be used for data signals) with the transistors of another of the integrated circuit dies (the package component in Fig. 60 shows RDL 1022 used to connect two or more device stacks 200; since ; ¶ 0002 teaches the package component to be a package-on-package technology for high level of integration; it is known in the art that integration requires exchange of data and/or power signals to/from corresponding integrated circuit dies);
forming a gap-filling dielectric (404, see Fig. 34) between the integrated circuit dies; and
singulating the gap-filling dielectric and the power distribution interposer (Fig. 35 and ¶ 0081); and
connecting the power distribution interposer of the die structure to a package substrate (52; using BRI 52 is a package substrate as it is the base on which all elements of package 400 is mounted on; see Fig. 35 and ¶ 0017).
Regarding claim 30, the method of claim 29, wherein the front-side interconnect structure of each of the integrated circuit dies comprises interconnects (Fig. 35: 193), and a width of the power rails is greater than a width of the interconnects (Fig. 35 shows 112 of 100B is wider than 193; see also Fig. 9 where 112 is marked; ¶ 0048 teaches power rail 112 being greater than any other interconnect structures: “the widths, lengths and/or thicknesses of the conductive lines 112 of the PDN layer 100B may also be larger than widths, lengths and/or thicknesses of respective conductive vias and lines of other interconnect structures such as… the semi-global interconnect 190…”; in the same paragraph, Yu teaches: “This may enable the conductive features of the PDN layer 100B to transmit power more efficiently without damage to the conductive features of the PDN layer 100B”).
Regarding claim 31, the method of claim 29, wherein the front-side interconnect structure of each of the integrated circuit dies comprises interconnects (Fig. 35: 193), and a length (length of 112 of 100B, see also Fig. 9) of the data rails is greater than a length (length of 193) of the interconnects (Fig. 35 shows 112 is longer than 193; ¶ 0048 teaches power rail 112 being greater than any other interconnect structures: “the widths, lengths and/or thicknesses of the conductive lines 112 of the PDN layer 100B may also be larger than widths, lengths and/or thicknesses of respective conductive vias and lines of other interconnect structures such as… the semi-global interconnect 190…”; in the same paragraph, Yu teaches: “This may enable the conductive features of the PDN layer 100B to transmit power more efficiently without damage to the conductive features of the PDN layer 100B”).
Regarding claim 34, the method of claim 23, wherein the back-side interconnect structure further comprises a stack of dielectric layers (Fig. 19B shows 100A&100B comprising a stack of dielectric layers; see ¶ 0045, ¶ 0046 ), and the power rail is among the dielectric layers (Fig. 9 shows 112 within 100B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 26 and 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 2021/0407942 A1) in view of another embodiment of Yu.
Regarding claim 26, Yu teaches the method of claim 23, However, the embodiment of Yu used to reject claim 24 does not teach further comprising: bonding a support substrate to the front-side interconnect structure of the integrated circuit die, the support substrate being wider than the front-side interconnect structure.
However, Yu, in another embodiment, teaches a method comprising:
bonding a support substrate (Fig. 65: 6034) to the front-side interconnect structure of the integrated circuit die (¶ 0094 states the package 210 of Fig 19B can be substituted in place of 200 in Fig. 65; hence front-side interconnect structure 282&290 of 215 in Fig. 19B is bonded to 6034), the support substrate being wider than the front-side interconnect structure (Fig. 65 shows 6034 is wider than 282&290).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of another embodiment of Yu into the method Yu to bond a support substrate to a front-side interconnect structure of an integrated circuit die, with the support substrate wider than the front-side interconnect structure, in a method at least comprising of forming a power distribution interposer and forming the integrated circuit die comprising of the front-side interconnect structure and a source/drain region connected to the front-side interconnect structure. The ordinary artisan would have been motivated to modify Yu in the manner set forth above for at least the purpose of designing integrated fan-out packages (¶ 0095) or a chip-on-wafer-on-substrate that integrates stacks of devices into a single package (¶ 0035).
Regarding claim 32, Yu teaches the method of claim 29, However, the embodiment of Yu used to reject claim 29 does not teach further comprising:
bonding a support substrate to the die structure, the support substrate being wider than the integrated circuit dies.
However, Yu, in another embodiment, teaches a method comprising:
bonding a support substrate (Fig. 65: 6034) to the die structure (¶ 0094 states the package 210 of Fig 19B can be substituted in place of 200 in Fig. 65), the support substrate being wider than the integrated circuit dies (Fig. 65 shows 6034 is wider than 200, with the integrated circuit dies within 200).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of another embodiment of Yu into the method Yu to bond a support substrate to a die structure, with the support substrate wider than the integrated circuit dies, in a method at least comprising of forming the die structure by: forming a power distribution interposer and attaching a plurality of integrated circuit dies, with each integrated circuit die comprising of the front-side interconnect structure and a device layer between the front-side interconnect structure and the power distribution interposer. The ordinary artisan would have been motivated to modify Yu in the manner set forth above for at least the purpose of designing integrated fan-out packages (¶ 0095) or a chip-on-wafer-on-substrate that integrates stacks of devices into a single package (¶ 0035).
Allowable Subject Matter
Claims 13-16, 18-20, and 33 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 13, the prior art discloses a method as generally recited in independent claim 13 (see 35 U.S.C § 103 rejection in previous Office Action), but no other prior art was found to anticipate or render obvious a method comprising:
forming a gap-filling dielectric around the integrated circuit die, a top surface of the gap-filling dielectric being co-planar with a top surface of the first interconnect structure.
Claims 27-28 and 36 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims 27-28, no prior art of record was found to anticipate or render obvious the method of claim 23, further comprising:
after bonding the integrated circuit die to the power distribution interposer, forming a gap-filling dielectric around the integrated circuit die, a top surface of the gap-filling dielectric being coplanar with a top surface of the integrated circuit die; and
singulating the gap-filling dielectric and the power distribution interposer.
Regarding claim 36, no other prior art was found to anticipate or render obvious the method of claim 23, further comprising:
forming a gap-filling dielectric around the integrated circuit die, a top surface of the gap-filling dielectric being co-planar with a top surface of the first interconnect structure.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS YAP whose telephone number is (703)756-1946. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571) 272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DOUGLAS YAP/Assistant Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899