Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/05/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 15-29 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 15 line 13-14 and claim 21 lines 13 recited “a plurality of the (first) conductive vias” is unclear. Do a plurality of the (first) conductive vias include conductive vias as previously claimed?
Claim 28 line 11 and claim 21 lines 13 recited “a plurality of the second conductive vias” is unclear. Do a plurality of the second conductive vias include conductive vias as previously claimed?
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 15, 17, 18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 2021/0098423).
As for claim 15, Chen et al. disclose in Fig. 1A-1L and the related text a method comprising:
bonding a first front-side of a first integrated circuit die 20 to a second front-side of a second integrated circuit die 10, the first integrated circuit die 20 comprising a semiconductor substrate 200 and a through-substrate via 209;
forming a gap-fill dielectric 300 on the first integrated circuit die and on the second integrated circuit die (Fig. 1B);
planarizing the gap-fill dielectric 300 until the gap-fill dielectric, the semiconductor substrate 200, and the through-substrate via 209 have top surfaces that are substantially coplanar (Fig. 1C, [0034]);
depositing a first dielectric layer 302 on the top surfaces of the gap-fill dielectric, the semiconductor substrate, and the through-substrate via (Fig. 1L); and
forming conductive vias 312 in the first dielectric layer, the conductive vias extending through the first dielectric layer to contact the top surface of the through-substrate via such that the top surface of the through-substrate via 209 is in physical contact with a plurality of the conductive vias (Fig. 1L).
As for claim 17, Chen et al. disclose the method of claim 15, wherein forming the gap-fill dielectric 300 comprises forming an epoxy material [0033] on the first integrated circuit die and on the second integrated circuit die (Fig. 1B-1L).
As for claim 18, Chen et al. disclose the method of claim 15, further comprising:
forming a through-dielectric via (310/outer 312) extending through the first dielectric layer 302 and through the gap-fill dielectric 300a;
depositing a second dielectric layer 314 on the through-dielectric via, the conductive vias, and the first dielectric layer (Fig. 1L); and
forming conductive lines 315 in the second dielectric layer, the conductive lines extending through the second dielectric layer to contact the through-dielectric via and the conductive vias (Fig. 1L).
As for claim 20, Chen et al. disclose the method of claim 15, wherein bonding the first front-side of the first integrated circuit die to the second front-side of the second integrated circuit die comprises bonding the first integrated circuit die to a wafer 10 comprising the second integrated circuit die (Fig. 1A), the gap-fill dielectric 300 is formed on the wafer (Fig. 1B-1L), and the method further comprises: singulating the wafer, wherein the second integrated circuit die, the gap-fill dielectric, and the first dielectric layer are laterally coterminous after singulating the wafer (fig. 1L, [0065]).
Claim Rejections - 35 USC § 103
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 15, 16, 21-22, 24-26, 28, 35, 37 and 39 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2021/0020601, as disclose in previous office action) in view of Yu et al. (US 2008/0142990).
As for claims 15 and 21, Chen et al. disclose in Figs. 1A-1H or 2A-2B and the related text a method comprising:
bonding a first front-side (lower surface) of a first integrated circuit die (a first upper integrated circuit die) 200 to a second front-side (upper surface) of a second integrated circuit die (a lower integrated circuit die) 100 in face-to-face manner (Fig. 1B), the first integrated circuit die 200 comprising a (first) semiconductor substrate 202 and a (first) through-substrate via TSV (Fig. 1B);
forming a gap-fill dielectric BL/BS/F1-1/F1-2/F2-1/F2-2 on (around) the first (upper) integrated circuit die and on the second integrated circuit die (Fig. 1C, 2A);
planarizing the gap-fill dielectric BL/BS/F1-1/F1-2/F2-1/F2-2 until the gap-fill dielectric, the semiconductor substrate 202, and the through-substrate via TSV have top surfaces that are substantially coplanar (Fig. 1C-1F, [0043]-[0045]); and
forming an interconnect structure 302/308 over the gap-fill dielectric, interconnect structure comprising a first dielectric layer 304 and first conductive vias 306/308,
wherein depositing the first dielectric layer 304 on the top surfaces of the gap-fill dielectric, the semiconductor substrate, and the through-substrate via (Fig. 1H/2A, [0052]);
the conductive vias 306/308 in the first dielectric layer (Fig. 1H/2A, [0052]), the conductive vias 306/308 extending through the first dielectric layer to contact the top surface of the through-substrate via TSV (Fig. 1H, 2A).
Chen et al. do not disclose the top surface of the through-substrate via is in physical contact with a plurality of the (first) conductive vias.
Yu et al. teach in Fig. 11 and the related text a top surface of the through-substrate via 64 is in physical contact with a plurality of the (first) conductive vias 66.
Chen et al. and Yu et al. are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chen et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Chen et al. to include the limitations as taught by Yu et al. in order to improve interconnections.
As for claims 16 and 26, Chen et al. disclose the method of claim 15, wherein forming the gap-fill dielectric BL/BS/F1-1/F1-2/F2-1/F2-2 comprises forming a nitride-oxide-nitride-oxide structure on the first integrated circuit die and on the second integrated circuit die [0064].
As for claim 22, Chen et al. disclose the method of claim 21, wherein the interconnect structure further comprises a second dielectric layer 310 and a first conductive line 312, the second dielectric layer 310 extending along the first dielectric layer 304, the first conductive line 312 extending through the second dielectric layer to contact each of the first conductive vias (Fig. 1H).
As for claim 24, Chen et al. disclose the method of claim 21, wherein (a portion of) a width of each of the first conductive vias is less than half a (entire) width of the first through-substrate via.
As for claim 25, Chen et al. disclose the method of claim 21, wherein each of the first conductive vias TSV is spaced apart from the first semiconductor substrate 202 (FIG. 1H/2A).
As for claim 26, Chen et al. disclose the method of claim 21, wherein the gap-fill dielectric comprises a nitride-oxide-nitride-oxide structure [0064].
As for claim 28, Chen et al. disclose the method of claim 21, further comprising: bonding a second upper integrated circuit die 200 to the lower integrated circuit die in a face- to-face manner (FIG. 1B-1H/2A), the second upper integrated circuit die comprising a second semiconductor substrate 202 and a second through-substrate via TSV, the gap-fill dielectric formed around the second upper integrated circuit die, the top surface of the gap-fill dielectric being substantially coplanar with a top surface of the second semiconductor substrate and with a top surface of the second through-substrate via (FIG. 1H/2A ); and wherein the interconnect structure further comprises second conductive vias 306/308, each of the second conductive vias extending through the first dielectric layer 304 to contact the top surface of the second through-substrate via (FIG. 1H/2A).
Chen et al. do not disclose the top surface of the second through-substrate via is in physical contact with a plurality of the second conductive vias.
Yu et al. teach in Fig. 11 and the related text a top surface of the through-substrate via 64 of 38 is in physical contact with a plurality of the (second) conductive vias 66.
Chen et al. and Yu et al. are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chen et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Chen et al. to include the limitations as taught by Yu et al. in order to improve interconnections.
As for claim 35, Chen et al. disclose in Figs. 1A-1H or 2A-2B and the related text a method comprising:
bonding a front-side (lower side) of a first upper integrated circuit die (left 200) and a front-side (lower side) of a second upper integrated circuit die (right 200) to a front-side (upper side) of a lower integrated circuit die 100, the first upper integrated circuit die comprising a first semiconductor substrate 202 and a first through-substrate via TSV, the second upper integrated circuit die comprising a second semiconductor substrate 202 and a second through-substrate via TSV (Fig. 1B/2A);
forming a gap-fill dielectric BL/BS/F1-1/F1-2/F2-1/F2-2 around the first upper integrated circuit die and around the second upper integrated circuit die (Fig. 1D-1E), the gap-fill dielectric filling a gap between the first upper integrated circuit die and the second upper integrated circuit die (Fig. 1D-1H and 2A);
planarizing the gap-fill dielectric BL/BS/F1-1/F1-2/F2-1/F2-2 until the gap-fill dielectric, the first semiconductor substrate 202, the second semiconductor substrate 202, the first through-substrate via TSV, and the second through-substrate via TSV have coplanar top surfaces (Fig. 1D-1F-2A, [0043]-[0045]);
depositing a first dielectric layer 304 on the coplanar top surfaces of the gap-fill dielectric, the first semiconductor substrate, the second semiconductor substrate, the first through-substrate via, and the second through-substrate via (Fig. 1H/2A, [0052]); and
forming first conductive vias 306/308 and second conductive vias 306/308 in the first dielectric layer 304 with a single damascene process [0052], the first conductive vias each extending through the first dielectric layer to contact the top surface of the first through-substrate via, the second conductive vias each extending through the first dielectric layer to contact the top surface of the second through- substrate via (Fig. 1H/2A).
Chen et al. do not disclose the top surface of the first through-substrate via is in physical contact with a plurality of the first conductive vias and the top surface of the second through-substrate via is in physical contact with a plurality of the second conductive vias.
Yu et al. teach in Fig. 11 and the related text a top surface of the first through-substrate via (64 of 36) is in physical contact with a plurality of the first conductive vias (left 66) and a top surface of the second through-substrate via (64 of 38) is in physical contact with a plurality of the second conductive vias (right 66).
Chen et al. and Yu et al. are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chen et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Chen et al. to include the limitations as taught by Yu et al. in order to improve interconnections.
As for claim 37, Chen et al. disclose the method of claim 35, wherein forming the gap-fill dielectric comprises forming a nitride-oxide-nitride-oxide structure around the first upper integrated circuit die and around the second upper integrated circuit die (Fig. 2A, [0064]).
As for claim 39, Chen et al. disclose the method of claim 35, wherein (a portion of) a width of each of the first conductive vias 306/308 is less than half a (entire) width of the first through-substrate via TSV, and (a portion of) a width of each of the second conductive vias is less than half a (entire) width of the second through-substrate via.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2021/0020601) in view of Yu et al. (US 2008/0142990) and further in view of Tseng et al. (US 2020/00105738, as disclose in previous office action).
As for claim 19, Chen et al. disclose the method of claim 15, further comprising:
depositing a second dielectric layer 314 on the conductive vias and the first dielectric layer 302 (Fig. 1L);
forming conductive lines 315 in the second dielectric layer 314, the conductive lines 315 extending through the second dielectric layer to contact the conductive vias (Fig. 1L);
depositing a third dielectric layer 316 on the conductive lines and the second dielectric layer (Fig. 1L); and
forming conductive features 317 in the third dielectric layer (Fig. 1L), wherein the conductive vias (inner) and the conductive lines 315 are each formed in a single damascene process (Fig. 1L).
Chen et al. do not disclose the conductive features are formed in a dual damascene process.
Tseng et al. disclose in Fig. 1 and the related text a conductive features 115/119 are formed in a dual damascene process [0023].
Chen et al. and Tseng et al. are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chen et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Chen et al. to include the limitations as taught by Tseng et al. in order to provide suitable process (Tseng et al. [0023]).
Claims 23, 27, 29, 36 and 38 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. in view of Yu et al. and further in view of Chen et al. (US 2021/0098423, as disclose in previous office action).
As for claims 27, 29, 36 and 38, Chen et al. disclose the method of claims 21 and 35, wherein forming the gap-fill dielectric comprises silicon oxide or silicon nitride around the first upper integrated circuit die 200 and around the second upper integrated circuit die 200 (Fig. 1C-1E).
Chen et al. do not disclose forming third conductive (through dielectric) vias in the gap-fill dielectric and in the first dielectric layer, wherein the interconnect structure further comprises a conductive line contacting the through-dielectric via and each of the first conductive vias; the gap-fill dielectric comprises forming an epoxy material; and the interconnect structure further comprises a third dielectric layer and conductive features, the third dielectric layer extending along the second dielectric layer, the conductive features comprising second conductive lines and second conductive vias in the third dielectric layer.
Chen et al. disclose in Fig. 1A-1L and the related text forming third (through dielectric) conductive vias 312 in the gap-fill dielectric 300a and in the first dielectric layer 302, wherein the interconnect structure further comprises a conductive line 317 contacting the through-dielectric via and each of the first conductive vias 315; the gap-fill dielectric 300a comprises forming an epoxy material [0035]; and the interconnect structure further comprises a third dielectric layer 316 and conductive features 317/318, the third dielectric layer 316 extending along the second dielectric layer 314, the conductive features 317/318 comprising second conductive lines 317 and second conductive vias 318 in the third dielectric layer 316 (Fig. 1L).
Chen et al. and Chen et al. are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chen et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Chen et al. to include the limitations as taught by Chen et al. in order to interconnections.
Response to Arguments
Applicant’s arguments with respect to claim(s) 15, 16, 19, 21-23, 24-27, 28-29, 35 and 37-39 is have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s arguments, with respect to claim 15 rejection that Chen et al. do not disclose “the top surface of the through-substrate via 209 is in physical contact with a plurality of the conductive vias” have been fully considered but they are not persuasive in view of the following reasons. Fig. 1L of Chen et al. clearly teach the top surface of the through-substrate via 209 is in physical contact with a plurality of the conductive vias 312. Therefore, Chen et al. still disclosed the claimed invention.
In view of the foregoing reasons, the Examiner believes that all Applicant’s arguments and remarks are addressed. The Examiner has determined that the previous Office Action is still proper based on the above responses. Therefore, the rejections are sustained and maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached on Monday-Thursday (9am-4pm).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 5712721670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TRANG Q TRAN/Primary Examiner, Art Unit 2811
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