DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Claim Rejections - 35 USC § 103 3
A. Claims 12 and 42 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0139794 (“Nishimura”) in view of US 2018/0138272 (“Ebihara”). 3
III. Allowable Subject Matter 6
IV. Response to Arguments 8
Conclusion 8
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 12 and 42 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0139794 (“Nishimura”) in view of US 2018/0138272 (“Ebihara”).
Claims 12 and 42 read,
12. (Currently Amended) A semiconductor device comprising:
[1] a silicon carbide substrate;
[2] a multi-layer structure provided on the silicon carbide substrate; and
[3a] a spacer dielectric layer provided over the multi-layer structure to form a sidewall on an inherent outer edge of the multi-layer structure,
[3b] the spacer dielectric layer directly contacting at least three sequentially-stacked dielectric layers of the multi-layer structure and also directly contacting the silicon carbide substrate; and
[4a] an encapsulation layer on the spacer dielectric layer opposite the multi-layer structure,
[4b] the encapsulation layer on the sidewall and directly contacting an upper surface of the silicon carbide substrate.
42. (New) The semiconductor device of Claim 12, wherein the encapsulation layer and the spacer dielectric layer contact the silicon carbide substrate adjacent a dicing street.
With regard to claim 12, Nishimura discloses, generally in Figs. 11 and 12,
12. (Currently Amended) A semiconductor device comprising:
[1] a silicon carbide substrate 1 [¶¶ 100-101];
[2] a multi-layer structure 2/3/4/6 provided on the silicon carbide substrate 1 [¶¶ 85, 29, 31-33]; and
[3a] a spacer dielectric layer 41, 15 [¶¶ 87, 91] provided over the multi-layer structure 2/3/4/6 to form a sidewall on an inherent outer edge of the multi-layer structure 2/3/4/6,
[3b] the spacer dielectric layer 41, 15 directly contacting at least three sequentially-stacked dielectric layers 2/3/4/6 [i.e. all 4 layers] of the multi-layer structure 2/3/4/6 and also directly contacting the silicon carbide substrate 1 [as shown in each of Figs. 11 and 12]; and
[4a] an encapsulation layer 7 [¶ 87] on the spacer dielectric layer 41, 15 opposite the multi-layer structure 2/3/4/6,
[4b] the encapsulation layer 7 on the sidewall and directly contacting … the silicon carbide substrate 1 [as shown in each of Figs. 11 and 12].
42. (New) The semiconductor device of Claim 12, wherein the encapsulation layer and the spacer dielectric layer contact the silicon carbide substrate adjacent a dicing street.
With regard to feature [4b] of claim 12, while the encapsulation layer 7 in each of Figs. 11 and 12 is on the upper surface of the SiC substrate 1 and directly contacts the side surface of the SiC substrate 1, Nishimura does not teach that the encapsulation layer 7 directly contacts the upper surface of SiC substrate 1.
Ebihara, like Nishimura, teaches an semiconductor device formed in/on a SiC substate 1 including a protective polyimide layer 6 on which is deposited a resin encapsulation 8 that contacts the side surface of the SiC substrate 1 (Ebihara: e.g. Fig. 1; ¶¶ 22-24, 29). Ebihara further teaches that the encapsulation layer 8 directly contacts the outermost edge of the upper surface of the SiC substrate 1.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to position the end portion of the spacer dielectric layer 15, 42 of the in Nishimura away from the outermost edge of the upper surface of the SiC substrate 1, such that the encapsulation layer 7 of Nishimura directly contacts said outermost edge of the upper surface of the SiC substrate 1 because Ebihara teaches that it is suitable to have the encapsulation directly contact entire edge corner of the SiC substrate 1. (See MPEP 2143.)
Moreover, it has been held that changes in configuration are obvious absent that a particular configuration is significant. See In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.)
So modified each of the spacer layer 15, 41 and the encapsulation 7 directly contacts the upper surface of the SiC substrate 1 adjacent to the dicing street, i.e. at least the side surface of the SiC substrate 1 (Nishimura: Fig. 8).
This is all of the limitations of claims 12 and 42.
III. Allowable Subject Matter
Claims 1-3, 5-7, 9-11, 15, 25-29, 30, and 34 are allowed.
Claims 1-3, 5-7, 9-11, 25-27, 29, and 30 were previously indicated to be allowable. The reasons for finding these claims allowable is provided in the Final Rejection mailed 02/13/2026 at page 8.
The reasons for finding claims 15, 28, and 34 allowable are explained in the Non-Final Rejection mailed 04/20/2026 at pages 5-6.
As repeated from the Non-Final Rejection mailed 04/20/2026 at pp. 6-7, Claims 14 and 36-41 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 14 reads,
14. (Previously Presented) The semiconductor device of claim 12, wherein the three sequentially-stacked dielectric layers of the multi-layer structure comprises:
[1] a gate oxide layer provided on the silicon carbide substrate;
[2] an inter-layer dielectric (ILD) layer provided over the gate oxide layer and the field oxide layer; and
[3] a final passivation layer provided over the ILD layer;
[4] the multi-layer structure further comprising a field oxide layer provided on the surface and adjacent to the gate oxide layer;
[5] wherein each of the gate oxide layer, the ILD layer, and the final passivation layer is terminated at an inner edge of the sidewall.
The prior art does not reasonably teach or suggest—in the context of claim 14—the limitations recited therein.
Claim 36 reads,
36. (Previously Presented) The semiconductor device of claim 12, wherein the three sequentially- stacked dielectric layers of the multi-layer structure comprise:
[1] a field oxide layer provided on the silicon carbide substrate;
[2] an inter-layer dielectric (ILD) layer provided over the field oxide layer; and
[3] a final passivation layer provided over the ILD layer.
The prior art does not reasonably teach or suggest—in the context of claim 36—the limitations recited therein.
Claim 37 is allowable for including the same allowable limitations by depending from claim 36.
Claim 38 reads,
38. (Currently Amended) The semiconductor device of claim 12, wherein the three sequentially- stacked dielectric layers of the multi-layer structure comprise:
[1] a gate oxide layer provided on the silicon carbide substrate;
[2] an inter-layer dielectric (ILD) layer provided over the gate oxide layer; and a final passivation layer provided over the ILD layer,
[3] wherein the multi-layer structure further comprises a field oxide layer that is provided adjacent the gate oxide layer,
[4] wherein the inter-layer dielectric layer is also provided over the field oxide layer.
The prior art does not reasonably teach or suggest—in the context of claim 38—the limitations recited therein.
Claim 39 reads,
39. (Previously Presented) The semiconductor device of Claim 12, wherein
[1] the silicon carbide substrate includes a recess, and
[2] at least one of the spacer dielectric layer and the encapsulation layer extend into the recess.
The prior art does not reasonably teach or suggest—in the context of claim 39—the limitations recited therein.
Claims 40 and 41 would be allowable for including the same allowable limitations by depending from claim 39.
IV. Response to Arguments
Applicant’s arguments filed 06/17/2022 have been fully considered but they are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant’s amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK KIELIN whose telephone number is (571)272-1693. The examiner can normally be reached Mon-Fri: 10:00 AM-7:00 PM.
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814
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