DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
As of October 1, 2025, no information disclosure statement has been made of record.
Drawing Objections
Examiner withdraws the drawing objections based upon Applicant’s amendments to the claims.
Claim Rejections - 35 USC § 112(a)
Examiner withdraws the 35 USC § 112(a) based upon Applicant’s amendment to claim 15.
Claim Rejections - 35 USC § 112(b)
Examiner withdraws some of the previous 35 USC § 112(b) rejections based upon Applicant’s amendments to claims 14-15. However, the following rejection is maintained.
Claims 1-6, 8, and 11-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 1, and 15
Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term “second gate” in claim 1 is used by the claim to mean “a charge trap layer, or an ONO layer, or a high-k layer,” (see Applicant’s ¶ 0032-34) while the accepted meaning is “conductive layer, or metal layer, or poly-si layer.” The term is indefinite because the specification does not clearly redefine the term.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 5-6, 8, 11-13, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dong et al. (US 2019/0304987 A1) (“Dong”), in view of Chiang et al. (US 2005/0199959 A1) (“Chiang”), in view of Sharma et al. (US 2020/0091274 A1) (“Sharma”).
Regarding claim 1,
Examiner will be using Dong to teach the claimed structure of the device using a top gate transistor. Chiang is being used to show that a top gate transistor is an obvious variant of a bottom gate transistor.
Dong teaches at least in figure 1A:
a gate structure (detailed below; hereinafter “A”) comprising
a first gate (102),
a second gate (106), and
a tunneling layer (104) sandwiched there-between (104 is between 102 and 106);
a ferroelectric structure (108) over and electrically connected with the gate structure (A);
a channel structure (110) over the ferroelectric structure (108).
As previously stated Dong teaches a top gate transistor, while it appears Applicant is claiming a bottom gate transistor.
Chiang teaches at least in figures 1A-1C,
That a top gate transistor (figure 1C) is an obvious variant of a bottom gate transistor (figure 1B). Because these two transistors are obvious variants of each other it would have been obvious to rearrange the top gate parts of Chiang to form a bottom gate transistor. MPEP 2144.04(VI)(C).
Dong does not teach:
a plurality of contact structures over the channel structure and laterally spaced apart with each other by a predetermined distance,
wherein sidewalls of the first gate are aligned with sidewalls of the plurality of contact structures.
Sharma teaches at least in figures 1,
A bottom gate transistor
a plurality of contact structures (111/113) over the channel structure (109) and laterally spaced apart with each other by a predetermined distance (111/113 are so spaced),
It would have been obvious to one of ordinary skill in the art to use the bottom-gate structure of Sharma in the device of Dong as Chiang teaches this is an obvious variant of the top-gate structure of Dong.
The combination of Sharma and Dong teach:
wherein the contact structures (Sharma 111/113) are spaced apart from the ferroelectric structure (Dong 108) by the channel structures (Sharma 109).
Regarding claim 2, The combination of Sharma and Dong teach:
wherein a length of the second gate (Dong 102) is greater than the predetermined distance (this is obvious based upon the structure of Sharma where Dong 102 would extend to the same length as the channel and gate electrode of Sharma).
Regarding claim 5, Dong teaches at least in figure 1A:
wherein a material of the ferroelectric structure (108) includes silicon doped hafnium oxide (¶ 0029).
Regarding claim 6, the prior art does not teach:
Wherein the predetermined distance is the same as a length of the second gate.
This appears to be a change in size or proportion of the gate structure. The court has held in In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), that where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. There is no evidence the claimed device would perform differently than the prior art device. Further, there is no persuasive evidence the particular claimed dimension is significant when compared to the prior art. Thus, this claim is not patentably distinct from the prior art.
Regarding claim 8, Dong teaches at least in figure 1A:
wherein sidewalls of the tunneling layer (104) are aligned with sidewalls of the first gate (102) and sidewalls of the second gate (106).
Regarding claim 11, the prior art does not teach:
wherein a height of the first gate (102) is larger than a height of the second gate (106).
However, this appears to be a change in size or proportion of the gate structure. The court has held in In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), that where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. There is no evidence the claimed device would perform differently than the prior art device. Further, there is no persuasive evidence the particular claimed dimension is significant when compared to the prior art. Thus, this claim is not patentably distinct from the prior art.
Further, one of ordinary skill in the art using routine skill in the art would be able to ascertain the required thicknesses of each of the layers in order for the device to function as described. This would require only routine skill in the art, and the choice of thickness of each structural element, and the relationship of thicknesses between each structural element would be known to those of ordinary skill in the art.
Regarding claim 12,
Claim 12 would be obvious for the same reasons given in claims 6-7 and 11 above.
Regarding claim 13,
Claim 13 is claiming a characteristic of the device when it is used. It would have been obvious that the prior art having the same structure would have this same claimed characteristic when used as it has the same structural elements as claimed. See MPEP 2112.
Regarding claim 15, Dong teaches at least in figure 1A:
a gate structure gate structure (detailed below; hereinafter “A”),
wherein the gate structure (A) comprises (detailed below)
a first gate (102),
a second gate (106), and
a tunneling layer (104) sandwiched there-between (104 is so sandwiched);
a ferroelectric structure (108) disposed on the second gate (106) of the gate structure (A);
a channel structure (110) disposed on the ferroelectric structure (108), and
Dong does not teach:
A plurality of contact structures electrically connected with the channel structure and laterally separated with each other,
Wherein the contact structures are not in contact with the ferroelectric structure.
Chiang teaches at least in figures 1A-1C,
That a top gate transistor (figure 1C) is an obvious variant of a bottom gate transistor (figure 1B). Because these two transistors are obvious variants of each other it would have been obvious to rearrange the top gate parts of Chiang to form a bottom gate transistor. MPEP 2144.04(VI)(C).
Sharma teaches at least in figures 1,
A bottom gate transistor
a plurality of contact structures (111/113) electrically connected with the channel structure (109) laterally separated with each other (Sharma in figure 1 shows this).
It would have been obvious to one of ordinary skill in the art to use the bottom-gate structure of Sharma in the device of Dong as Chiang teaches this is an obvious variant of the top-gate structure of Dong.
The combination of Sharma and Dong teach:
wherein the contact structures (Sharma 111/113) are not in contact with the ferroelectric structure (Dong 108) (Dong 108 is spaced apart from Sharma 111/113 by the channel structures Sharma 109).
Claim(s) 3-4, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dong, in view of Chiang, in view of Sharma, in view of Ohguro et al. (US 2015/0249156 A1) (“Ohguro”).
Regarding claims 3 and 16, Ohguro teaches at least in figure 1:
further comprising a plurality of sidewall structures (222) covering a bottom surface and two opposite side surfaces of the contact structures (12/13)
It would have been obvious to one of ordinary skill in the art to replace the silicon channel Dong with the oxide semiconductor material channel of Ohguro as it is known in the art that oxide semiconductor material can be formed at lower temperatures, and can act as a storage layer unlike silicon. However, as one makes the transistor channel shorter one gets a deterioration of the threshold voltage. ¶ 0003-04. In order to counteract this one would include another oxide semiconductor material as the source and drain liner to prevent the formation of a hole trap in the oxide semiconductor material channel, ¶ 0034, and prevent degradation of the threshold voltage. ¶ 0035. By forming said oxide semiconductor material liner (222) one can keep the reactants away from the channel even in smaller gate length devices and when the device is heated during the course of fabrication. ¶ 0037.
Regarding claim 4, Ohguro teaches at least in figure 1:
wherein sidewall structures (220) are in contact with the channel structure (220), and
the contact structures (12/13) are spaced apart from the channel structure (220) by the sidewall structures (222).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dong, in view of Chiang, in view of Sharma, in view of Ito et al. (US 2006/0077713 A1) (“Ito”).
Regarding claim 14, Dong does not explicity state:
wherein the floating gate (106) comprises a triple dielectric structure includes oxide-nitride-oxide, or ONO film.
Dong teaches:
The floating gate (106) can comprise dielectric charge trapping material in layers. ¶ 0026.
Ito teaches:
The charge storage layer (Dong 106) can comprise a ONO layer formed of SiO, SiN, and SiON. ¶ 0077.
This is consistent with Dong. Based upon Ito it would have been obvious to one of ordinary skill in the art that when Dong teaches charge storage layers that said layer can be an ONO layer as described by Ito.
Response to Arguments
Applicant’s amendments have overcome the previous grounds of rejection. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of previous prior art in view of Sharma as indicated above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/VINCENT WALL/ Primary Examiner, Art Unit 2898