DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
As of April 27, 2026, no information disclosure statement has been made of record.
Claim Rejections - 35 USC § 112(b)
Examiner withdraws the 35 USC § 112(b) based upon Applicant’s amendments to claims 1 and 15.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 15-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 15,
The term “the ferroelectric layer” lacks antecedent basis in the claim. Previously, Applicant used the term “a ferroelectric structure”. For purposes of examination only Examiner will treat the terms as being synonymous.
The term “the channel layer” lacks antecedent basis in the claim. Previously, Applicant used the term “a channel structure”. For purposes of examination only Examiner will treat the terms as being synonymous.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dong et al. (US 2019/0304987 A1) (“Dong”), in view of Chiang et al. (US 2005/0199959 A1) (“Chiang”), in view of Sharma et al. (US 2020/0091274 A1) (“Sharma”).
Regarding claim 15, Dong teaches at least in figure 1A-1C:
a gate structure, the gate structure (detailed below; hereinafter “A”) (detailed below),
a first gate (102),
a second gate (106), and
a tunneling layer (104) interposed between the first gate (102) and the second gate (106),
wherein the second gate (106) includes a charge trapping layer (106b);
a ferroelectric structure (108) disposed on the second gate (106) of the gate structure (A);
a channel structure (110) disposed on the ferroelectric structure (108), and
wherein the first gate (102) and the tunneling layer (104) have first sidewalls aligned with each other (sidewalls of 102 and 104 are so aligned),
the ferroelectric layer (108) and the channel layer (110) have second sidewalls aligned with each other (108 and 110 are so aligned).
Dong does not teach:
the first sidewalls are laterally offset from the second sidewalls;
However, the amount of lateral offset is not claimed. Therefore, it would have been obvious that one of ordinary skill in the art making the device of the prior art would have obviously met this limitation based upon standard process variations when overlaying one layer on top of another.
Dong does not teach:
A plurality of contact structures electrically connected with the channel structure and laterally separated with each other,
Wherein the contact structures are not in contact with the ferroelectric structure.
Chiang teaches at least in figures 1A-1C,
That a top gate transistor (figure 1C) is an obvious variant of a bottom gate transistor (figure 1B). Because these two transistors are obvious variants of each other it would have been obvious to rearrange the top gate parts of Chiang to form a bottom gate transistor. MPEP 2144.04(VI)(C).
Sharma teaches at least in figures 1,
A bottom gate transistor
a plurality of contact structures (111/113) electrically connected with the channel structure (109) laterally separated with each other (Sharma in figure 1 shows this).
It would have been obvious to one of ordinary skill in the art to use the bottom-gate structure of Sharma in the device of Dong as Chiang teaches this is an obvious variant of the top-gate structure of Dong.
The combination of Sharma and Dong teach:
wherein the contact structures (Sharma 111/113) are not in contact with the ferroelectric structure (Dong 108) (Dong 108 is spaced apart from Sharma 111/113 by the channel structures Sharma 109).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dong, in view of Chiang, in view of Sharma, in view of Ohguro et al. (US 2015/0249156 A1) (“Ohguro”).
Regarding claim 16, Ohguro teaches at least in figure 1:
further comprising a plurality of sidewall structures (222) covering a bottom surface and two opposite side surfaces of the contact structures (12/13)
It would have been obvious to one of ordinary skill in the art to replace the silicon channel Dong with the oxide semiconductor material channel of Ohguro as it is known in the art that oxide semiconductor material can be formed at lower temperatures, and can act as a storage layer unlike silicon. However, as one makes the transistor channel shorter one gets a deterioration of the threshold voltage. ¶ 0003-04. In order to counteract this one would include another oxide semiconductor material as the source and drain liner to prevent the formation of a hole trap in the oxide semiconductor material channel, ¶ 0034, and prevent degradation of the threshold voltage. ¶ 0035. By forming said oxide semiconductor material liner (222) one can keep the reactants away from the channel even in smaller gate length devices and when the device is heated during the course of fabrication. ¶ 0037.
Allowable Subject Matter
Claims 1-6, 8, and 11-14 are allowed.
The following is an examiner’s statement of reasons for allowance: see below.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Regarding claim 1,
Examiner will be using Dong to teach the claimed structure of the device using a top gate transistor. Chiang is being used to show that a top gate transistor is an obvious variant of a bottom gate transistor.
Dong teaches at least in figure 1A-1C:
a gate structure (detailed below; hereinafter “A”) comprising
a first gate (102),
a second gate (106), and
a tunneling layer (104) sandwiched there-between (104 is between 102 and 106),
wherein the second gate (106) includes a charge trapping layer (¶¶ 0025-26, where 106 is a floating gate which may include a charge trapping layer 106b);
a ferroelectric structure (108) over and electrically connected with the gate structure (A);
a channel structure (110) over the ferroelectric structure (108).
As previously stated, Dong teaches a top gate transistor, while it appears Applicant is claiming a bottom gate transistor.
Chiang teaches at least in figures 1A-1C,
That a top gate transistor (figure 1C) is an obvious variant of a bottom gate transistor (figure 1B). Because these two transistors are obvious variants of each other it would have been obvious to rearrange the top gate parts of Chiang to form a bottom gate transistor. MPEP 2144.04(VI)(C).
Dong does not teach:
a plurality of contact structures over the channel structure and laterally spaced apart with each other by a predetermined distance,
wherein sidewalls of the first gate are aligned with sidewalls of the plurality of contact structures.
Sharma teaches at least in figures 1,
A bottom gate transistor
a plurality of contact structures (111/113) over the channel structure (109) and laterally spaced apart with each other by a predetermined distance (111/113 are so spaced),
It would have been obvious to one of ordinary skill in the art to use the bottom-gate structure of Sharma in the device of Dong as Chiang teaches this is an obvious variant of the top-gate structure of Dong.
The combination of Sharma and Dong teach as shown in Examiner figure 1 (references are to Examiner’s figure 1):
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a first dielectric layer (A) laterally encapsulating the first gate (102) and the tunneling layer (104);
a second dielectric layer (B) formed on the first dielectric layer (A),
wherein the second dielectric layer (A) is disposed along sidewalls of the second gate (106), the ferroelectric structure (108) and the channel structure (109), and
wherein the contact structures (Sharma 111/113) are spaced apart from the ferroelectric structure (Dong 108) by the channel structures (Sharma 109).
The previous prior art does not teach:
the second dielectric layer further extends onto a surface of the ferroelectric structure facing away from the channel structure;
Response to Arguments
Applicant's arguments filed April 21, 2026 have been fully considered but they are not persuasive.
Applicant asserts the prior art does not teach the claimed structure of claim 15. While the claimed structure is not explicitly disclosed it would have been obvious to one of ordinary skill in the art due to standard process variations in semiconductor manufacturing.
Conclusion
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/VINCENT WALL/ Primary Examiner, Art Unit 2898
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