Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
This office action is in response to response to Election/Restriction filed on 02/02/26.
Summary of claims
Claims 1-29 are pending.
Claims 10-29 are rejected.
Claims 1-9 are withdrawn.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 10-29 rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tien et al. (US Pub. 2022/0084945).
As to claim 10 the prior art teaches a method for generating a layout of a semiconductor device, comprising:
placing a first cell (see fig 2A element 102b) and a second cell (see fig 2A element 102b) adjacent to the first cell in the layout, wherein the first cell has a first height different from a second height of the second cell (see fig 2A, 2B element 102b, element 202c paragraph 0015, and 0026-0030);
disposing a first polysilicon pattern in the first cell extending along a first direction and a second polysilicon pattern in the second cell extending along the first direction (see fig 1-2 paragraph 0022-0027);
designating a plurality of first tracks in the first cell extending along a second direction different from the first direction (see fig 1-2 paragraph 0020-0024);
and designating a plurality of second tracks in the second cell extending along the second direction, wherein two adjacent ones of the plurality of first tracks are spaced apart by a first pitch, and two adjacent ones of the plurality of second tracks are spaced apart by a second pitch, wherein the first pitch is greater than the second pitch (see fig 1-3 paragraph 0028-0033).
As to claim 11 and 25 the prior art teaches further comprising disposing a plurality of first metal segments on one or more of the plurality of first tracks (see fig 1 paragraph 0015-0020).
As to claim 12, 21 and 26 the prior art teaches wherein two adjacent metal segments of the plurality of first metal segments disposed on the same track in the first cell are spaced apart by a distance (see fig 1 paragraph 0018-0022).
As to claim 13, 22 and 27 the prior art teaches wherein the distance is determined based on a width of the first cell and a number of the plurality of first metal segments in the same track in the first cell (see fig 1-2 paragraph 0021-0025).
As to claim 14 and 28 the prior art teaches further comprising disposing a plurality of second metal segments on one or more of the plurality of second tracks, wherein the plurality of first metal segments has a width greater than a width of the plurality of second metal segments (see fig 1-2 paragraph 0024-0028).
As to claim 15, 23 and 29 the prior art teaches wherein the first height of the first cell in the layout exceeds the second height of the second cell in the layout (see fig 1-2 paragraph 0026-0029).
As to claim 16 and 20 the prior art teaches wherein the plurality of first tracks in the first cell has a number identical to that of the plurality of second tracks in the second cell (see fig 1-2 paragraph 0029-0034).
As to claim 17 the prior art teaches further comprising: generating a tape out file for manufacturing the semiconductor device according to the layout (see fig 2-4 paragraph 0035--0042).
As to claim 18 the prior art teaches a non-transitory computer-readable medium storing computer-executable instructions, when the computer-executable instructions are executed on a computer system, the computer system is caused to:
place a first cell and a second cell adjacent to the first cell in the layout, wherein the first cell has a first height different from a second height of the second cell (see fig 2A, 2B element 102b, element 202c paragraph 0015, and 0026-0030);
dispose a polysilicon pattern in the first cell extending along a first direction (see fig 1-2 paragraph 0022-0027);
designate a plurality of first tracks in the first cell extending along a second direction different from the first direction (see fig 1-2 paragraph 0020-0024);
and designate a plurality of second tracks in the second cell extending along the second direction, wherein two adjacent ones of the plurality of first tracks are spaced apart by a first pitch, and two adjacent ones of the plurality of second tracks are spaced apart by a second pitch, wherein the first pitch is greater than the second pitch (see fig 1-3 paragraph 0028-0033).
As to claim 19 the prior art teaches wherein the computer system is further caused to: dispose a plurality of first metal segments on the plurality of first tracks (see fig 1 paragraph 0015-0020);
and dispose a plurality of second metal segments on the plurality of second tracks, wherein the plurality of first metal segments has a width greater than a width of the plurality of second metal segments (see fig 1-2 paragraph 0024-0028).
As to claim 24 the prior art teaches a method for generating a layout of a semiconductor device, comprising:
placing a first cell and a second cell adjacent to the first cell in the layout, wherein the first cell has a first height different from a second height of the second cell (see fig 2A, 2B element 102b, element 202c paragraph 0015, and 0026-0030);
disposing a polysilicon pattern in the first cell extending along a first direction (see fig 1-2 paragraph 0022-0027);
designating a plurality of first tracks in the first cell extending along a second direction different from the first direction (see fig 1-2 paragraph 0020-0024);
and designating a plurality of second tracks in the second cell extending along the second direction, wherein two adjacent ones of the plurality of first tracks are spaced apart by a first pitch, and two adjacent ones of the plurality of second tracks are spaced apart by a second pitch, wherein the first pitch is different from the second pitch (see fig 1-3 paragraph 0028-0033).
Conclusion
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on 571 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BINH C TAT/Primary Examiner, Art Unit 2851