DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on Jun. 26th 2026 has been entered. Claims 1-20 remain pending in the application.
Claim Objections
Claim 8 is objected to because of the following informalities:
In claim 8, line 20, “wheiren" should read “wherein”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 8-11 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 20210313449) in view of Lee et al. (US 20180151564).
Regarding claim 8, Lin teaches a method of manufacturing a semiconductor device (Abstract), the method comprising:
forming a multi-layer stack (fig. 1B, first semiconductor layers 104, second semiconductor layers 106; para. 0017) over a substrate (substrate 101; para. 0017), the multi-layer stack (104, 106) comprising:
a first semiconductor material (106 with silicon germanium; para. 0018); and
a second semiconductor material (104 with Si; para. 0018) different (104 and 106 are made of different materials; para. 0018) from the first semiconductor material (silicon germanium), wherein the first semiconductor material (106) and the second semiconductor material (104) are in alternating layers within the multi-layer stack (104, 106);
forming a first set of nanostructures (fig. 4B, 106) from the first semiconductor material (106);
forming a second set of nanostructures (104) from the second semiconductor material (104);
removing the first set of nanostructures (fig. 5B, 106 removed);
forming an interposer (fig. 6B, dummy dielectric layer 132; para. 0035) in between the second set of nanostructures (104) where the first set of nanostructures (106) have been removed, wherein forming the interposer (132) comprises
depositing an interposer material (dielectric material layer of 132; para. 0034) between the second nanostructures (104); and
after solid the interposer material (132 is solid), etching (fig. 14B, etching 132; para. 0038) the interposer material (dielectric material layer of 132) to remove portions of the interposer material (132 along sidewalls) along sidewalls of the multi-layer stack (stack of 104 and 132, which replace 106), wherien after the etching the interposer material (dielectric material layer of 132) the interposer material (132) has a non-linear surface profile (curved sidewall surfaces; para. 0066).
replacing the interposer (fig. 13B, 132) with a gate electrode (gate electrode layer 156; para. 0059).
Lin fails to explicitly teach after completely depositing the interposer material, performing an ultraviolet curing process on the interposer material, wherein the ultraviolet curing process introduces oxygen or nitrogen into the interposer material, after the performing the ultraviolet curing process, the interposer material solid.
However, Lee teaches after completely depositing the interposer material (Lee: flowable isolation dielectric precursor by FCVD; para. 0085, similar to the material of 132 of Lin), performing an ultraviolet curing process (Lee: UV curing; para. 0085) on the interposer material (Lee: flowable isolation dielectric precursor), wherein the ultraviolet curing process (Lee: UV curing) introduces oxygen or nitrogen (Lee: nitrogen, oxygen; para. 0085) into the interposer material (Lee: flowable isolation dielectric precursor), after the performing the ultraviolet curing process (Lee: UV curing), the interposer material solid (Lee: flowable isolation dielectric precursor solid after curing).
Lee and Lin are considered to be analogous to the claimed invention because they are in the same field of insulating material in transistor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed method to add performing an ultraviolet curing process increases an oxygen concentration or a nitrogen concentration of the interposer material as taught by Lee.
Doing so would realize a curing process to increase the structural density of the insulating layer (Lee: para. 0086).
Regarding claim 9, Lin in view of and Lee further teaches the method of claim 8, wherein the first semiconductor material (Lin: fig. 1B, 106) is formed of silicon germanium (Lin: silicon germanium; para. 0018) and the second semiconductor material (Lin: 104) is formed of silicon (Lin: Si; para. 0018).
Regarding claim 10, Lin in view of and Lee further teaches the method of claim 9, wherein the first set of nanostructures (Lin: fig. 4B, 106) are removed utilizing a dry etching process (Lin: dry etching process; para. 0032).
Regarding claim 11, Lin in view of and Ju further teaches the method of claim 8, further comprising forming spacers (Lin: fig. 9B, inner spacer layer 136; para. 0037) adjacent to the interposer (Lin: 132) and in between the second set of nanostructures (Lin: 104) where the first set of nanostructures (Lin: 106) have been removed.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Lee as applied to claim 8 above, and further in view of UN (UNANNOUNCED INVENTOR) et al. (CN 111192850).
Regarding claim 12, Lin in view of Lee teaches the method of claim 8 including after the removing of the first set of nanostructures (Lin: fig. 5B, 106 removed), forming the interposer (Lin: fig. 6B, 132).
Lin in view of Lee fails to explicitly teach depositing an oxide film over exposed surfaces of the second set of nanostructures, wherein the oxide film is deposited prior to the forming the interposer.
However, UN teaches depositing an oxide film (UN: trench oxide layer (not shown); para. 0059) over exposed surfaces of the second set of nanostructures (UN: exposed surfaces of semiconductor substrate 100; para. 0060, similar to exposed surfaces of 104 and 101 of Lin), wherein the oxide film (UN: trench oxide layer) is deposited prior to the forming the interposer (UN: before depositing isolation medium 102 by FCVD; para. 0059, similar to the material layer of 132 of Lin).
UN, Lee and Lin are considered to be analogous to the claimed invention because they are in the same field of insulating material in transistor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed method to add the oxide film as taught by UN.
Doing so would clarify the detail process of FCVD and realize an oxide layer to improve the filling effect of depositing (UN: para. 0059).
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Lee and UN as applied to claim 12 above, and further in view of Xie.
Regarding claim 13, Lin in view of Lee and UN teaches the method of claim 12, wherein after the depositing the oxide film (UN: trench oxide layer) the depositing the interposer material (Lin: material of 132) comprises utilizing a contour-flowable chemical vapor deposition (c-FCVD) process (Lin: 132 is formed by flowable CVD and contour the shape of 132 between 104; para. 0035).
Lin in view of Lee and UN fails to explicitly teach deposit the interposer material over exposed surfaces of the substrate and surrounding each of the second set of nanostructures, wherein the interposer material is seam-free in between each of the second set of nanostructures.
However, Xie teaches deposit the interposer material (Xie: fig. 1D, insulating material 116; para. 0024, similar to the material of 132 of Lin) over exposed surfaces of the substrate (Xie: semiconductor substrate 103, buried insulation layer 104; para. 0017, similar to 101 of Lin) and surrounding each of the second set of nanostructures (Xie: semiconductor material 108; para. 0024, similar to 104 of Lin), wherein the interposer material (Xie: 116) is seam-free (Xie: 116 fills the spaces between 108; para. 0024) in between each of the second set of nanostructures (Xie: 108).
Xie, UN, Lee and Lin are considered to be analogous to the claimed invention because they are in the same field of insulating material in transistor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed method to add the interposer material as taught by Xie.
Doing so would clarify the detail process of FCVD and realize an interposer material ensure complete coating/fill between semiconductor layers (Xie: para. 0024).
Regarding claim 14, Lin in view of Lee, UN and Xie teaches the method of claim 13, wherein the forming the interposer (Lin: 132) further comprises etching the interposer material (Xie: fig. 1E, etching 116) to remove portions of the interposer material (Xie: 116) over the substrate (Xie: 103, 104) not directly underneath the second set of nanostructures (Xie: 108), on sidewalls of the second set of nanostructures (Xie: 108) and in between each of the second set of nanostructures (Lin: fig. 7B, 104), wherein the etching is a cyclic dry etching process (Xie: anisotropic etching; para. 0025 and UN: dry etching; para. 0060 need at least one dry etch cycle).
Allowable Subject Matter
Claims 1-7 and 15-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
The prior art fails to teach or clearly suggest the limitations stating:
"after the removing the first nanostructures forming an interposer in between the second nanostructures, wherein forming the interposer comprises:
depositing an insulating material between the second nanostructures, wherein after the depositing the insulating material the insulating material has a curved outer surface adjacent to the second nanostructures; and
after completely depositing the insulating material, introducing oxygen or nitrogen through the curved outer surface and into the insulating material while performing a densification process " as cited in claim 1.
Claims 2-7 are allowable for being dependent on claim 1.
Lin et al. (US 20210313449) teaches after the removing the first nanostructures (fig. 4B-5B, 106) forming an interposer (132) in between the second nanostructures (104), wherein forming the interposer (132) comprises: depositing an insulating material (material of 132) between the second nanostructures (104). However, Lin does not teach wherein after the depositing the insulating material the insulating material has a curved outer surface adjacent to the second nanostructures; and after completely depositing the insulating material, introducing oxygen or nitrogen through the curved outer surface and into the insulating material while performing a densification process.
"performing a first etching process to remove the first nanostructures, wherein the first etching process partially etches the second nanostructures such that edge regions of the second nanostructures are less wide than center regions of the second nanostructures;
forming an interposer in between the second nanostructures, wherein edge regions of the interposer are wider than a center region of the interposer, wherein forming the interposer comprises:
depositing a first dielectric layer, wherein after the depositing the first dielectric layer edge regions of the first dielectric layer are wider than the edge regions of the second nanostructures;
after depositing the first dielectric layer, performing a first oxidation process to oxidize at least a first portion of the first dielectric layer; after performing the first oxidation process, performing a second oxidation process, the second oxidation process further oxidizes at least a second portion of the first dielectric layer; and
after performing the second oxidation process, reducing the edge regions of the first dielectric layer to at least the edge regions of the interposer " as cited in claim 15.
Claims 16-20 are allowable for being dependent on claim 15.
Lin et al. (US 20210313449) teaches performing a first etching process to remove the first nanostructures (fig. 4B-5B, 106); forming an interposer (132) in between the second nanostructures (104), wherein edge regions of the interposer (fig. 14B, edge regions of 132) are wider than a center region of the interposer (center region of 132), wherein forming the interposer comprises: depositing a first dielectric layer (132), reducing the edge regions of the first dielectric layer (fig. 14B, 132) to at least the edge regions of the interposer (132). However, Lin does not teach wherein the first etching process partially etches the second nanostructures such that edge regions of the second nanostructures are less wide than center regions of the second nanostructures, wherein after the depositing the first dielectric layer edge regions of the first dielectric layer are wider than the edge regions of the second nanostructures; after depositing the first dielectric layer, performing a first oxidation process to oxidize at least a first portion of the first dielectric layer; after performing the first oxidation process, performing a second oxidation process, the second oxidation process further oxidizes at least a second portion of the first dielectric layer; and after performing the second oxidation process, reducing the edge regions of the first dielectric layer to at least the edge regions of the interposer.
Response to Arguments
Applicant's arguments filed on Jun. 26th 2026 have been fully considered but they are not persuasive.
With respect to pages 1 of applicant’s response of claim 1 is rejected under 35 U.S.C.103.
Applicant submits "the cited references, either individually or in combination, fail to teach or suggest the features cited in claim 8".
The examiner respectfully disagrees.
As shown in fig. 14B of Lin, Lin teaches etching the interposer material (132) to remove portions of the interposer material (side portion of 132) along sidewalls of the multi-layer stack (104/132), wherien after the etching the interposer material (132) the interposer material (132) has a non-linear surface profile (curved surface). In addition, Lee teaches the ultraviolet curing process (UV curing) to solid the interposer material. As result, given a broadest reasonable interpretation, Lin in view of and Lee teaches all limitations of claims 8. Details of rejections are discussed above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHIJUN XU whose telephone number is (571)270-3447. The examiner can normally be reached Monday-Thursday 9am-5pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ZHIJUN XU/Examiner, Art Unit 2818
/BRIAN TURNER/Primary Examiner, Art Unit 2818
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