DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
2. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
3. Claim(s) 15, 16, 19-24, 27-29, is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al., US 2018/0138101 A1, in view of Chiu et al., US 2019/0295913 A1.
Claims 15, 23. Yu et al., disclose a method comprising:
-forming a gap-fill dielectric (item 100) around a first integrated circuit die (68/88), the first integrated circuit die comprising a semiconductor substrate (item 60) and a through-substrate via (item 74);
-planarizing the gap-fill dielectric until the gap-fill dielectric, the semiconductor substrate, and the through-substrate via have top surfaces that are substantially coplanar (this limitation would read through the steps in fig. 10);
-depositing a first dielectric layer (item 117, fig. 11) on the top surfaces of the gap-fill dielectric, the semiconductor substrate, and the through-substrate via (this limitation would read through the steps in fig. 11);
-forming a bond pad (item 118, fig. 11)) in the first dielectric layer, the bond pad extending through the first dielectric layer to contact the top surface of the through-substrate via,
-and bonding a second integrated circuit die to the bond pad and the first dielectric layer (this limitation would read through [0033] wherein is disclosed the bonding between the dies 68 and 88 and the components 96 may be a solder bonding or a direct metal-to-metal (such as a copper-to-copper or tin-to-tin) bonding).
Yu et al., appear to not specify the limitation of “a width of the bond pad being less than a width of the through-substrate via”.
However, in a similar package structure, fig. 1L of Chiu et al., a bond pad (item 500b) being less than a width of the through-substrate via (item 200).
It would have been obvious to one having ordinary skill in the art at the time the invention was made to have a width of the bond pad being less than a width of the through-substrate via, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Allen, 105 USPQ233. In addition, it is noted that a bond pad is intentionally made smaller than the via to improve mechanical reliability by preventing pad cracking, as the larger via provides a larger anchor point for the bond pad and helps resist stresses from thermal expansion. Additionally, using a smaller pad can reduce parasitic capacitance between pads, leading to better electrical performance, especially in high-density and high-speed applications.
Claim 16. Yu et al., disclose the method of claim 15, wherein the second integrated circuit die comprises a second dielectric layer and a die connector, and bonding the second integrated circuit die to the bond pad and the first dielectric layer comprises: pressing the second dielectric layer against the first dielectric layer (this limitation would read through [0033] wherein is disclosed the bonding between the dies 68 and 88 and the components 96 may be a solder bonding or a direct metal-to-metal (such as a copper-to-copper or tin-to-tin) bonding);
-annealing the second dielectric layer and the first dielectric layer to form covalent bonds between a material of the second dielectric layer and a material of the first dielectric layer (this limitation would read through [0043] wherein is disclosed the curing step is performed to cure the encapsulant 112, wherein the curing may be a thermal curing, a Ultra-Violet (UV) curing, or the like); and annealing the die connector and the bond pad to intermingle a material of the die connector and a material of the bond pad (this limitation would read through [0043] wherein is disclosed the curing step is performed to cure the encapsulant 112, wherein the curing may be a thermal curing, a Ultra-Violet (UV) curing, or the like).
Claim 19. Yu et al., disclose the method of claim 15, wherein forming the gap-fill dielectric comprises forming a nitride-oxide-nitride-oxide structure around the first integrated circuit die (this limitation would read through [0046] wherein is disclosed the dielectric layers 117 may comprise silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, low-K dielectric material, such as PSG, BPSG, FSG, SiO.sub.xC.sub.y, Spin-On-Glass, Spin-On-Polymers, silicon carbon material, compounds thereof, composites thereof, combinations thereof, or the like).
Claim 20. Yu et al., disclose the method of claim 15, wherein forming the gap-fill dielectric comprises forming an epoxy material around the first integrated circuit die (this limitation would read through [0036] wherein is disclosed the underfill material 100 may be any acceptable material, such as a polymer, epoxy, molding underfill, or the like).
Claims 21, 22. Yu et al., disclose the method of claim 15, wherein the bond pad is one of a plurality of bond pads formed in the first dielectric layer, each of the bond pads extending through the first dielectric layer to contact the top surface of the through-substrate via (this limitation would read through the structure 11, items 117, 118).
Claim 24. Yu et al., disclose the method of claim 23, further comprising: forming a second gap-fill dielectric around the second integrated circuit die (this limitation would read through [0036] wherein is disclosed the underfill material 100 may extend up along sidewall of the dies 68 and the dies 88); and attaching a support substrate to the second gap-fill dielectric and to the second integrated circuit die (this limitation would read through [0036] wherein is disclosed the underfill material 100 may be formed by a capillary flow process after the dies 68 and 88 are attached, or may be formed by a suitable deposition method before the dies 68 and 88 are attached).
Claim 27. Yu et al., disclose the method of claim 23, wherein exposing the through-substrate via comprises thinning the first gap-fill dielectric and a semiconductor substrate of the first integrated circuit die (this limitation would read through [0043] wherein is disclosed a planarization step, such as a grinding, may be performed to remove excess portions of the encapsulant 112).
Claim 28. Yu et al., disclose the method of claim 23, wherein bonding the second integrated circuit die comprises bonding the second integrated circuit die with a combination of dielectric-to- dielectric bonds and metal-to-metal bonds (this limitation would read through [0033] wherein is disclosed the bonding between the dies 68 and 88 and the components 96 may be a solder bonding or a direct metal-to-metal (such as a copper-to-copper or tin-to-tin) bonding).
Claim 29. Yu et al., disclose the method of claim 23, wherein forming the first gap-fill dielectric comprises: forming a first nitride liner; forming a first oxide liner over the first nitride liner; forming a second nitride liner over the first oxide liner; and forming an oxide filler over the second nitride liner (this limitation would read through [0046] wherein is disclosed the dielectric layers 117 may comprise silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, low-K dielectric material, such as PSG, BPSG, FSG, SiO.sub.xC.sub.y, Spin-On-Glass, Spin-On-Polymers, silicon carbon material, compounds thereof, composites thereof, combinations thereof, or the like).
Allowable Subject Matter
4. Claims 17-18, 25-26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
(A) Claims 17, 25 contain allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of wherein the width of the bond pad is greater than half the width of the through-substrate via.
(B) Claims 18, 26 contain allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of wherein the width of the bond pad is less than half the width of the through-substrate via.
Allowable Subject Matter
5. Claims 30-34 are allowed.
Reasons for Allowance
6. The following is an examiner's statement of reasons for allowance:
7. Regarding claims 30-34, the prior art failed to disclose or reasonably suggest after recessing the second nitride liner, depositing an oxide filler on the second nitride liner; and planarizing the oxide filler, the oxide liner, and the first nitride liner such that a top surface of the oxide filler is coplanar with a top surface of the oxide liner, a top surface of the first nitride liner, and the top surface of the semiconductor substrate; depositing a dielectric layer on the top surface of the oxide filler, the top surface of the oxide liner, and the top surface of the first nitride liner; forming a bond pad in the dielectric layer, the bond pad extending through the dielectric layer to contact the through-substrate via; and bonding an upper integrated circuit die to the bond pad and to the dielectric layer.
Response to Arguments
8. Applicant's arguments filed 02/16/2026, have been fully considered but they are not persuasive.
9. Regarding claim 15, Applicant respectfully submits that Yu’s reference fails to teach or suggest "forming a gap-fill dielectric around a first integrated circuit die, the first integrated circuit die comprising a semiconductor substrate and a through-substrate via" and "bonding a second integrated circuit die".
In response to applicant’s argument, it is noted that [0036] of Yu discloses an underfill material 100 is dispensed into the gaps between the dies 68, the dies 88, the redistribution structure 76, and surrounding the conductive joints 91. Further, [0036] of Yu discloses that the underfill material 100 may be any acceptable material, such as a polymer, epoxy, molding underfill, or the like. Furthermore, [0046] of Yu discloses a redistribution structure is formed on the second surface 116 of the substrate 70, and is used to electrically connect the TVs 74 together and/or to external devices.
10. Regarding claim 23, Applicant respectfully submits that Yu’s reference fails to teach or suggest “after bonding the second integrated circuit die, forming an interconnect structure on the first gap-fill dielectric and on a front-side of the first integrated circuit die”. In response to applicant’s argument, it is noted that [0033] of Yu discloses the electrical connectors 77/78/79 are in contact with the die connectors 66 and 86, respectively, and the pads of the redistribution structure 76 to physically and electrically couple the dies 68 and the dies 88 to the components 96. After the bonding process, an IMC (not shown) may form at the interface of the metal pillars 77 and 79 and the metal cap layers 78.
11. With respect to claims 19 and 29, Applicant respectfully submits that Yu’s reference fails to teach or suggest “wherein forming the gap-fill dielectric comprises forming a nitride-oxide-nitride-oxide structure around the first integrated circuit die." In response to applicant’s argument, it is noted that [0021] of Yu discloses the dielectric layers may comprise silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, low-K dielectric material.
In conclusion, Examiner believe that the combination of Yu with Chiu et al., meets the limitations of the rejected claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILNER JEAN BAPTISTE whose telephone number is (571)270-7394. The examiner can normally be reached M-T 8:00-6:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/W.J/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights