Office Action Predictor
Last updated: April 16, 2026
Application No. 18/152,477

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING

Final Rejection §103
Filed
Jan 10, 2023
Examiner
GHYKA, ALEXANDER G
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Co., LTD.
OA Round
2 (Final)
84%
Grant Probability
Favorable
3-4
OA Rounds
2y 3m
To Grant
97%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allow Rate
1067 granted / 1278 resolved
+15.5% vs TC avg
Moderate +14% lift
Without
With
+13.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
34 currently pending
Career history
1312
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
55.5%
+15.5% vs TC avg
§102
15.8%
-24.2% vs TC avg
§112
12.2%
-27.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1278 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Applicants’ response of 12/04/2025 has been considered and entered in the record. The rejections of the previous Office action are withdrawn in view Applicants’ amendments and arguments. The following new rejection is made. Applicants’ arguments are addressed below. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al (US 2016/0322462) in view of Lin et al (US 2013/0207122). With respect to Claim 1, Chou et al discloses a method of forming a semiconductor device (Figures 5A-8B) comprising: forming a fin (Figure 5A, 312) over a semiconductor substrate (Figure 5A, 302); forming a precursor film (Figure 5A, 314) over the fin (Figure 5A, 312) and the semiconductor substrate(Figure 5A, 302); treating (Figure 7C-7D, plasma 702, 712) the precursor film, wherein the treating the precursor film forms a first dielectric material (Figures 7C -7D, 314 outside of H area) from a first portion of the precursor film and forms a second dielectric material (Figures 7C -7D, 314 inside of H area) from a second portion of the precursor film, wherein the first dielectric material has a first density and the second dielectric material has a second density, the first density being different from the second density (inherent as dopant concentrations vary) ; and removing the second dielectric material (Figure 8A) wherein after the removing the second dielectric material an isolation structure (Figure 8B, 316a and 316b) is formed comprising the first dielectric material over the semiconductor substrate and adjacent to the fin. See Figures 5A – 8B and paragraphs 42-61. However, Chou et al do not disclose that the precursor film is treated “with an anisotropic plasma process”. Lin et al is relied upon to disclose to disclose the use of anisotropic plasma processes to change the etch selectivity of a material in the formation of fin structures. See Figures 2-6 and corresponding text, especially paragraphs 10 and 19-23. It would have been obvious to one of ordinary skill in the art, before the effective date of the invention, to use anisotropic plasma process in the process of Chou et al, for its known benefit of changing the etch selectivity of materials as disclosed by Lin et al. The use of a known process for its known benefit would have been prima facie obvious to one of ordinary skill in the art. With respect to Claim 2, Chou et al discloses wherein the removing the second dielectric material the isolation structure has a convex profile. See Figure 8A and corresponding text. With respect to Claim 3, Chou et al does not explicitly disclose “wherein the convex profile has a first profile angle, the first profile angle being in a range of 35 degrees to 50 degrees. It would have been obvious to one of ordinary skill in the art, before the effective date of the invention, to arrive at the claimed angles, as changes in shape are prima facie obvious in the absence of unobvious results. See In re Dailey, 149 USPQ 47 (CCPA 1966). Response to Applicants’ Arguments Applicants argue that the claimed limitations are not disclosed by the Chou et al reference. The Examiner notes that the rejection as discussed above addresses all of the claimed limitations. Applicants argue that the withdrawal of Claims 21-27 is improper as the mechanism is only available after an action on the merits. The Examiner notes that Applicants have received an Office action on the merits and have constructively elected Claims drawn to deposition of a precursor (silicon) and its treatment with plasma. The elected Claims are mutually exclusive from Claims drawn to the deposition of two dielectric layers. Rejoinder issues will be addressed upon indication of allowability of the Claims. Allowable Subject Matter Claims 4-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 15-20 are allowed. The following is an examiner’s statement of reasons for allowance: The closest prior art known to the Examiner is listed on the PTO 892 and IDS forms of record. With respect to Claims 15-20 the cited prior art does not anticipate or make obvious inter alia “depositing a layer of silicon over the first semiconductor fin and over the substrate adjacent to the first semiconductor fin; applying an anisotropic plasma to the layer of silicon with an element, wherein the applying the anisotropic plasma forms a first dielectric material from horizontal portions of the layer of silicon and forms a second dielectric material from vertical portions of the layer of silicon, the first dielectric material having a first concentration of the element and the second dielectric material having a second concentration of the element”. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER G GHYKA whose telephone number is (571)272-1669. The examiner can normally be reached Monday-Friday 9-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at 571 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. AGG February 10, 2026 /ALEXANDER G GHYKA/Primary Examiner, Art Unit 2812
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Prosecution Timeline

Jan 10, 2023
Application Filed
Sep 02, 2025
Non-Final Rejection — §103
Dec 04, 2025
Response Filed
Feb 10, 2026
Final Rejection — §103
Feb 25, 2026
Examiner Interview Summary
Feb 25, 2026
Applicant Interview (Telephonic)

Precedent Cases

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Patent 12593661
SEMICONDUCTOR STRUCTURE WITH OVERLAY MARK, METHOD OF MANUFACTURING THE SAME, AND SYSTEM FOR MANUFACTURING THE SAME
2y 5m to grant Granted Mar 31, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
84%
Grant Probability
97%
With Interview (+13.8%)
2y 3m
Median Time to Grant
Moderate
PTA Risk
Based on 1278 resolved cases by this examiner. Grant probability derived from career allow rate.

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