Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 9-15 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
There is no support in the original specification for the claim limitations of “the second semiconductor device…being laterally spaced spart from the second redistribution structure and the third redistribution structure”, as recited in claim 9.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 8-12, 14-15 and 21-24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (US 2021/0028147, as disclosed in previous office action).
As for claim 1, Yu et al. disclose in Figs. 1-12 (as view upside down) and the related text a package comprising:
a first redistribution structure 104;
a first semiconductor device (upper left 110) attached to a first side of the first redistribution structure 104;
a second semiconductor device attached to the first side of the first redistribution structure 104 (fig. 1), wherein the second semiconductor device comprises:
a second redistribution structure (redistribution layer above upper 110, [0015]);
a first device die (upper right 110) disposed over the second redistribution structure and comprising an active surface facing the second redistribution structure (fig. 9);
a first encapsulant (molding material [0015]) extending along sidewalls of the first device die (fig. 9);
a first through via (through vias that form in molding material) extending through the first encapsulant (fig. 9);
a third redistribution structure (redistribution layer below upper 110, [0015]) disposed over the first encapsulant (fig. 9), the third redistribution structure comprising a first metallization pattern electrically coupled connecting to the first through via (fig. 9);
a second device die (lower 110) disposed over the third redistribution structure (fig. 9), wherein the first device die and the second device die are free of through substrate vias (fig. 9); and
a second encapsulant (molding material) extending along sidewalls of the second device die (fig. 9, [0015]); and
a third encapsulant 106 disposed over the first redistribution structure and surrounding sidewalls of the first semiconductor device and the second semiconductor device (fig. 9), wherein a top (lower) surface of the third encapsulant is level with a top (lower) surface of the second encapsulant (fig. 9), wherein a topmost (lower) surface of the first redistribution structure 104 is below or coplanar with a bottommost surface of the third encapsulant 106.
As for claim 2, Yu et al. disclose the package of claim 1, wherein a top surface of the second device die (lower 110) is lower than a top surface of the second encapsulant (fig. 9).
As for claim 8, Yu et al. disclose the package of claim 1, wherein each of the first device die (upper right) and the second device die (lower 110) has an active surface facing the first redistribution structure (Fig. 9).
As for claim 9, Yu et al. disclose in Figs. 1-12 (as view upside down) and the related text a package comprising:
a first semiconductor device (upper 110) disposed over a first (lower) side of a first redistribution structure 104, wherein the first semiconductor device comprises:
a first fan-out tier comprising: a second redistribution structure (lower redistribution above upper 110 [0015]);
a first device die (upper 110) disposed over the second redistribution structure and comprising an active surface facing the second redistribution structure (fig. 9);
a first encapsulant (molding material, [0015]) extending along sidewalls of the first device die; and
a first through via (via in molding material) extending through the first encapsulant and connecting to the first encapsulant (fig. 9);
a second fan-out tier disposed over the first fan-out tier, wherein the second fan-out tier comprises:
a third redistribution structure (redistribution layer below upper 110) disposed over the first encapsulant and the first through via (fig. 9);
a second device die (lower left 110) disposed over the third redistribution structure; and
a second encapsulant (molding material [0015]) extending along sidewalls of the second device die (fig. 9);
a second semiconductor device (lower right 110) disposed over the first side of the first redistribution structure 104 (fig. 1), the second semiconductor device (lower right 110) being (electrically) bonded to the first metal of the first redistribution structure 104, and being laterally spaced spart from the second redistribution structure and the third redistribution structure (Fig. 9); and
a third encapsulant 106 surrounding sidewalls of the first semiconductor device and the second semiconductor device (fig. 9), wherein a top surface of the third encapsulant is level with a top surface of the second encapsulant (fig. 9), and a top (lower) surface of the second device die is lower than the top (lower) surface of the third encapsulant (fig. 9).
As for claim 10, Yu et al. disclose the package of claim 9, wherein the third redistribution structure is in physical contact with a top surface of the first encapsulant and a top surface of the first through via (fig. 9).
As for claim 11, Yu et al. disclose the package of claim 9, further comprising an adhesive layer (a layer form above lower 110) disposed between a top surface of the first device die and the third redistribution structure (fig. 9).
As for claim 12, Yu et al. disclose the package of claim 9, wherein the first device die encapsulant is free of through vias (fig. 9).
As for claim 14, Yu et al. disclose the package of claim 9, further comprising a third fan-out tier disposed between the first fan-out tier and the second fan-out tier, wherein the third fan-out tier comprises: a fourth redistribution structure disposed over the first encapsulant and the first though via; a third device die disposed over the fourth redistribution structure; a fourth encapsulant extending along sidewalls of the third device die; and a third through via extending through the fourth encapsulant, wherein a top surface of the third device die is lower than a top surface of the third through via ([0015] of Yu et al. teach a device comprise more than four dies 110, therefore it is inherent to have a third fan-out tier having structure as claimed).
As for claim 15, Yu et al. disclose the package of claim 9, further comprising a dissipating structure 122 laterally surrounding the first semiconductor device, the second semiconductor device, and the third encapsulant (fig. 9).
As for claim 21, Yu et al. disclose in Figs. 1-12 (as view upside down) and the related text a package comprising:
a first redistribution structure 104;
a first semiconductor device (upper left 110) bonded to a first metal layer (conductive layer of 104, [0027]) of the first redistribution structure 104;
a second semiconductor device bonded to the first metal layer of the first side of the first redistribution structure 104 (fig. 1), wherein the second semiconductor device comprises:
a second redistribution structure (redistribution layer above upper 110, [0015]);
a first device die (upper right 110) disposed over the second redistribution structure and comprising an active surface facing the second redistribution structure (fig. 9);
a first encapsulant (molding material [0015]) extending along sidewalls of the first device die (fig. 9);
a first through via (through vias that form in molding material) extending through the first encapsulant (fig. 9);
a third redistribution structure (redistribution layer below upper 110, [0015]) disposed over the first encapsulant and the first through via (fig. 9);
a second device die (lower 110) disposed over the third redistribution structure (fig. 9), and
a second encapsulant (molding material) extending along sidewalls of the second device die (fig. 9, [0015]); and
a third encapsulant 106 disposed over the first redistribution structure and surrounding sidewalls of the first semiconductor device and the second semiconductor device (fig. 9), wherein (outer portion of) the third encapsulant is free of conductive vias extending therethrough (Fig. 9).
As for claim 23, Yu et al. disclose the package of claim 21, further comprising a third encapsulant over the second device die, the third encapsulant being surrounded by the first encapsulant (fig. 9).
As for claim 24, Yu et al. disclose the package of claim 21, further comprising an adhesive layer (layer surround the pads) between the second device die and the third redistribution structure.
Claim Rejections - 35 USC § 103
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 13 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. in view of Uzoh (US 2024/0038702, as disclosed in previous office action).
As for claims 13 and 25, Yu et al. disclosed the package of claim 9, except the second semiconductor device comprises a die stack, wherein the die stack comprises a third device die and a fourth device die, the third device die and the fourth device die being bonded through a hybrid bond.
Uzoh teaches in Figs. 1A-1B and the related text a second semiconductor device comprises a die stack (left stack), wherein the die stack comprises a third device die and a fourth (first) device die, the third (third) device die and the fourth device die being bonded through a hybrid bond [0023].
Yu et al. and Uzoh are analogous art because they both are directed packaging structures and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yu et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Yu et al. to include the limitations as taught by Uzoh in order to improve density of the device.
Allowable Subject Matter
Claims 3-4 and 6-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: a fourth encapsulant disposed over the second device die and surrounded by the second encapsulant, wherein the third encapsulant and the fourth encapsulant are a same material, as recited in claim 3. Claims 4 and 6-7 depend among objected claim 3.
Response to Arguments
Applicant's response filed on 11/05/2025 is acknowledged and is answered as follows.
Applicant’s arguments, see pg. 1-2, with respect to the rejections of claim 1 that Yu et al. do not disclose “a first semiconductor device attached to a first side of the first redistribution structure; a second semiconductor device attached to the first side of the first redistribution structure” have been fully considered but they are not persuasive in view of the following reasons: Fig. 1 of Yu et al. clearly disclose a first semiconductor device (upper left 110) attached to a first (lower) side of the first redistribution structure 104; and a second semiconductor device (upper right 110) attached to the first side of the first redistribution structure 104.
Applicant’s arguments, see pg. 3-4, with respect to the rejections of claims 9 and 21 that Yu et al. do not disclose “a first semiconductor device disposed over a first side of a first redistribution structure; a second semiconductor device being boned to the first metal of the first redistribution structure” have been fully considered but they are not persuasive in view of the following reasons: Fig. 1 of Yu et al. clearly disclose a first semiconductor device (upper 110) disposed over a first (lower) side of a first redistribution structure 104; and a second semiconductor device (lower right 110) disposed over the first side of the first redistribution structure 104.
Applicant’s arguments, see pg. 5, with respect to the rejections of claim 21 that Yu et al. do not disclose “a third encapsulant disposed over the first redistribution structure and surrounding sidewalls of the first semiconductor device and the second semiconductor device, wherein the third encapsulant is free of conductive vias extending therethrough” have been fully considered but they are not persuasive in view of the following reasons: Fig. 1 of Yu et al. clearly disclose a third encapsulant 106 disposed over the first redistribution structure and surrounding sidewalls of the first semiconductor device and the second semiconductor device, wherein (outer portion of) the third encapsulant 106 is free of conductive vias extending therethrough.
For above reasons, Yu et al. still disclosed the claimed invention.
In view of the foregoing reasons, the Examiner believes that all Applicant’s arguments and remarks are addressed. The Examiner has determined that the previous Office Action is still proper based on the above responses. Therefore, the rejections are sustained and maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached on Monday-Thursday (9am-4pm).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 5712721670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TRANG Q TRAN/Primary Examiner, Art Unit 2811