DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102/§ 103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claim(s) 1 and 4-7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by YEONG et al. (US 2020/0381289), (hereinafter, YEONG) or on the alternative Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over YEONG et al. (US 2020/0381289), (hereinafter, YEONG).
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RE Claim 1, YEONG discloses a semiconductor and a method of making the same. YEONG discloses in FIGS. 2A-2H and 3 a method, comprising:
forming a first fin 102A and a second fin 102B over a semiconductor substrate 100;
forming an isolation region 130 between the first fin 102A and the second fin 102B, forming the isolation region 130 comprising:
depositing an oxide liner 130 “silicon oxynitride” along the first fin 120A, the second fin 102B, and the semiconductor substrate 100, the oxide liner comprising a first upper portion and a first lower portion along the first fin, the first lower portion being between the first upper portion and the semiconductor substrate, referring to FIGS. 2B/3B. examiner notes that the silicon oxynitride comprises silicon oxide. Since the claim preamble of the process is open ended by the language use of comprising and silicon oxynitride layer 130 comprises silicon oxide, it meets the claimed limitation of depositing an oxide liner. However, if applicant proof otherwise, it would have been obvious for one of ordinary skill in the art, at the effective filing date of the instant application, absent unexpected results, to use the pure oxide layer, such as metal oxide as liner in the isolation region as a well-known oxide material in order to achieve adequate etch selectivity with other oxide or nitride layers in the device;
wherein after depositing the oxide liner 130, the oxide liner is continuous from a first topmost surface of the first fin to a second topmost surface of the second fin, referring to FIG. 2B;
thinning the oxide liner 130, referring to FIGS. 2C/3C. examiner notes that etching back the silicon oxynitride liner 130 to form the liner 132, referring to FIG. 2C/3C represent a thinning process, hence reading on the claimed limitation of thinning process;
wherein after thinning the oxide liner 130, the oxide liner 132 remains continuous from a first topmost surface of the first fin 410 to a second topmost surface of the second fin 410. Examiner notes that the first and second fins are recessed in an etching step of the oxide liner 130, such that oxide liner 132 is continuous from a first topmost surface of the first fin 410 to a second topmost surface of the second fin 410, hence meeting the claimed limitation due to the fact that the upper portions of the first and second fins are recessed wherein the top-most surfaces of the first and second fins are at the same level points of the top-most portions of the oxide liner surface, hence meeting the claimed limitation of remains continuous from the first topmost surface of the first fin to the second topmost surface of the second fin;
depositing an insulation material 152 over the oxide liner 130/132, referring to FIG. 2F; and
recessing “thinning” the insulation material 152, referring to FIG. 2H [0079]; and
forming a gate structure 196 over the first fin 102A, the second fin 102B, and the isolation region 130/132, referring to FIG. 2H.
RE Claim 4, YEONG discloses a method, wherein before thinning the oxide liner 130, the first upper portion of the oxide liner 130 overhangs the first lower portion of the oxide liner 130 by a first distance T6, referring to FIG. 2B, wherein after thinning the oxide liner 130, the first upper portion of the oxide liner overhangs the first lower portion of the oxide liner by a second distance T12, and wherein the first distance is greater than the second distance, referring to FIGS. 2B-2C [0043-0044].
RE Claim 5, YEONG discloses a method, wherein thinning the oxide liner comprises 130 thinning the first upper portion, with a thickness T6 by a greater amount than thinning the first lower portion T13, referring to FIGS. 2B-2C. As annotated above in FIGS. 2B-2C, the thickness removed from the upper portion of liner 130 is more than that removed at the lower bottom portion T”13 as annotated above, hence meeting the claimed limitation [0043-0045 and 0052].
RE Claim 6, YEONG discloses a method, wherein the oxide liner further comprises a second upper portion and a second lower portion along the second fin 102B, wherein thinning the oxide liner 130 comprises increasing a first lateral distance D1 between the first upper portion and the second upper portion of the oxide liner 130, referring to FIG. 2C.
RE Claim 7, YEONG discloses a method, wherein thinning the oxide liner 130 comprises increasing a second lateral distance D2 between the first lower portion and the second lower portion of the oxide liner 130, referring to FIG. 2B, and wherein increasing the first lateral distance D1 is by a greater amount than increasing the second lateral distance D2. It is the examiner position that the limitation is met since the more material of the spacer 130 is removed form the upper potion that the lower portion, which is an indication of increasing the first lateral distance D1 is by a greater amount than increasing the second lateral distance D2.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claim(s) 2 and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable YEONG et al. (US 2020/0381289), (hereinafter, YEONG).
RE Claims 2 and 3, YEONG discloses a method, wherein thinning the oxide liner comprises performing a post-deposition anisotropic dry etching process on the oxide liner 130 [0050].
YEONG does not disclose explicitly a plasma dry etch.
However, Examiner take an Official Notice that plasma etch is a well-know method of oxide dry etching.
Therefore, it would have been obvious for one of ordinary skill in the art, at the effective filing date of the instant application, to use plasma etching for thinning the oxide liner 130 order to control the etch selectivity and hence the oxide liner 130 etched profile.
Response to Arguments
Applicant's arguments filed 03/20/2026 have been fully considered but they are not persuasive. Since the upper portions of the first and second fins are recessed wherein the top-most surfaces of the first and second fins are at the same level points of the top-most portions of the oxide liner surface, the claimed limitation of “remains continuous from the first topmost surface of the first fin to the second topmost surface of the second fin” is met. Therefore, the rejection is maintained.
Allowable Subject Matter
Claims 8-15 and 21-25 are allowable
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including depositing an oxide layer over the first semiconductor fin to form a first combined fin comprising a first portion of the oxide layer and the first semiconductor fin, in a cross-section the first combined fin having an upper region and a middle region, the upper region being at a top of the first combined fin, the middle region being midway between the upper region and the substrate, a first upper width of the upper region being greater than a first middle width of the middle region; and recessing the insulation material and the oxide layer to be below a top surface of the first semiconductor fin, as disclosed in Claim 8; or depositing an oxide layer over the first semiconductor fin to form a first combined fin comprising a first portion of the oxide layer and the first semiconductor fin, in a cross-section the first combined fin having an upper region and a middle region, the upper region being at a top of the first combined fin, the middle region being midway between the upper region and the substrate, a first upper width of the upper region being greater than a first middle width of the middle region; performing a plasma process on the oxide layer, wherein after performing the plasma process: a second upper width of the upper region is less than the first upper width; and a second middle width of the middle region is less than the first middle width; depositing an insulation material over the first combined fin; and recessing the insulation material and the oxide layer to be below a top surface of the first semiconductor fin, as disclosed in Claim 21.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. In the instant case, Wang et al. (US 11,527,430) disclose a method for shallow trench isolation structures in a semiconductor device and a semiconductor device including the shallow trench isolation structures are disclosed. In an embodiment, the method may include forming a trench in a substrate; depositing a first dielectric liner in the trench; depositing a first shallow trench isolation (STI) material over the first dielectric liner, the first STI material being deposited as a conformal layer; etching the first STI material; depositing a second STI material over the first STI material, the second STI material being deposited as a flowable material; and planarizing the second STI material such that top surfaces of the second STI material are co-planar with top surfaces of the substrate.
MEYER et al. (US 2019/0164809) disclose a semiconductor structure having a fin comprising silicon, and a lower fin portion and an upper fin portion. An insulating structure is directly adjacent sidewalls of the lower fin portion of the fin. A first gate electrode is provided over the upper fin portion and over a first portion of the insulating structure. A second gate electrode is provided over the upper fin portion and over a second portion of the insulating structure. A first dielectric spacer is provided along a sidewall of the first gate electrode. A second dielectric spacer is provided along a sidewall of the second gate electrode, and continuous with the first dielectric spacer over a third portion of the insulating structure between the first gate electrode and the second gate electrode. A third dielectric spacer is provided along a sidewall of the upper fin portion and not on a top surface of the fin, and continuous with the first and second dielectric spacers. The dielectric spacers comprise silicon and nitrogen.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YASSER ABDELAZIEZ whose telephone number is (571)270-5783. The examiner can normally be reached Monday - Friday 9 am - 6 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571)270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YASSER A ABDELAZIEZ, PhD/Primary Examiner, Art Unit 2898
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