DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/10/2026 has been entered.
Response to Amendment
The present amendment, filed on or after 02/10/2026, has been entered. The Applicant has amended claims 1 and 16, canceled claim 22, and added claim 24 as a new claim. Claims 8, 10, and 17 were canceled previously. Accordingly, claims 1-7, 9, 11-16, and 18-21 and 23-24 remain pending in the application.
Priority
Acknowledgment is made of applicant’s claim for the benefit of U.S. Provisional Application No. 63/404,315, filed on 09/07/2022.
Claim Objections
Claims 1-7, 9, and 21 are objected, because the following limitations/phrases should be aligned to the prior limitations/phrases to avoid 112 issues due to indefiniteness:
Regarding claim 1, it is recited on line 11 that “the gate stack further comprises”. There is insufficient antecedent basis for “the gate stack”. For the purpose of examination, “the gate stack” is considered to be “the gate stack structure”.
Claims 2-7, 9, and 21 are also objected, because these claims depend on an objected claim.
Appropriate corrections are required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 16 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Wei (US 2023/0062210 A1) in view of Hsu (US 2022/0037519 A1).
Regarding claim 16, Wei teaches a semiconductor device structure (Fig. 1A, [0021]), comprising:
a substrate (substrate 106, subfin regions 110, and nanoribbons 112, Fig. 1A, [0022] and [0025]) having a base (substrate 106, Fig. 1A), a first fin (subfin regions 110 and nanoribbons 112 of the semiconductor device 102, Fig. 1A, [0025]), and a second fin (subfin regions 110 and nanoribbons 112 of the semiconductor device 104, Fig. 1A, [0025]) over the base (substrate 106, Fig. 1A);
a first metal gate stack (comprising first conductive material 116 and fill metal 120, Fig. 1A, [0028]) wrapped around a first upper portion (nanoribbons 112 of the semiconductor device 102, Fig. 1A) of the first fin (subfin regions 110 and nanoribbons 112 of the semiconductor device 102, Fig. 1A);
a second metal gate stack (comprising second conductive material 118 and fill metal 120, Fig. 1A, [0028]) wrapped around a second upper portion (nanoribbons 112 of the semiconductor device 104, Fig. 1A) of the second fin (subfin regions 110 and nanoribbons 112 of the semiconductor device 104, Fig. 1A);
an isolation structure (dielectric wall 122, Fig. 1A, [0029]) between the first metal gate stack (comprising first conductive material 116 and fill metal 120, Fig. 1A) and the second metal gate stack (comprising second conductive material 118 and fill metal 120, Fig. 1A), wherein a top of the isolation structure (dielectric wall 122, Fig. 1A) is substantially level with a top of the second metal gate stack (comprising second conductive material 118 and fill metal 120, Fig. 1A).
Wei, however, does not teach
a conductive line over the first metal gate stack, the second metal gate stack, and the isolation structure, wherein the conductive line electrically connects the first metal gate stack to the second metal gate stack, and the conductive line extends across opposite sidewalls of the isolation structure, wherein an interface between the conductive line and the isolation structure is substantially level with the top of the second metal gate stack.
Hsu, on the other hand, teaches a semiconductor device (Figs. 4T and 4U, [0070]-[0072]) comprising an PMOS transistor (PMOS transistor 101b, Figs. 4T and 4U, [0072]) and an NMOS transistor (NMOS transistor 101c, Figs. 4T and 4U, [0072]), wherein
a conductive line (conductor layer 150, Fig. 4U, [0072]) over the first metal gate stack (gate 101b, Fig. 4U, [0068]), the second metal gate stack (gate 101c, Fig. 4U, [0068]), and the isolation structure (slit 109b, Fig. 4U, [0070]), wherein the conductive line (conductor layer 150, Fig. 4U) electrically connects the first metal gate stack (gate 101b, Fig. 4U) to the second metal gate stack (gate 101c, Fig. 4U, [0072]: “a conductor layer 150 comprising material such as metal is formed by using metal deposition and pattern-etching to connect the control gates of PMOS transistor 101b and NMOS transistor 101c”), and the conductive line (conductor layer 150, Fig. 4U) extends across opposite sidewalls of the isolation structure (left and right walls of the slit 109b in Fig. 4U).
Hsu further discloses that “many logic gates such as invertors, NAND gates, and NOR gates have ‘common gate’ structure, in which the gates for PMOS and NMOS transistors are connected together” ([0071]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the semiconductor device structure of Wei also includes PMOS and NMOS transistors adjacent to each other (Wei, [0026]), and therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention who is aiming to form logic gates in the semiconductor device structure of Wei, would be motivated to include a conductive line connecting the adjacent metal gates, as taught by Hsu, in the semiconductor device of structure of Wei, which would lead to a device structure, wherein
a conductive line over the first metal gate stack, the second metal gate stack, and the isolation structure, wherein the conductive line electrically connects the first metal gate stack to the second metal gate stack, and the conductive line extends across opposite sidewalls of the isolation structure, wherein an interface between the conductive line and the isolation structure is substantially level with the top of the second metal gate stack.
Thus, the combination of Wei and Hsu meets all the limitations of claim 16.
Regarding claim 18, Wei in view of teaches the semiconductor device structure as claimed in claim 16, wherein
Wei further teaches that the first metal gate stack (comprising first conductive material 116 and fill metal 120, Fig. 1A) has a first footing portion (the portion of the first metal gate stack in the dielectric fill 108 between the semiconductor device 102 and semiconductor device 104, Fig. 1A) close to the first fin (subfin regions 110 and nanoribbons 112 of the semiconductor device 102, Fig. 1A: on the right side of the first fin) and protruding toward the second metal gate stack (comprising second conductive material 118 and fill metal 120, Fig. 1A: first foot portion is extending from the first fin to the second metal stack).
Regarding claim 19, Wei in view of Hsu teaches the semiconductor device structure as claimed in claim 18, wherein
Wei further teaches that the second metal gate stack (comprising second conductive material 118 and fill metal 120, Fig. 1A) has a second footing portion (the portion of the second metal gate stack in the dielectric fill 108 between the semiconductor device 102 and semiconductor device 104, Fig. 1A) close to the second fin (subfin regions 110 and nanoribbons 112 of the semiconductor device 104, Fig. 1A: on the left side of the second fin) and protruding toward the first footing portion (the portion of the first metal gate stack in the dielectric fill 108 between the semiconductor device 102 and semiconductor device 104, Fig. 1A) of the first metal gate stack (comprising first conductive material 116 and fill metal 120, Fig. 1A).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Wei (US 2023/0062210 A1) in view of Hsu (US 2022/0037519 A1) as applied to claims 16 and 18-19 above, and further in view of Hsueh (US 2020/0006334 A1).
Regarding claim 20, while Wei in view of Hsu teaches the semiconductor device structure as claimed in claim 16, wherein
Wei and Hsu do not teach that the isolation structure has an upper portion and a lower portion, and the lower portion is narrower than the upper portion.
Hsueh, on the other hand, teaches a semiconductor device (FinFET device, Fig. 14 A, [0007]) with an isolation structure (opening 141, Fig. 14A, [0049]) between fins (fins 64, Fig. 14A, [0053]) wherein the isolation structure (opening 141, Fig. 14A) has an upper portion (top half of the opening 141, Fig. 14A) and a lower portion (bottom half of the opening 141, Fig. 14A), and the lower portion is narrower than the upper portion (the width of upper potion W5 Is larger than the width of the lower portion W6, Fig. 14A, [0053]).
Because the role of the isolation structure in Hsueh and Wei in view of Hsu are analogous (in both cases the isolation structure is used to isolate the devices on adjacent fin structures), it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device structure of Wei in view of Hsu such that the isolation structure decreases in width from the upper portion towards the lower portion as taught by Hsueh, which provides the benefit of providing a larger volume for the conductive materials at the top portions (which reduces resistivity) and reducing the risk of damage to the surrounding semiconductor material in the deep portions as evidenced by Li (US 2022/0013527 A1, [0011]).
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Wei (US 2023/0062210 A1) in view of Hsu (US 2022/0037519 A1) as applied to claims 16 and 18-19 above, and further in view of Chen (US 2021/0193530 A1).
Regarding claim 23, while Wei in view of Hsu teaches the semiconductor device structure as claimed in claim 16,
Wei and Hsu do not teach that the semiconductor device structure further comprises:
a protective layer extending along a bottom and sidewalls of the isolation structure, wherein each of the first metal gate stack and the second metal gate stack comprises a gate dielectric layer, and the gate dielectric layer is spaced apart from the isolation structure by the protective layer.
Chen, on the other hand, teaches a semiconductor device comprising multiple transistors (Fig. 5, [0015]-[0016]) with reduced the parasitic capacitance and fringing capacitance that are caused by the gate cuts between adjacent gates (gate structure 100, Fig. 5, [0018]). Chen discloses that using an isolation structure (fill structure 520, Fig. 5, [0028]) comprising a silicon nitride liner 500 (Fig. 5, [0028]) and an oxide fill 510 (Fig. 5, [0028]) leads to a reduction of parasitic and fringing capacitances in the device ([0016]-[0017]). Accordingly, Chen’s device comprises
a protective layer (silicon nitride liner 500, Fig. 5, [0036]) extending along a bottom and sidewalls of the isolation structure (fill structure 520, Fig. 5).
Chen further discloses that the volume occupied by oxide fill 510 in fill structure 520 is larger than that of silicon nitride liner 500, and therefore, the impact on the fringing capacitance from fill structure 520 is reduced compared to a fill structure having silicon nitride as the only fill material ([0029]). Considering that isolation material in the method of Wei in view of Hsu is silicon nitride (Wei, [0029]), a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to replace the isolation structure in the semiconductor device structure of Wei in view of Hsu with the isolation structure (fill structure 520, Fig. 5) of Chen to obtain the benefit of minimizing the fringing capacitance in the device (Chen, [0029]).
Thus, thus the combination of Wei in view of Hsu, and Chen meets the limitations of claim 23 such that the semiconductor device structure further comprises
a protective layer (silicon nitride liner 500 of Chen after Wei in view of Hsu is modified by Chen, Fig. 5) extending along a bottom and sidewalls of the isolation structure (fill structure 520 of Chen after Wei’s dielectric wall 122 is replaced by fill structure 520 of Chen, Wei’s Fig. 1A and Chen’s Fig. 5) wherein each of the first metal gate stack (first metal gate stack comprising first conductive material 116 and fill metal 120, Wei’s Fig. 1A) and the second metal gate stack (first metal gate stack comprising second conductive material 118 and fill metal 120, Wei’s Fig. 1A) comprises a gate dielectric layer (gate dielectric 114, Wei’s Fig. 1A, [0027]), and the gate dielectric layer (gate dielectric 114, Wei’s Fig. 1A) is spaced apart from the isolation structure (fill structure 520 of Chen after Wei’s dielectric wall 122 is replaced by fill structure 520 of Chen, Wei’s Fig. 1A and Chen’s Fig. 5) by the protective layer (silicon nitride liner 500 of Chen after Wei’s dielectric wall 114 is replaced by fill structure 520 of Chen to include a silicon nitride liner at the sidewalls of the isolation structure, Fig. 5).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Wei (US 2023/0062210 A1) in view of Hsu (US 2022/0037519 A1) as applied to claims 16 and 18-19 above, and further in view of Bi (US 2020/0287039 A1).
Regarding claim 24, while Wei in view teaches the semiconductor device structure as claimed in claim 16,
Wei and Hsu do not teach that the conductive line comprises a barrier layer and a conductive layer, and the barrier layer is between the conductive layer and the first metal gate stack.
Bi, on the other hand teaches a semiconductor device structure (nanosheet-based structure 100, Fig. 11A, [0052]), wherein
conductive line (gate contacts 1214, Fig. 11A, [0052]; gate contacts 1214 are analogous to the conductive line of Wei in view of Hsu) comprises a barrier layer ([0054]: “The gate contacts 1214 … can be tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), which can further include a barrier layer (not shown).”) and a conductive layer (gate contacts 1214 as tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), Fig. 11A, [0054]), and the barrier layer (not shown in figures) is between the conductive layer (gate contacts 1214 as tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), Fig. 11A) and the first metal gate stack (metal gates 802, Fig. 11A, [0054]: “the barrier layer … can be conformally deposited in the trenches 1104, 1102 (shown in FIG. 10A)”, and therefore, the barrier layer is between the metal gates 802 and gate contacts 1214).
Bi further discloses that including the barrier layer prevents diffusion and/or alloying of the metal contact fill material with the material that forms the metal gates ([0054]), which can change the threshold voltage of the transistor devices as evidenced by Lin (US 2015/0054085 A1, [0048]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to include a barrier layer between the conductive layer and the first metal gate stack in the semiconductor structure of Wei in view of Hsu, as taught by Bi, to be able to prevent the diffusion of metal material from the conductive line to the gate metal structures, which will provide the benefit of keeping the threshold voltage of the transistors stable.
Allowable Subject Matter
Claims 1-7, 9, and 21 are objected, where claim 1 is the independent claim.
Independent claim 1, now disclosing the limitation that
“the gate stack further comprises a first semiconductor layer, an etch stop layer, and a second semiconductor layer sequentially stacked over the substrate, and the etch stop layer is partially exposed after the first trench is formed and before the isolation structure is formed.”
would be allowable if the claim objection of claim 1 is overcome.
The closest prior art identified for the invention disclosed in claim 1 is Yang (US 2022/0173097 A1). Yang teaches a method for forming a semiconductor device structure (method for forming the integrated circuit device of Fig. 10, Figs. 11-27, [0018]), comprising:
providing a substrate (substrate 102, first fin active region F1 and second fin active region F2, Fig. 13C, [0102]-[0103]), an isolation layer (isolation film 112, Fig. 13C, [0102]), a gate stack structure (dummy gate structure DGS, Fig. 13C, [0105]), and a dielectric layer (intergate insulating film 144, Fig. 14A, [0113]), wherein the substrate has a base (substrate 102, Fig. 13C), a first fin (second fin active region F2, Fig. 13C), and a second fin (first fin active region F1, Fig. 13C) over the base (substrate 102, Fig. 13C), the isolation layer (isolation film 112, Fig. 13C) is over the base (substrate 102, Fig. 13C) and surrounds the first fin (second fin active region F2, Fig. 13C: isolation layer surrounds the second fin active region F2 from two sides) and the second fin (first fin active region F1, Fig. 13C: isolation layer surrounds the first fin active region F1 from two sides), the gate stack structure (dummy gate structure DGS, Fig. 13C) is wrapped around a first upper portion of the first fin (upper portion of the second fin active region F2, Fig. 13C, [0024]: while not depicted in Fig. 13C, Yang discloses that “… the second fin active region F2 may protrude upwardly through the isolation film 112 in a fin shape on the second device region AR2.”, and therefore, the gate structure wraps around the protruding portion of the fin active region) and a second upper portion of the second fin (upper portion of the first fin active region F1, Fig. 13C, [0024]: “The first fin active region F1 may protrude upwardly through the isolation film 112 in a fin shape on the first device region AR1 …”) and the dielectric layer (intergate insulating film 144, Fig. 14A) is over the isolation layer (isolation film 112, Fig. 13C, [0113]: while it is not shown in the figures, the insulating liner 142 and intergate insulating film 144 covers the regions between the dummy gate structures DGS and between the source/drain regions SD1 and SD2, and therefore intergate insulating film 144 is over the isolation film 112) and wrapped around the gate stack structure (dummy gate structure DGS, Fig. 13C, [0113]: “ … the top surface of the dummy gate layer D114 may be exposed by removing the capping layer D116 and planarizing the outer insulating spacers 118, the insulating liner 142, and the intergate insulating film 144.”, indicating that the intergate insulating film 144 wraps around the gate structure DGS);
partially removing (Fig. 14C, [0115]) the gate stack structure (dummy gate structures DGS, Fig. 14C) to form a first trench (gate cut space CTS in the middle, see first trench in Illustrative Fig. 1, which is the annotated version of Fig. 14C) in the gate stack structure (dummy gate structures DGS comprising oxide film D112 and dummy gate layer D114, Illustrative Fig. 1), wherein the gate stack structure (oxide film D112 and dummy gate layer D114, Illustrative Fig. 1) is divided into a first gate stack (first gate stack, Illustrative Fig. 1) and a second gate stack (second gate stack, Illustrative Fig. 1) by the first trench (first trench, Illustrative Fig. 1), the first gate stack (first gate stack, Illustrative Fig. 1) is over the first fin (second fin active region F2, Illustrative Fig. 1), and the second gate stack (second gate stack, Illustrative Fig. 1) is over the second fin (fist fin active region F1, Illustrative Fig. 1);
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forming an isolation structure (gate cut insulating film 150 in the middle, Fig. 15C, [0116]) in the first trench (first trench, Illustrative Fig. 1, para [0116]: “ … gate cut insulating films 150 respectively filling the gate cut spaces CTS may be formed …”), wherein the gate stack further comprises a second semiconductor layer (dummy gate layer D114, Illustrative Fig. 1) ;
removing the first gate stack (first gate stack, Illustrative Fig. 1) and the second gate stack (first gate stack, Illustrative Fig. 1) to form a first recess (gate spaces GS on the right, see first recess in Illustrative Fig. 2, which is an annotated version of Fig. 27A, [0146]) and a second recess (second recess, Illustrative Fig. 2) in the dielectric layer (intergate insulating film 144, Fig. 15B: cross section towards Y direction shows that first and second recesses are formed through the intergate insulating film 144);
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forming a first metal gate stack (see first metal gate stack in Illustrative Fig. 3, which is an annotated version of Yang’s Fig. 27F-, [0152]-[0153]; [0056]: while in Yang the stack on the first fin active region F1 comprises PMOS transistors and the stack on the second fin active region F2 comprises NMOS transistors, a person of ordinary skill in the art before the effective filing date of the claimed invention would know that the method also applies if NMOS transistors and PMOS transistors are flipped) and a second metal gate stack (second metal gate stack, Illustrative Fig. 3) in the first recess (first recess in Illustrative Fig. 3) and the second recess (second recess, Illustrative Figs. 3) respectively, wherein a top of the first metal gate stack (first metal gate stack, Illustrative Fig. 3) is substantially as high as a top of the isolation structure (inter-region insulating pattern 550C, Illustrative Fig. 3, [0152]: inter-region insulating pattern 550C is the remaining portion of the middle gate cut insulating film 150 (see Fig. 27E)); and
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forming ([0154]) a conductive line (conductive line 586, see Illustrative Fig. 4 which is an annotated version of Fig. 10, [0154]) over the first metal gate stack (first metal gate stack, Illustrative Fig. 4), the second metal gate stack (second metal gate stack, Illustrative Fig. 4), and the isolation structure (inter-region insulating pattern 550C, Illustrative Fig. 4), wherein the conductive line (conductive line 586, Illustrative Fig. 4) electrically connects the first metal gate stack (first metal gate stack, Illustrative Fig. 4) to the second metal gate stack (second metal gate stack, Illustrative Fig. 4, [0154]: conductive line 586 electrically connects first metal gate stack and second metal gate stack via gate contacts 582), and the conductive line (conductive line 586, Illustrative Fig. 4) extends across opposite sidewalls (left and right sidewalls, Illustrative Fig. 4) of the isolation structure ((inter-region insulating pattern 550C, Illustrative Fig. 4: conductive line 586 extends across right and left sidewalls from top view).
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Yang, however, fails to teach that
the gate stack further comprises a first semiconductor layer, an etch stop layer, and a second semiconductor layer sequentially stacked over the substrate, and the etch stop layer is partially exposed after the first trench is formed and before the isolation structure is formed.
Yang does not teach forming a first semiconductor layer and an etch stop layer as part of the gate stack (see Yang’s Fig. 13C, where dummy gate stack DGS has only the second semiconductor layer (dummy gate layer D114)). There was no other prior art identified that could be combined with Yang to make the claim 1 obvious. While there is prior art, such as Foguer (US 2023/0065970 A1), Chen (US 2019/0334008 A1), or Li (US 2022/0013527 A1), that used an etch stop layer around the gate stack, and a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to include an etch stop layer in the gate stack structure to protect the semiconductor structures under the etch stop layer during etching, none of the prior art included a first semiconductor layer below the etch stop layer, as disclosed in claim 1, and there has been no motivation to include the first semiconductor layer in the method of Yang. Therefore, claim 1 would be allowable if the claim objection on claim 1 is overcome.
Claims 2-7, 9, and 21 would be also allowable if the claim objection on claim 1 is overcome, as these claims depend on claim 1.
Claim 11-15 are allowed.
Independent claim 11 is allowed, because the references of the Prior Art of record and considered pertinent to the applicant’s disclosure and examiner’s knowledge does not teach or render obvious, as least to the skilled artisan, the instant invention regarding the limitation that
the gate stack structure comprises a first semiconductor layer, an etch stop layer, and a second semiconductor layer sequentially stacked over the substrate;
partially removing the etch stop layer and the first semiconductor layer through the first trench to form a second trench passing through the etch stop layer and the first semiconductor layer, wherein the gate stack structure is divided into a first gate stack and a second gate stack by the first trench and the second trench,
as recited in claim 11, in combination with the remaining structural components of the claim.
Regarding the allowability of claim 11, the closest art that have been identified is Yang (US 2022/0173097 A1). Yang teaches all the limitations of the method of claim 11 (see the description of Yang regarding the claim 1 above, as claim 1 has similar limitations as claim 11) except the one stated above. Regarding the stated limitation, Yang does not teach forming a first semiconductor layer and an etch stop layer as part of the gate stack (see Yang’s Fig. 13C, where dummy gate stack DGS has only the second semiconductor layer (dummy gate layer D114)). Also, there is only a single trench formed in the method of Yang (see Fig 14C). There was no other prior art identified that could be combined with Yang to make the claim 11 obvious. While there is prior art, such as Foguer (US 2023/0065970 A1), Chen (US 20190334008 A1), or Li (US 2022/0013527 A1), that used an etch stop layer around the gate stack, none of the prior art included a first semiconductor layer below the etch layer, as disclosed in claim1, for the purpose of forming a second trench through the first trench. Therefore, claim 11 is allowable.
Claims 12-15 are also allowed, because these claims inherit the allowable subject matter from claim 11.
Response to Arguments
It has been acknowledged that the Applicant amended independent claims 1 and 16, canceled claim 22, and added claim 24 as a new claim per response dated on 2/10/2026.
Regarding independent claim 1, the Applicant amended claim 1 to include allowable subject matter from previously objected claim 22. Therefore, the amended independent claim 1 contains allowable subject matter. An updated search targeting the allowable subject matter did not lead to a prior art that can render the independent claim 1 anticipated or obvious. However, independent claim 1 is now objected as detailed in the office action above. Accordingly, claims that depend on claim 1 are also objected.
Regarding independent claim 16, the Applicant amended claim 16 by including a new limitation that “an interface between the conductive line and the isolation structure is substantially level with the top of the second metal gate stack”. The Examiner agrees with the Applicant that the amended claim 16 overcame the rejection based on Yang (US 2022/0173097 A1). Claim 16, however, is not rejected under new grounds based on new prior art Wei (US 2023/0062210 A1) and Hsu (US 2022/0037519 A1) in the current office action. Claims 18-20 and 23-24 are also rejected based on these prior art or their combination with others.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chen (US 2023/0061555 A1) teaches a semiconductor device structure (Fig. 24A), which teaches all the limitations of claim 16, and further relevant to claims 18-20 and 23-24.
Chen (US 2023/0141523 A1) teaches a semiconductor device structure (Fig. 12), which teaches all the limitations of claim 16, and further relevant to claims 18-20 and 23-24.
Ju (US 2022/0238717 A1) teaches a semiconductor device structure (Fig. 37B), which teaches all the limitations of claim 16, and further relevant to claims 18-20 and 23-24.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ILKER OZDEN whose telephone number is (703)756-5775. The examiner can normally be reached Monday - Friday 8:30am-5:30pm.
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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