Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 10/22/2025 have been fully considered but they are not persuasive. Per applicants arguments on pages 7-9, Claim 1 states “… a flange pattern protruding from the device layer…” which is designated as element 106 in the present disclosure. The prior art, Vaufredaz, discloses the same limitation where element 1110 is part of the device layer [element 111] in figures 4A-4G. The claim also designates that the substrate “…having…” a flange pattern, which under a broadest reasonable interpretation can indicate an experience or process to undergo. The substrate, element 113, of Veufredaz, does experience and undergo the trimming process that creates the protrusion attached to the device layer (the claim language states “from the device layer”, which would be better worded “with respect to the device layer” so there is no confusion if the protrusion is part of the device layer). If the applicant wishes to ensure that the substrate is the layer that is trimmed to only contain the flange portion, it is recommended that the applicant clear up the language to ensure that it is only the substrate that has a protrusion which contains the flange and not the device layer, as stated (even if the claim language was made clear - simply switching element 111 to be the substrate and element 113 to be the device layer would result in the claim language Applicant is arguing, so further clarity is recommended). Similarly, per applicants arguments on pages 9 – 11, regarding claim 9, the thickness and depth are defined in reference to bonding and non-bonding regions, where the first thickness in Vaufredaz is defined as the cumulative thickness of elements 113, 112 and 111, and the depth of the non-bonding region is less than said thickness by an amount of the thickness of the flange portion 1110. Thus, the arguments are not persuasive (note this is being interpreted in the y-direction, if applicant requires a different direction, this should be clarified in the claim language). In regards to the applicants’ arguments on pages 11-13 regarding claim 16, the opening created by the trimming method is indeed the shape of a ring (defined as a “circular-object” which is the common, broadest reasonable interpretation of the definition of “ring”), and the central portion is also ring shaped (see figures 2 and 3 of Vaufredaz, see also col 3 lines 49-51), such that the central region is in the shape of a ring. If there is further definition of what is meant by “ring shaped opening in the central region and edge region” it is recommended that the applicant further limit the definition of “ring” and “opening” in the claim such that it is clear the opening must be closed on certain sides and cannot just contain an open area.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7, 9-12, 16, and 18-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Vaufredaz et al (8314007 B2).
Vaufredaz teaches
[claim 1] A trimming method, comprising: providing a first wafer including a substrate and a device layer over a first side of the substrate; bonding the first wafer to a second wafer with the first side of the substrate facing toward the second wafer (figure 4A-4D, col 4 lines 9-13, where element 111 is the device layer [i.e. silicon layer], and the first substrate is element 113 with a bonding layer element 114 that connects the first wafer, element 110, to the second wafer, element 120, where the first wafter is connected to the second wafer in a direction of element 111, which is the first direction);
performing an edge trimming process to remove a trimmed portion of the substrate from a second side opposite to the first side vertically downward toward the first side in a first direction along a perimeter of the substrate, wherein the edge trimming process results in the substrate having a flange pattern laterally protruding from the device layer and laterally surrounding an untrimmed portion of the substrate along a second direction perpendicular to the first direction (figures 4A-4D, col 5 line 1 – col 6 line 4, where element 110 is the first wafer, element 120 is the second wafer, and a trimming of the first wafer happens vertically from a second side [side away from second wafer] to first side [side connected to second wafer] leaving behind a flange, element 1110 that laterally protrudes from the first substrate and in a direction perpendicular to a first direction [horizontal is perpendicular to vertical [[first direction]]]),
and performing a grinding process on the untrimmed portion of the substrate from the second side to thin the untrimmed portion of the substrate to a reduced thickness in the first direction, wherein the grinding process results in the reduced thickness being greater than a thickness of the flange pattern (figures 4E-4G, col 6 line 19 – col 7 line 13, where element 210 grinds the untrimmed portion of the substrate to a reduced thickness in the vertical direction [first direction], such that in figure 4G the height of the 1110 [the flange] is less than the height of the trimmed portion, thus the untrimmed portion has a greater thickness than the flange pattern).
[claim 2] The trimming method according to claim 1, wherein along the first direction, a vertical projection of the flange pattern onto the second wafer is overlapped with a span of a vertical projection of the device layer onto the second wafer (figure 4G, element 1110 is the flange, element 111 is the device layer, and each’s projection onto the second wafer [element 120] provides the glange overlapped with a span of the device layer).
[claim 3] The trimming method according to claim 1, wherein the first wafer further comprises an etch stop layer over the first side of the substrate and between the substrate and the device layer (figure 4G, col 4 lines 28-31, where element 114 is a thermal oxide layer which oxidizes the silicon substrate and thus creates silicon oxide, which is a known etch stop layer material, thus functionally acting as an etch stop layer placed over the first side of the substrate [side attached to second wafer, element 120]).
[claim 4] The trimming method according to claim 3, wherein the flange pattern is in contact with the etch stop layer (figure 4G, element 111 with a flange [element 1110] is in contact with element 114, the etch stop layer).
[claim 5] The trimming method according to claim 3, after performing the grinding process, further comprising: removing the substrate to expose the etch stop layer; and removing the etch stop layer to expose the device layer (figure 4G, col 7 lines 14-27, where the substrate [element 113] is removed exposing an etch stop layer [element 112], and element 112 can also be removed exposing the device layer [element 111]).
[claim 6] The trimming method according to claim 1, wherein a thickness of the trimmed portion of the substrate is less than a thickness of the untrimmed portion of the substrate along the first direction (figure 4G, where the trimmed portion is the side of elements 112 and 11 that go from the top to the flange portion [element 1110], and the untrimmed portion is the same layers but going a full height to the etch stop layer, element 114, thus the untrimmed height is greater than the trimmed height).
[claim 7] The trimming method according to claim 1, wherein a thickness difference between the reduced thickness of the untrimmed portion and the thickness of the flange pattern is greater than 1 μm (figure 4G, col 5 lines 51-63 where element 110 has thickness of 55 micrometers or less, and per col 6 lines 63-64 the substrate has thickness of 65 micrometers, thus making the difference between the untrimmed portion and the flange thickness being greater than 1 micrometer [10 micrometers specifically]).
[claim 9] A trimming method, comprising: providing a first wafer including a semiconductor substrate and a device layer, wherein the semiconductor substrate has a bonding region and a non-bonding region surrounding the bonding region, the semiconductor substrate has a first surface and a second surface opposite to the first surface in the bonding region, and the device layer is disposed over the first surface of the semiconductor substrate, wherein the bonding region of the semiconductor substrate has a first thickness; bonding the first wafer to a second wafer with the device layer being between the second wafer and the semiconductor substrate (figure 4D, col 5 lines 6-37, where element 110 is the first wafer, and element 120 is the second wafer, the first substrate is element 113 and has a first side where the device region is attached, which is element 111. The Bonding region is the region on the inside of the flange portion, element 1110, and the non-bonding region is the region that contains the flange region, element 1110. When looking down onto the substrate, a horizontal cross-section of the substrate the non-bonding region surrounds the bonding region, interpreting the language per applicant’s use in the specification, where the first thickness [higher pd + e of figure 4D] is over 65 micrometers [depth of bonding region of substrate where it is trimmed down as shown to the level of figure 4G).
trimming the non-bonding region of the semiconductor substrate from the second surface of the semiconductor substrate downward toward the first surface along a perimeter of the substrate to a trimming depth and form a trimmed edge, wherein the trimming depth is less than the first thickness (figure 4D, col 5 lines 51-63, where the non-bonding region [vertical projection of the width of flange element 1110] is trimmed from a second surface [surface facing away from element 120] to a first surface [surface facing element 120 and containing elements 111 and 114], where the trimming depth is equivalent to the thickness of element 113, 112 and the portion of element 111 that does not have the flange, element 1110; the first thickness [within the bonding region] is equivalent to the thickness of element 113, 112 and all of element 111, thus the trimming depth is less than the first thickness by an amount of the thickness of element 1110),
and thinning the bonding region of the semiconductor substrate from the second surface of the semiconductor substrate to reduce the first thickness to a second thickness, wherein a thickness difference between the first thickness and the second thickness is less than the trimming depth (figures 4F and 4G, where the first wafer is thinned down from a second surface to a first surface [negative y-direction], and the difference in thickness is equivalent to the thickness of element 113, where element 113 has a thickness less than the trimming depth [which is equal to the thickness of element 113, 112 and the portion of element 111 no covered by element 1110], thus the thickness of element 113 necessarily is less than the thickness of element 113 plus the thickness of element 112 and part of element 111).
[claim 10] The trimming method according to claim 9, wherein the trimmed edge is located within the bonding region of the semiconductor substrate (figure 4F, a side edge of element 113 above flange element 1110 is within the bonding region and part of the substrate of the first wafer).
[claim 11] The trimming method according to claim 9, wherein the first wafer further comprises an etch stop layer in the bonding region of the semiconductor substrate and between the semiconductor substrate and the device layer (figure 4F, col 7 lines 23-27, element 112 is the etch stop layer in the bonding region between the substrate [element 113] and the device layer [element 111]).
[claim 12] The trimming method according to claim 11, after the step of thinning the bonding region of the semiconductor substrate, further comprising: removing the semiconductor substrate by a first etching process; and removing the etch stop layer by a second etching process, wherein during the first etching process, the semiconductor substrate and the etch stop layer comprise materials with different etching selectivities (col 7 lines 14-27, where the substrate is removed by a plasma etching or dry etching, and the etch stop layer is removed by wet etchings, where the substrate is made of silicon and the etch-stop layer is made of silicon oxide which have different etching selectivities).
[claim 16] A trimming method, comprising: providing a first wafer including a semiconductor substrate and a device layer, wherein the semiconductor substrate has a central region and an edge region surrounding the central region, the semiconductor substrate has a first surface and a second surface opposite to the first surface in the central region, and the device layer is disposed over the first surface of the semiconductor substrate along a thickness direction ((figure 4D, col 5 lines 6-37, where element 110 is the first wafer, and element 120 is the second wafer, the first substrate is element 113 and has a first side where the device region is attached, which is element 111. The central region is the region on the inside of the flange portion, element 1110, and the edge region is the region that contains the flange region, element 1110. When looking down onto the substrate, a horizontal cross-section of the substrate the edge region surrounds the central region, interpreting the language per applicant’s use in the specification).
bonding the first wafer to a second wafer with the first surface being nearer to the second wafer than the second surface along the thickness direction; performing an edge trimming process on the semiconductor substrate from the second surface toward the first surface along the thickness direction to form a ring-shaped opening in the central region and the edge region (figure 4D, where the second wafer [element 120] is bonded to the first surface of the first wafer [element 110] thus making the first surface closer to the second wafer than the second surface [top of element 113 of figure 4D], where the trimming creates an edge region [second ld] where the ring-shaped opening is the ring around the substrate that constitutes the inner half of the width ‘ld’ and the outer region constitutes the outer half of the width ‘ld’ around the wafer);
and performing a thinning process on the second surface of the semiconductor substrate to allow a bottom surface of the ring-shaped opening is lower than the second surface (figure 4D, where the bottom of the ring shaped opening is the top of element 1110, which is lower than the second surface [top of element 113]).
[claim 18] The trimming method according to claim 16, wherein the thinning process is a grinding process (figure 4E, col 6 lines 39-46, where element 210 is a grinding machine that grinds the substrate to thin the substrate).
[claim 19] The trimming method according to claim 16, wherein the first wafer further comprises an etch stop layer in the central region of the semiconductor substrate and between the semiconductor substrate and the device layer (figure 4E-4F, col 7 lines 23-27, where element 112 is the etch stop layer and is situated between the substrate [element 113] and the device layer [element 111]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8, 13-15, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Vaufredaz et al (8314007 B2) in view of Hsieh (US 20080044984 A1).
Vaufredaz teaches all of the limitations of the parent claim, claim 1, and additionally teaches
[claim 8] The trimming method according to claim 1, wherein the flange pattern is resulted by performing the edge trimming process (figures 4E-4G, where the flange pattern [element 1110] is a result of performing trimming on the edge of the wafer [element 110]).
[claim 20] The trimming method according to claim 16, wherein the ring-shaped opening is formed by performing the edge trimming process (figures 4E-4G, where the flange pattern [element 1110] is a result of performing trimming on the edge of the wafer [element 110], and the ring-shaped opening on the inner-half of width ‘ld’ is formed via the same way).
However, Vaufredaz does not specifically dislose
[claim 8 & 20] followed by a bevel etching process.
[claim 13] The trimming method according to claim 9, wherein the non-bonding region of the semiconductor substrate includes a first bevel region extending between the first surface and an outermost edge of the semiconductor substrate, and a second bevel region extending between the outermost edge and the second surface.
[claim 14] The trimming method according to claim 13, wherein after the non-bonding region of the semiconductor substrate is trimmed, the second bevel region is removed while the first bevel region remains.
[claim 15] The trimming method according to claim 14, after the non-bonding region of the semiconductor substrate is trimmed and before the bonding region of the semiconductor substrate is thinned, further comprising performing a bevel etching process to remove the remained first bevel region.
However, Hsieh does teach
[claim 8 & 20] followed by a bevel etching process (paragraph 0039, where the etch method is wet etch, and can remove part of the bevel, thus being a bevel etch, with the option of it being followed by the blade trimming).
[claim 13] The trimming method according to claim 9, wherein the non-bonding region of the semiconductor substrate includes a first bevel region extending between the first surface and an outermost edge of the semiconductor substrate, and a second bevel region extending between the outermost edge and the second surface (figure 4B, paragraphs 0030-0034, where the non-bonding region is represented by the distance “d” and surrounds the wafer, the bonding region is the rest of the wafer, the first bevel region is the lower half of the bevel in figure 4B situated in the non-bonding region [region represented by distance “d”], and the second bevel region is the top half [which is shown being removed, best shown in figure 4A where it is present]).
[claim 14] The trimming method according to claim 13, wherein after the non-bonding region of the semiconductor substrate is trimmed, the second bevel region is removed while the first bevel region remains (figures 4B and 4C, paragraphs 0030-0034 where the second bevel region is removed by the step shown in figure 4B and in figure 4C it is shown that the first bevel region remains).
[claim 15] The trimming method according to claim 14, after the non-bonding region of the semiconductor substrate is trimmed and before the bonding region of the semiconductor substrate is thinned, further comprising performing a bevel etching process to remove the remained first bevel region (paragraph 0039, where the etch method is wet etch, and can remove part of the bevel, thus being a bevel etch, with the option of it being followed by the blade trimming).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Vaufredaz with the teachings of Hsieh in order to etch a Bevel (curved portion of the substrate) to reduce defect density of the wafer that may appear after a mechanical trimming process, such as grinding or other common mechanical methods of trimming the wafer.
Claim(s) 17 is rejected under 35 U.S.C. 103 as being unpatentable over Vaufredaz et al (8314007 B2) in view of Shih et al (US 20120270394 A1).
Vaufredaz teaches all of the limitations of the parent claim, claim 16, but does not specifically disclose
[claim 17] wherein during the thinning process, the semiconductor substrate has a stepped profile.
However, Shih et al does teach
[claim 17] wherein during the thinning process, the semiconductor substrate has a stepped profile (figure 2B, paragraph 0016, where the thinning process contains a stepped semiconductor substrate, element 202, with the step shown by element 206).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Vaufredaz to incorporate the teachings of Shih et al in order to improve edge stability during the trimming process so the bevel doesn’t completely break off thus ensuring a higher quality wafer trimming.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW ZABEL whose telephone number is (703)756-4788. The examiner can normally be reached M-F 9-5PM ET.
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/ANDREW JOHN ZABEL/ Examiner, Art Unit 2818
/JEFF W NATALINI/ Supervisory Patent Examiner, Art Unit 2818