Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/07/2026 has been entered.
Response to Arguments
In response to the amendments filed on 05/07/2026, independent claims 1, 9 and 16 now overcome the previous prior art rejection. However, after further search and consideration a new rejection is formed with a new base reference, Tanou et al (US 20220406602, below. Per the applicants arguments, due to the amendments the arguments are no longer applicable.
Additionally, it is recommended by the examiner to consider describing the shape and size of the flange pattern in future potential amendments.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7, 9-12, 16, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Tanoue et al (US 20220406602) in view of Vaufredaz et al (8314007 B2).
Tanoue et al teaches
[claim 1] A trimming method, comprising: providing a first wafer including a substrate and a device layer over a first side of the substrate (figure 1A, paragraph 0018, where element W1 is the substrate of the wafer, and element D below element W1 is the device layer of the first wafer),
wherein the substrate is integrally formed as one single piece (figure 1, paragraph 0018, where element W1, D and F [below element W1] comprise the first integrally formed wafer, and element W2, D and F [directly above W2] comprise the second integrally formed wafer);
bonding the first wafer to a second wafer with the first side of the substrate facing toward the second wafer (figure 1A, paragraph 0018, where the first wafer [W1, D and F] and the second wafer [W2, D and F] are bonded together with a first side of the substrate [element W1] being the bottom side which faces the second wafer [element W2, D and F]),
wherein the device layer is located between the substrate and the second wafer (figure 1A, paragraph 0018, where element D directly below and touching element W1 is the device layer and is situated between the substrate [element W1] and the second wafer [element W2, D and F directly bove]),
performing an edge trimming process to remove a trimmed portion of the substrate from a second side opposite to the first side vertically downward toward the first side in a first direction along a perimeter of the substrate (figures 3-5D, paragraph 0065, where section We is the edge portion that is removed by step S4 of figure 3, where the process is done vertically top down where cracks are formed [top down] then the edge portion is removed),
wherein the edge trimming process results in a flange pattern of the substrate having a flange pattern laterally protruding from the device layer and laterally surrounding an untrimmed portion of the substrate along a second direction perpendicular to the first direction, and a bottom surface of the flange pattern is aligned with a bottom surface of the untrimmed portion (figure 5A-5D, paragraph 0065, see figure 1 below for specific visual representation of the flange – where the flange pattern is the angled part of element Wd1 sticking out from the vertical part, where the flange laterally protrudes from the untrimmed portion [element Wc of figures 4A-4D], and surrounds the untrimmed portion in a second direction [horizontal direction] which is perpendicular to the first [vertical direction], and the bottom surface of the untrimmed portion and the flange are substantially aligned. Please note, figure 1B shows that the whole wafer is circular in nature, and figures 4A-5D are just a cross-sectional image of the device, so the flange portion surrounds the untrimmed portion in a circular nature).
[claim 9] A trimming method, comprising: providing a first wafer including a semiconductor substrate and a device layer (figure 1A, paragraph 0018, where element W1 is the substrate of the wafer, and element D below element W1 is the device layer of the first wafer),
wherein the semiconductor substrate has a bonding region and a non-bonding region surrounding the bonding region (figure 1A, paragraph 0018, where element We is the non-bonding region and element Wc is the bonding region where the non-bonding region surrounds the bonding region),
the semiconductor substrate has a first surface and a second surface opposite to the first surface in the bonding region, the semiconductor substrate is integrally formed as one single piece, and the device layer is disposed over the first surface of the semiconductor substrate (figure 1A, paragraph 0018, where element W1 [substrate] has a first surface [bottom surface] and second surface [top surface] which are opposite to one another, and the substrate is integrally formed as one piece with the device layer [element D below W1] and the device layer is disposed over [note when bonding the wafer is flipped upside down to what is shown in figure 1A, thus element D would be “over” element W1 at the moment of bonding]),
wherein the bonding region of the semiconductor substrate has a first thickness (figure 1A, paragraph 0018, where element We has a first thickness that is the thickness of element W1 in the vertical direction),
bonding the first wafer to a second wafer with the device layer being between the second wafer and the semiconductor substrate (figure 1A, paragraph 0018, where the first wafer [W1 and layers F and D directly below] are bonded to the second wafer [element W2 and layers D and F directly above], where the device layer [element D directly below element W1] is situated between the substrates [elements W1 and W2]);
trimming the non-bonding region of the semiconductor substrate from the second surface of the semiconductor substrate downward toward the first surface along a perimeter of the substrate to a trimming depth and form a trimmed edge (figures 3-5D, paragraph 0065, where section We is the non-bonding region that is trimmed down by step S4 of figure 3, where the process is done vertically top down where cracks are formed [top down] then the edge portion is removed. The depth of the trimming in the non-bonding region is defined as the depth from the top of element W1 to the top of the triangle portion of the flange as shown in Figure 1 above),
wherein the trimming depth is less than the first thickness (figures 3-5D, where the trimming depth [top of element W1 to top of flange portion as shown in Figure 1 above] is less than the first thickness [full thickness of element W1]);
[claim 16] A trimming method, comprising: providing a first wafer including a semiconductor substrate and a device layer (figure 1A, paragraph 0018, where element W1 is the substrate of the wafer, and element D below element W1 is the device layer of the first wafer),
wherein the semiconductor substrate has a central region and an edge region surrounding the central region (figure 1A, paragraph 0018, where the central region is section Wc and the edge region is element We),
the semiconductor substrate has a first surface and a second surface opposite to the first surface in the central region (figure 1A, paragraph 0018, where element W1 is the substrate and has a first surface [bottom surface as seen in figure 1A] and a second surface [top surface]),
the semiconductor substrate is integrally formed as one single piece, and the device layer is disposed over the first surface of the semiconductor substrate along a thickness direction (figure 1A, paragraph 0018, the substrate is integrally formed as one piece with the device layer [element D below W1] and the device layer is disposed over the substrate [note when bonding the wafer is flipped upside down to what is shown in figure 1A, thus element D would be “over” element W1 at the moment of bonding] in the thickness direction [y-direction as seen in figures 4A-5D]),
bonding the first wafer to a second wafer with the first surface being nearer to the second wafer than the second surface along the thickness direction (figure 1A, paragraph 0018, where the first wafer is bonded to the second wafer where the first surface of element W1 is closer to the second wafer [element W2 with elements F and D directly above] than the second surface [top surface of element W1]),
wherein the device layer is located between the semiconductor substrate and the second wafer (figure 1, paragraph 0018, where element D [device layer] is situated between the substrate [element W1] and the second wafer [elements S2 and layers F and D directly above]);
performing an edge trimming process on the semiconductor substrate from the second surface toward the first surface along the thickness direction to form a ring-shaped opening in the central region and the edge region, wherein a bottom surface of the ring-shaped opening is defined by the semiconductor substrate (figures 3-5D, paragraph 0065, where section We is the edge region that is trimmed down by step S4 of figure 3, where the process is done vertically top down where cracks are formed [top down] then the edge portion is removed. Note from figure 1B, the entire wafer is circulate in shape, thus the trimming method trims the edge portion such that there is a ring-shaped opening in the central region surrounded by the edge region [seen by figure 1B]).
However, Tanoue et al does not specifically disclose
[claim 1] and performing a grinding process on the untrimmed portion of the substrate from the second side to thin the untrimmed portion of the substrate to a reduced thickness in the first direction, wherein the grinding process results in the reduced thickness being greater than a thickness of the flange pattern.
[claim 9] and thinning the bonding region of the semiconductor substrate from the second surface of the semiconductor substrate to reduce the first thickness to a second thickness, wherein a thickness difference between the first thickness and the second thickness is less than the trimming depth.
[claim 16] and performing a thinning process on the second surface of the semiconductor substrate to allow the bottom surface of the ring-shaped opening is lower than the second surface.
However, Vaufredaz teaches
[claim 1] and performing a grinding process on the untrimmed portion of the substrate from the second side to thin the untrimmed portion of the substrate to a reduced thickness in the first direction, wherein the grinding process results in the reduced thickness being greater than a thickness of the flange pattern (figures 4E-4G, col 6 line 19 – col 7 line 13, where the first wafer [element W1 and layers F and D directly below of Tanoue et al] is substituted for element 110, where element 210 grinds the untrimmed portion of the substrate to a reduced thickness in the vertical direction [first direction], such that in figure 4G the height of the 1110 [the flange] is less than the height of the trimmed portion, thus the untrimmed portion has a greater thickness than the flange pattern).
[claim 9] and thinning the bonding region of the semiconductor substrate from the second surface of the semiconductor substrate to reduce the first thickness to a second thickness, wherein a thickness difference between the first thickness and the second thickness is less than the trimming depth (figures 4F and 4G, where the first wafer [element W1 and F and D from Tanoue et al is in place of element 110 of Vaufredez et al] is thinned down from a second surface to a first surface [negative y-direction], and the difference in thickness is equivalent to the thickness of element 113, where element 113 has a thickness less than the trimming depth [which is equal to the thickness of element 113, 112 and the portion of element 111 no covered by element 1110], thus the thickness of element 113 necessarily is less than the thickness of element 113 plus the thickness of element 112 and part of element 111).
[claim 16] and performing a thinning process on the second surface of the semiconductor substrate to allow a bottom surface of the ring-shaped opening is lower than the second surface (figure 4D, note element 110 is replaced by element W1 and layers F and D directly below element W1 of Tanoue et al, where the bottom of the ring shaped opening is the top of element 1110, which is lower than the second surface [top of element 113]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Lee et al with the teachings of Vaufredaz et al in order to improve surface quality by performing such precision trimming so as not to cause undue structural stress on the wafers to cause cracks or breaks or weakness in the structure, thus improving overall durability of the device.
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Figure 1: From figures 5A-5D of Tanoue et al (U 20220406602).
Regarding claims 2-7, 10-12, and 18-19
Tanoue et al as modified teaches all of the limitations of the parent claims, claims 1, 9 and 16, but however does not specifically disclose
[claim 2] The trimming method according to claim 1, wherein along the first direction, a vertical projection of the flange pattern onto the second wafer is overlapped with a span of a vertical projection of the device layer onto the second wafer.
[claim 3] The trimming method according to claim 1, wherein the first wafer further comprises an etch stop layer over the first side of the substrate and between the substrate and the device layer.
[claim 4] The trimming method according to claim 3, wherein the flange pattern is in contact with the etch stop layer.
[claim 5] The trimming method according to claim 3, after performing the grinding process, further comprising: removing the substrate to expose the etch stop layer; and removing the etch stop layer to expose the device layer.
[claim 6] The trimming method according to claim 1, wherein a thickness of the trimmed portion of the substrate is less than a thickness of the untrimmed portion of the substrate along the first direction.
[claim 7] The trimming method according to claim 1, wherein a thickness difference between the reduced thickness of the untrimmed portion and the thickness of the flange pattern is greater than 1 μm.
[claim 10] The trimming method according to claim 9, wherein the trimmed edge is located within the bonding region of the semiconductor substrate.
[claim 11] The trimming method according to claim 9, wherein the first wafer further comprises an etch stop layer in the bonding region of the semiconductor substrate and between the semiconductor substrate and the device layer.
[claim 12] The trimming method according to claim 11, after the step of thinning the bonding region of the semiconductor substrate, further comprising: removing the semiconductor substrate by a first etching process; and removing the etch stop layer by a second etching process, wherein during the first etching process, the semiconductor substrate and the etch stop layer comprise materials with different etching selectivities.
[claim 18] The trimming method according to claim 16, wherein the thinning process is a grinding process.
[claim 19] The trimming method according to claim 16, wherein the first wafer further comprises an etch stop layer in the central region of the semiconductor substrate and between the semiconductor substrate and the device layer.
However, Vaufredaz further teaches
[claim 2] The trimming method according to claim 1, wherein along the first direction, a vertical projection of the flange pattern onto the second wafer is overlapped with a span of a vertical projection of the device layer onto the second wafer (figure 4G, element 1110 is the flange, element 111 is the device layer, and each’s projection onto the second wafer [element 120] provides the glange overlapped with a span of the device layer).
[claim 3] The trimming method according to claim 1, wherein the first wafer further comprises an etch stop layer over the first side of the substrate and between the substrate and the device layer (figure 4G, col 4 lines 28-31, where element 114 is a thermal oxide layer which oxidizes the silicon substrate and thus creates silicon oxide, which is a known etch stop layer material, thus functionally acting as an etch stop layer placed over the first side of the substrate [side attached to second wafer, element 120]).
[claim 4] The trimming method according to claim 3, wherein the flange pattern is in contact with the etch stop layer (figure 4G, element 111 with a flange [element 1110] is in contact with element 114, the etch stop layer).
[claim 5] The trimming method according to claim 3, after performing the grinding process, further comprising: removing the substrate to expose the etch stop layer; and removing the etch stop layer to expose the device layer (figure 4G, col 7 lines 14-27, where the substrate [element 113] is removed exposing an etch stop layer [element 112], and element 112 can also be removed exposing the device layer [element 111]).
[claim 6] The trimming method according to claim 1, wherein a thickness of the trimmed portion of the substrate is less than a thickness of the untrimmed portion of the substrate along the first direction (figure 4G, where the trimmed portion is the side of elements 112 and 11 that go from the top to the flange portion [element 1110], and the untrimmed portion is the same layers but going a full height to the etch stop layer, element 114, thus the untrimmed height is greater than the trimmed height).
[claim 7] The trimming method according to claim 1, wherein a thickness difference between the reduced thickness of the untrimmed portion and the thickness of the flange pattern is greater than 1 μm (figure 4G, col 5 lines 51-63 where element 110 has thickness of 55 micrometers or less, and per col 6 lines 63-64 the substrate has thickness of 65 micrometers, thus making the difference between the untrimmed portion and the flange thickness being greater than 1 micrometer [10 micrometers specifically]).
[claim 10] The trimming method according to claim 9, wherein the trimmed edge is located within the bonding region of the semiconductor substrate (figure 4F, a side edge of element 113 above flange element 1110 is within the bonding region and part of the substrate of the first wafer).
[claim 11] The trimming method according to claim 9, wherein the first wafer further comprises an etch stop layer in the bonding region of the semiconductor substrate and between the semiconductor substrate and the device layer (figure 4F, col 7 lines 23-27, element 112 is the etch stop layer in the bonding region between the substrate [element 113] and the device layer [element 111]).
[claim 12] The trimming method according to claim 11, after the step of thinning the bonding region of the semiconductor substrate, further comprising: removing the semiconductor substrate by a first etching process; and removing the etch stop layer by a second etching process, wherein during the first etching process, the semiconductor substrate and the etch stop layer comprise materials with different etching selectivities (col 7 lines 14-27, where the substrate is removed by a plasma etching or dry etching, and the etch stop layer is removed by wet etchings, where the substrate is made of silicon and the etch-stop layer is made of silicon oxide which have different etching selectivities).
[claim 18] The trimming method according to claim 16, wherein the thinning process is a grinding process (figure 4E, col 6 lines 39-46, where element 210 is a grinding machine that grinds the substrate to thin the substrate).
[claim 19] The trimming method according to claim 16, wherein the first wafer further comprises an etch stop layer in the central region of the semiconductor substrate and between the semiconductor substrate and the device layer (figure 4E-4F, col 7 lines 23-27, where element 112 is the etch stop layer and is situated between the substrate [element 113] and the device layer [element 111]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Lee et al with the teachings of Vaufredaz et al in order to improve surface quality by performing such precision trimming so as not to cause undue structural stress on the wafers to cause cracks or breaks or weakness in the structure, thus improving overall durability of the device.
Claim(s) 8, 13-15, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Tanoue et al (US 20220406602), and Vaufredaz et al (8314007 B2) and in further view of Hsieh (US 20080044984 A1).
Tanoue et al as modified teaches all of the limitations of the parent claim, claim 1, and additionally teaches
[claim 8] The trimming method according to claim 1, wherein the flange pattern is resulted by performing the edge trimming process (figures 4A-5D, and figure 1 above, paragraph 0065 where the flange pattern is created by performing an edge trimming process),
[claim 20] The trimming method according to claim 16, wherein the ring-shaped opening is formed by performing the edge trimming process (figures 4A-5D, and figure 1 above, paragraph 0065 where the ring-shaped pattern as seen in figure 1B [element Wc in the middle] is created by performing an edge trimming process),
However, Tanoue et al as modified does not specifically disclose
[claim 8 & 20] followed by a bevel etching process.
[claim 13] The trimming method according to claim 9, wherein the non-bonding region of the semiconductor substrate includes a first bevel region extending between the first surface and an outermost edge of the semiconductor substrate, and a second bevel region extending between the outermost edge and the second surface.
[claim 14] The trimming method according to claim 13, wherein after the non-bonding region of the semiconductor substrate is trimmed, the second bevel region is removed while the first bevel region remains.
[claim 15] The trimming method according to claim 14, after the non-bonding region of the semiconductor substrate is trimmed and before the bonding region of the semiconductor substrate is thinned, further comprising performing a bevel etching process to remove the remained first bevel region.
However, Hsieh does teach
[claim 8 & 20] followed by a bevel etching process (paragraph 0039, where the etch method is wet etch, and can remove part of the bevel, thus being a bevel etch, with the option of it being followed by the blade trimming).
[claim 13] The trimming method according to claim 9, wherein the non-bonding region of the semiconductor substrate includes a first bevel region extending between the first surface and an outermost edge of the semiconductor substrate, and a second bevel region extending between the outermost edge and the second surface (figure 4B, paragraphs 0030-0034, where the non-bonding region is represented by the distance “d” and surrounds the wafer, the bonding region is the rest of the wafer, the first bevel region is the lower half of the bevel in figure 4B situated in the non-bonding region [region represented by distance “d”], and the second bevel region is the top half [which is shown being removed, best shown in figure 4A where it is present]).
[claim 14] The trimming method according to claim 13, wherein after the non-bonding region of the semiconductor substrate is trimmed, the second bevel region is removed while the first bevel region remains (figures 4B and 4C, paragraphs 0030-0034 where the second bevel region is removed by the step shown in figure 4B and in figure 4C it is shown that the first bevel region remains).
[claim 15] The trimming method according to claim 14, after the non-bonding region of the semiconductor substrate is trimmed and before the bonding region of the semiconductor substrate is thinned, further comprising performing a bevel etching process to remove the remained first bevel region (paragraph 0039, where the etch method is wet etch, and can remove part of the bevel, thus being a bevel etch, with the option of it being followed by the blade trimming).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Tanoue et al as modified with the teachings of Hsieh in order to etch a Bevel (curved portion of the substrate) to reduce defect density of the wafer that may appear after a mechanical trimming process, such as grinding or other common mechanical methods of trimming the wafer.
Claim(s) 17 is rejected under 35 U.S.C. 103 as being unpatentable over Tanoue et al (US 20220406602), and Vaufredaz et al (8314007 B2) and in further view of Shih et al (US 20120270394 A1).
Tanoue et al teaches all of the limitations of the parent claim, claim 16, but does not specifically disclose
[claim 17] wherein during the thinning process, the semiconductor substrate has a stepped profile.
However, Shih et al does teach
[claim 17] wherein during the thinning process, the semiconductor substrate has a stepped profile (figure 2B, paragraph 0016, where the thinning process contains a stepped semiconductor substrate, element 202, with the step shown by element 206).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Tanoue et al as modified to incorporate the teachings of Shih et al in order to improve edge stability during the trimming process so the bevel doesn’t completely break off thus ensuring a higher quality wafer trimming.
Conclusion
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/ANDREW JOHN ZABEL/ Examiner, Art Unit 2818
/JEFF W NATALINI/ Supervisory Patent Examiner, Art Unit 2818
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