Prosecution Insights
Last updated: May 04, 2026
Application No. 18/152,865

METHOD OF MANUFACTURING WAFER

Non-Final OA §102§103§112
Filed
Jan 11, 2023
Priority
Jan 27, 2022 — JP 2022-011228
Examiner
REIDA, MOLLY KAY
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Disco Corporation
OA Round
2 (Non-Final)
83%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
85%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
349 granted / 420 resolved
+15.1% vs TC avg
Minimal +2% lift
Without
With
+2.0%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
31 currently pending
Career history
451
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
46.3%
+6.3% vs TC avg
§102
34.5%
-5.5% vs TC avg
§112
15.9%
-24.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 420 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Election/Restrictions Applicant’s election without traverse of Species A, subspecies A2 relating to claims 1, 2, 4, 7, and 8 in the reply filed on 12/10/2025 is acknowledged. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on 01/11/2023 and 10/16/2025 have been considered by the examiner. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claim 10 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The claimed removing step is drawn to Figs. 14 and 15 wherein the “face side” of the wafer faces upwardly (Figs. 14, 15 and Applicant’s Specification para. 0068). There is not support for the combination of the claimed removing step wherein the “face side” of the wafer faces downwardly. The Examiner suggests cancellation of claim 10. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 2, and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeong et al. (KR2019-0085273A). Regarding independent claim 1, Jeong teaches a method of manufacturing a wafer (para. 0030+), comprising: a wafer (Fig. 1: PCB board (10)) preparing step of preparing a wafer including a plurality of semiconductor devices (1) joined to a substrate by respective adhesive layers (2) (Fig. 1; para. 0031); a determining step of determining whether each of the semiconductor devices joined to the substrate is defective or non-defective (para. 0030, 0032); a laser beam applying step (S20) of applying a laser beam to heat one of the adhesive layers by which one of the semiconductor devices that has been determined as defective is bonded to the substrate, thereby melting the adhesive layer in an area of the wafer that is irradiated with the laser beam (para.0030); and a treating step (S30, S40) of treating the semiconductor device released from a bonded state due to the adhesive layer being melted in the laser beam applying step, wherein the treating step is a removing step of removing the semiconductor device from the substrate (para. 0030), and wherein the removing step includes: a step of providing a removing unit (jig (20)) having a receptacle (receiving space (23)) and a suction blower mechanism (air blower tube (30)/suction tube (40)) attached to the receptacle (Figs. 3, 4); a step of positioning the receptacle over the semiconductor device (1) (Fig. 4), the receptacle being sized to receive at least one semiconductor device through a lower opening thereof (para. 0040); a step of applying the laser beam (L) through the receptacle to release the semiconductor device from the bonded state (S30); a step of ejecting a gas from the suction blower mechanism toward the semiconductor device released from the bonded state to lift the semiconductor device off the substrate (S40), and a step of attracting the lifted semiconductor device under suction into the receptacle to remove the semiconductor device from the substrate (S40) (abstract; para. 0030). Re claim 2, Jeong teaches wherein the laser beam is applied to the adhesive layer through the semiconductor device (Jeong Fig. 4). Re claim 8, Jeong teaches a non-defective semiconductor device bonding step (S50), after the removing step, of bonding a semiconductor device having same functions as those of the semiconductor device determined as defective to an area from which the semiconductor device determined as defective has been removed (para. 0030). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al. (KR2019-0085273A) in view of You et al. (US Pub. 2021/0193894) and further in view of Vaupel et al. (US Pub. 2013/0084658). Re claim 9, Jeong teaches wherein, in the wafer preparing step, the wafer is placed on the “repair dedicated device” (para. 0037) without further explanation and is silent with respect to the limitations of wherein “the wafer is attached to tape that is attached to a frame”. You teaches (Fig. 5A) wherein the wafer (210) is attached to a frame (stage and clamp) (para. 0099). It would have been obvious to one of ordinary skill in the art at the time of filing to look to You to provide that which was missing from Jeong; that is, specifics regarding a “repair dedicated device” such that the wafer to Jeong was attached to the frame of Jeong for the purpose of stabilizing the wafer. The combination of Jeong and You is silent with respect to tape; that is, Jeong used a clamp for attachment purposes instead of tape. Vaupel teaches that tape is known in the art to use tape for wafer attachment purposes in Fig. 3 where tape layer (35) is used to attach to a wafer (10) to a carrier (30). It would have been obvious to one of ordinary skill in the art at the time of filing to substitute tape as taught by Vaupel for the clamp(s) of You to provide the predictable result of attaching the wafer to the frame with a reasonable expectation of success. It is considered obvious to substitute one known element for another to obtain predictable results (MPEP 2143, I, B). Re claim 11, Jeong in view of You and Vaupel teaches wherein the wafer is attached to the tape so that a face side of the wafer faces upwardly (Jeong Fig. 4; You Fig. 7). Response to Arguments Applicant’s arguments with respect to claim 1 and its corresponding dependent claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOLLY KAY REIDA whose telephone number is (571)272-4237. The examiner can normally be reached M-F 8:30-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (571)272-4237. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOLLY K REIDA/Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Jan 11, 2023
Application Filed
Jan 06, 2026
Non-Final Rejection — §102, §103, §112
Apr 02, 2026
Response Filed
Apr 02, 2026
Examiner Interview Summary
Apr 02, 2026
Applicant Interview (Telephonic)
Apr 16, 2026
Final Rejection — §102, §103, §112 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
83%
Grant Probability
85%
With Interview (+2.0%)
2y 1m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 420 resolved cases by this examiner. Grant probability derived from career allowance rate.

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