DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims presented have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 21 and 25-27 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Lee et al. (US20170148914A1).
Regarding claim 21, Fig.5 of Lee teaches a method for forming a semiconductor structure, comprising:
forming a fin structure AP1/AP2 (para.0042) over a substrate 100 (para.0042);
forming a spacer layer 206 (para.0048) formed over the fin structure AP1/AP2;
forming a gate structure GE/GI (Fig.2B, para.0049) within the spacer layer 206;
forming an epitaxial structure SD1/SD2 (para.0097) over the fin structure AP1/AP2 and along an inner surface of the spacer layer 206, wherein forming the epitaxial structure SD1/SD2 comprises etching the fin structure AP1/AP2 (para.0060) and the spacer layer 206, and an air spacer AG (para.0078, as seen in Fig.5, second liner insulating layer 206 is disposed on the sidewalls of active patterns AP1 and AP2 and extend to the sidewalls of source/drain regions SD1 and SD2, air gap AG is then formed between the second liner insulating layer at the bottom side of the air gap and the source/drain region SD2 at the top side of the air gap) is formed between the spacer layer 206 and the epitaxial structure SD1/SD2; and
forming a contact etch stop layer 125 (para.0078) on the inner surface of the spacer layer 206 and an upper surface of the epitaxial structure SD1/SD2, wherein the contact etch stop layer 125 covers the air spacer AG.
Regarding claim 25, Lee further teaches the method as claimed in claim 21, further comprising:
forming an isolation structure ST (Fig.2B, para.00800) around the fin structure AP1/AP2 (para.0042), wherein the contact 165 (para.0068) comes into physically contact with a top surface of the isolation structure ST.
Regarding claim 26, Lee further teaches the method as claimed in claim 21, wherein forming the epitaxial structure SD1/SD2 (para.0097) further comprises:
forming a sidewall of the epitaxial structure SD1/SD2 protruding from a sidewall of the fin structure AP1/AP2 (para.0042), wherein a gap AG (para.0078) is formed between the sidewall of the epitaxial structure SD1/SD2 and the inner surface of the spacer layer 206 (para.0048).
Regarding claim 27, Lee further teaches the method as claimed in claim 21, wherein the air spacer AG (para.0078) is misaligned with the fin structure AP1/AP2 (para.0042) in a normal direction of the substrate 100 (para.0042).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US20170148914A1) in view of Wang et al. (US20200135932A1).
Regarding claim 1, Fig.5 of Lee teaches A method for forming a semiconductor structure, comprising:
forming a fin structure AP1/AP2 (para.0042) protruding from a substrate 100 (para.0042),
forming a spacer layer 206 (para.0048) over the fin structure AP1/AP2;
forming a first inter-layer dielectric (ILD) layer 130 (para.0067) over the spacer layer 206;
recessing the fin structure AP1/AP2, the first ILD layer ST2, and the spacer layer 206 to form a first opening CL (para.0095) through the first ILD layer 130, wherein the spacer layer 206 comprises a curved edge in the first opening CL;
forming an epitaxial structure SD1/SD2 (para.0097) in the first opening CL, wherein an air spacer AG (para.0078, as seen in Fig.5, second liner insulating layer 206 is disposed on the sidewalls of active patterns AP1 and AP2 and extend to the sidewalls of source/drain regions SD1 and SD2, air gap AG is then formed between the second liner insulating layer at the bottom side of the air gap and the source/drain region SD2 at the top side of the air gap) is formed between an edge of the epitaxial structure SD1/SD2 and the curved edge of the spacer layer 206;
forming a second ILD layer 150 (para.0066) over the epitaxial structure SD1/SD2 and the first ILD layer 130;
Lee does not teach wherein the fin structure comprises first semiconductor material layers and second semiconductor material layers alternately stacked; and
removing the first semiconductor material layers; and
forming a gate structure around the second semiconductor material layers.
Fig.3B of Wang teaches a semiconductor device that includes one or more semiconductor fins 204 protruding from a substrate 202 and separated by isolation structures 208; and wherein the semiconductor fin 204 may include alternating layers of semiconductor materials, e.g., semiconductor material 204A and semiconductor material 204B that is different from the semiconductor material 204B.
Fig.4B of Wang further teaches wherein portions of the semiconductor fins 204 are removed to form recesses 230 therein. Wang further teaches, in Figs. 9A-9C, wherein metal gate structure 270 are formed be depositing material layers of the metal gate structure 270 in the gaps formed between the layers of the semiconductor material 204A when the semiconductor material 204B is removed from the device 200 (para.0022, 0043).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include Wang’s semiconductor materials 204A and 204B and also the formation of gate structures in the teachings of Lee because the alternating layers of the semiconductor materials 204A and 204B are configured to provide multi-gate devices such as GAA FETs which, in turn, improve gate control by increasing gate-channel coupling, reduce OFF-state current, and reduce short-channel effects (Wang, [para.0023]).
Regarding claim 2, Lee further teaches the method as claimed in claim 1, further comprising:
forming a second opening (para.0067, there is an opening where source/drain contacts CA may penetrate the second interlayer insulating layer 150, the first interlayer insulating layer 130) through the second ILD layer 150 (para.0066) to expose the epitaxial structure SD1/SD2 (para.0097); and
forming a contact 165 (para.0068) in the second opening over the epitaxial structure SD1/SD2.
Regarding claim 3, Lee further teaches the method as claimed in claim 2, further comprising:
forming a contact spacer 160 (para.0068, wherein first conductive pattern 160 may be a barrier conductive pattern which may include at least one of titanium nitride, tungsten nitride, or tantalum nitride) on a sidewall of the second opening before forming the contact 165 (para.0068).
Regarding claim 4, Lee further teaches the method as claimed in claim 3, wherein the contact spacer 160 (para.0068) is in direct contact with the first ILD layer 130 (para.0067).
Regarding claim 11, Fig.5 of Lee teaches a method for forming a semiconductor structure, comprising:
forming a plurality of fin structures AP1/AP2 (para.0042) protruding from a substrate 100 (para.0042),
forming a spacer layer 206 (para.0048) over the fin structures AP1/AP2;
forming a contact etch stop layer 125 (para.0078) and an inter-layer dielectric (ILD) layer 130 (para.0103) over the spacer layer 206;
etching the ILD layer 130, the contact etch stop layer 125 and the spacer layer 206 to form a plurality of openings CL (para.0097) through the ILD layer 130 and the contact etch stop layer 125;
forming an epitaxial structure SD1/SD2 (para.0097) in each of the openings CL and over each of the fin structures AP1/AP2, wherein an air spacer AG (para.0078) is formed and interfaces with the spacer layer 206 and the epitaxial structure SD1/SD2;
Lee does not teach wherein each of the fin structures comprises first semiconductor material layers and second semiconductor material layers alternately stacked;
removing the first semiconductor material layers and second semiconductor material layers exposed in the openings;
removing the first semiconductor material layers; and
forming a gate structure around the second semiconductor material layers.
Fig.3B of Wang teaches a semiconductor device that includes one or more semiconductor fins 204 protruding from a substrate 202 and separated by isolation structures 208; and wherein the semiconductor fin 204 may include alternating layers of semiconductor materials, e.g., semiconductor material 204A and semiconductor material 204B that is different from the semiconductor material 204B.
Fig.4B of Wang further teaches wherein portions of the semiconductor fins 204 are removed to form recesses 230 therein. Wang further teaches, in Figs. 9A-9C, wherein metal gate structure 270 are formed be depositing material layers of the metal gate structure 270 in the gaps formed between the layers of the semiconductor material 204A when the semiconductor material 204B is removed from the device 200 (para.0022, 0043).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include Wang’s semiconductor materials 204A and 204B and also the formation of gate structures in the teachings of Lee because the alternating layers of the semiconductor materials 204A and 204B are configured to provide multi-gate devices such as GAA FETs which, in turn, improve gate control by increasing gate-channel coupling, reduce OFF-state current, and reduce short-channel effects (Wang, [para.0023]).
Regarding claim 12, Wang teaches the method as claimed in claim 11, further comprising:
forming an isolation structure 208 (Fig.4C, para.0046) between the fin structures 204 (para.0020), wherein a height difference between a bottom surface of the epitaxial structures 250 (Fig.5C, para.0034) and a top surface of the isolation structure 208 is greater than 0 and less than about 20 nm.
Regarding claim 13, Lee further teaches the method as claimed in claim 11, wherein a thickness of the spacer layer 206 (para.0048) is not less than a thickness of the contact etch stop layer 125 (para.0078).
Regarding claim 14, Lee further teaches the method as claimed in claim 11, further comprising: forming a contact 165 (para.0068) electrically and physically connected to adjacent two of the epitaxial structures SD1/SD2 (para.0067).
Claims 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US20170148914A1) in view of Wang et al. (US20200135932A1) and in further view of Wang et al. (US20190164966A1; hereinafter Wang’966).
Regarding claim 5, Lee further teaches the method as claimed in claim 1, further comprising: forming a first contact etch stop layer 125 (para.0078) over the spacer layer 206 (para.0048) before forming the first ILD layer 130 (para.0067).
Lee does not teach forming a second contact etch stop layer over the over the epitaxial structure before forming the second ILD layer.
Wang’966, in Fig.6 and Fig.14, teaches forming a first contact etch stop layer 610 (para.0025) over the spacer layer 310 (para.0025) before forming the first ILD layer 620 (para.0026); and forming a second contact etch stop layer 1410 (para.0037) over the over the epitaxial structure 420 (para.0021) before forming the second ILD layer 1420 (para.0038).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the second contact etch stop layer of Wang’966 in the teachings of Lee, as modified by Wang, in order to prevent epitaxial features 250 from getting etched.
Regarding claim 7, Fig.3C of Wang’966 teaches the method as claimed in claim 5, wherein recessing the fin structure 204 (para.0020) comprises removing a portion of the first contact etch stop layer (para.0052, forming a recess in the semiconductor) and a portion of the spacer layer 222 (para.0038).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US20170148914A1) in view of Wang et al. (US20200135932A1) and Wang et al. (US20190164966A1; hereinafter Wang’966) and in further view of Huang et al. (US20190371898A1).
Regarding claim 6, Lee does not teach wherein forming the second contact etch stop layer comprises forming the second contact etch stop layer lower than a top surface of the first contact etch stop layer.
Tsai teaches, in Fig.3, wherein a fin-shaped structure 14 on the substrate 12, an epitaxial layer 32 on the fin-shaped structure 14, a spacer 26 adjacent to the epitaxial layer 32 and fin-shaped structure 14, a cap layer 34 on the epitaxial layer 32, spacer 26, and STI 16, a first CESL 36 on the cap layer 34, a cap layer 38 on the first CESL 36, a second CESL 42 on the cap layer 38, and a cap layer 44 on the second CESL 42.
The first CESL 36 (the second contact etch stop layer) is formed lower than the second CESL 42 (the first contact etch stop layer).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the second contact etch stop layer lower than a top surface of the first contact etch stop layer as taught by Tsai because the first CESL 36 and second CESL 42 could have different stress depending on the demand of the product. (Tsai, [col.4, lines 1-3]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US20170148914A1) in view of Wang et al. (US20200135932A1) and in further view of Huang et al. (US20190371898A1).
Regarding claim 8, the combination of Lee and Wang does not teach wherein forming the epitaxial structure in the opening comprises forming the epitaxial structure having a height of about 30 nm to about 70 nm.
Fig.3A of Huang teaches the epitaxial source/drain regions are formed where portions of fin 274 were removed and wherein the cross-sectional area of the epitaxial source/drain regions along A-A line may have a height 292h that ranges from 40nm and 50nm. (Huang, [para.0029]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the height of Huang's epitaxial source/drain regions in the teachings of Lee, as modified by Wang, in order to allow enough room for forming recesses that can have increased contact area between the source/drain region and the conductive feature, and can enable reduced resistance therebetween (Huang, [para.0012]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US20170148914A1) in view of Wang et al. (US20200135932A1) and in further view of Xiao et al. (US20170110580A1).
Regarding claim 10, the combination of Lee and Wang does not teach wherein the method as claimed in claim 1, further comprising:
performing a gas treatment prior to forming the epitaxial structure, wherein the gas treatment comprises introducing a gas into the opening, and the gas comprises Si(CH3)4.
Xiao teaches, in paragraph 0043, wherein silicon-germanium (SiGe) 610 is formed in the source-drain trench in the PMOS device region 110 as a source-drain epitaxial material, in which the reactant gas for forming SiGe 610 is the mixed gas of germane (GeH.sub.4) and more than one of silane (SiH.sub.4), disilane (Si.sub.2H.sub.6), dichlorosilane (SiH.sub.2Cl.sub.2), trichlorosilane (SiHCl.sub.3), tetrachlorosilane (SiCl.sub.4) and tetramethylsilane (Si(CH.sub.3).sub.4). (Xiao, [para.0043])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Xiao's tetramethylsilane (Si(CH.sub.3).sub.4) as part of the reactant gas for forming a silicon-germanium (SiGe) 610 in the teachings of Lee, as modified by Wang, in order to act as a precursor that provides silicon.
Claims 22-24 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US20170148914A1) in view of Yu et al. (US11101347B2).
Regarding claim 22, Lee further teaches the method as claimed in claim 21, further comprising:
etching the contact etch stop layer 125 (para.0078);
forming a silicide layer (para.0068, wherein a metal silicide layer may be disposed between each of the source/drain contacts CA and each of the first and second source/drain regions SD1 and SD2) on the upper surface of the epitaxial structure SD1/SD2 (para.0067); and
Lee does not teach forming a contact over the silicide layer, wherein the contact extends lower than a bottom surface of the silicide layer.
Fig.10A of Yu teaches formation of silicide regions 78 and source/drain contact plugs 68; wherein the source/drain contact plugs 68 are formed over the silicide regions 78; and wherein portions of the source/drain contact plugs 68 extend lower than the middle portion of the silicide regions 78 (col.9, lines 34-35).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include Yu’s source/drain contact plugs 68 and silicide regions 78 in the teachings of Lee in order to reduce source/drain contact resistance.
Regarding claim 23, Lee further teaches the method as claimed in claim 22, further comprising:
forming a contact spacer 160 (para.0068 around the contact 165 (para.0068), wherein the contact spacer 160 vertically overlaps the contact etch stop layer 125 (para.0078).
Regarding claim 24, Lee further teaches the method as claimed in claim 23, wherein the air spacer AG (para.0078) is sealed by the contact spacer 160 (para.0068), the epitaxial structure SD1/SD2 (para.0097) and the spacer layer 206 (para.0048).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT KIPKEMOI RONO whose telephone number is (571)270-5977. The examiner can normally be reached Mon-Fri, 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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VINCENT KIPKEMOI. RONO
Examiner
Art Unit 2891
/V.K.R./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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