DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on 07/26/2025 is acknowledged.
Claims 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 07/26/2025.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4,9,11-14 and 21-26 are rejected under 35 U.S.C. 102(a)(1)/ (a)(2) as being anticipated by Wang et al. (US20200135932A1).
Regarding claim 1, Fig.3B and 9A-9C of Wang teaches a method for forming a semiconductor structure, comprising:
forming a fin structure 204 (Fig.2A, para.0020) protruding from a substrate 202 (para.0017), wherein the fin structure 204 comprises
first semiconductor material layers 204B (Fig.2A, para.0022) and second semiconductor material layers 204A (Fig.2A, para.0022) alternately stacked;
forming a spacer layer 214 (Fig.3C, para.0025) over the fin structure 204;
forming a first inter-layer dielectric (ILD) layer 206 (Fig.3C, para.0029) over the spacer layer 214;
recessing the fin structure 204 (para.0031) and the first ILD layer 206 to form a first opening 230 (Fig.4C, para.0031) through the first ILD layer 206;
forming an epitaxial structure 250 (Fig.5C, para.0034) in the first opening 230;
forming a second ILD layer 266 (Fig.9B, para.0040) over the epitaxial structure 250 and the first ILD layer 206; removing the first semiconductor material layers 204B (para.0032); and
forming a gate structure 270 (Fig.9B, para.0043) around the second semiconductor material layers 204A.
Regarding claim 2, Wang teaches the method as claimed in claim 1, further comprising:
forming a second opening 265 (Fig.10C, para.0044) through the second ILD layer 266 (Fig.9C, para.0040) to expose the epitaxial structure 250 (Fig.5C, para.0034); and
forming a contact 290 (Fig.12C, para.0048) in the second opening 265 over the epitaxial structure 250.
Regarding claim 3, Wang teaches the method as claimed in claim 2, further comprising:
forming a contact spacer 264 (Fig.9C, para.0047) on a sidewall of the second opening 265 (para.0044) before forming the contact 290 (para.0048).
Regarding claim 4, Wang teaches the method as claimed in claim 3, wherein the contact spacer 264 (para.0047) is in direct contact with the first ILD layer 206 (Fig.3C, para.0029).
Regarding claim 9, Wang teaches the method as claimed in claim 1, further comprising forming an air spacer 268 (Fig.10C, para.0045) between the epitaxial structure 250 (Fig.5C, para.0034) and the spacer layer 214 (para.0025).
Regarding claim 11, Fig.3B and 9A-9C of Wang teaches a method for forming a semiconductor structure, comprising:
forming a plurality of fin structures 204 (Fig.2A, para.0020) protruding from a substrate 202 (para.0017), wherein each of the fin structures 204 comprises first semiconductor material layers 204B (Fig.2A, para.0022) and second semiconductor material layers 204A (Fig.2A, para.0022) alternately stacked;
forming a spacer layer 220 (Fig.3C, para.0029) over the fin structures 204;
forming a contact etch stop layer 264 (Fig.9B, para.0039) and an inter-layer dielectric (ILD) layer 266 (Fig.9B, para.0040) over the spacer layer 220;
etching the ILD layer 266 (Fig.9B, para.0044), the contact etch stop layer 264 and the spacer layer 220 to form a plurality of openings 265 (Fig.10C, para.0044) through the ILD layer 266 and the contact etch stop layer 264;
removing the first semiconductor material layers 204B and second semiconductor material layers 204A exposed in the openings 265;
forming an epitaxial structure 250 (Fig.5C, para.0034) in each of the openings 230 (Fig.4C, para.0031) and over each of the fin structures 204;
removing the first semiconductor material layers 204B (para.0043); and
forming a gate structure 270 (Fig.9B, para.0043) around the second semiconductor material layers 204A (para.0043).
Regarding claim 12, Wang further teaches the method as claimed in claim 11, further comprising:
forming an isolation structure 208 (Fig.4C, para.0046) between the fin structures 204 (para.0020), wherein a height difference between a bottom surface of the epitaxial structures 250 (Fig.5C, para.0034) and a top surface of the isolation structure 208 is greater than 0 and less than about 20 nm.
Regarding claim 13, Wang further teaches the method as claimed in claim 11, wherein a thickness of the spacer layer 220 (Fig.3C, para.0029) is not less than a thickness of the contact etch stop layer 264 (para.0039).
Regarding claim 14, Wang further teaches the method as claimed in claim 11, further comprising: forming a contact 290 (para.0046) electrically and physically connected to adjacent two of the epitaxial structures 250 (para.0034).
Regarding claim 21, Fig.3B and 9A-9C of Wang teaches a method for forming a semiconductor structure, comprising:
forming a fin structure 204 (Fig.2A, para.0020) over a substrate 202 (Fig.2A, para.0017);
forming a spacer layer 214 (Fig.3C, para.0025) formed over the fin structure 204;
forming a gate structure 270 (Fig.9B, para.0043) within the spacer layer 214;
forming an epitaxial structure 250 (Fig.5C, para.0034) over the fin structure 204 and along an inner surface of the spacer layer, wherein forming the epitaxial structure 250 comprises etching the fin structure 204 (para.0031) and the spacer layer 222 (para.0045); and
forming a contact etch stop layer 264 (Fig.9B, para.0039) on the inner surface of the spacer layer 214 and an upper surface of the epitaxial structure 250.
Regarding claim 22, Wang further teaches the method as claimed in claim 21, further comprising:
etching the contact etch stop layer 264 (para.0039);
forming a silicide layer 280 (para.0047) on the upper surface of the epitaxial structure 250 (para.0047); and
forming a contact 290 (para.0046) over the silicide layer 280, wherein the contact 290 extends lower than a bottom surface of the silicide layer 280.
Regarding claim 23, Wang further teaches the method as claimed in claim 22, further comprising:
forming a contact spacer 220 (para.0029) around the contact 290 (para.0046), wherein the contact spacer 220 vertically overlaps the contact etch stop layer 264 (para.0039).
Regarding claim 24, Wang further teaches the method as claimed in claim 23, further comprising: forming an air spacer 268 (para.0045) sealed by the contact spacer 220 (para.0029), the epitaxial structure 250 (para.0034) and the spacer layer 222 (para.0045).
Regarding claim 25, Wang further teaches the method as claimed in claim 21, further comprising:
forming an isolation structure 208 (para.0046) around the fin structure 204 (para.0031), wherein the contact 290 (para.0046) comes into physically contact 290 with a top surface of the isolation structure 208.
Regarding claim 26, Wang further teaches the method as claimed in claim 21, wherein forming the epitaxial structure 250 (para.0034) further comprises:
forming a sidewall 280 (para.0047) of the epitaxial structure 250 protruding from a sidewall of the fin structure 204 (para.0031), wherein a gap 268 (para.0045) is formed between the sidewall of the epitaxial structure 250 and the inner surface of the spacer layer.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US20200135932A1) in view of Wang et al. (US20190164966A1; hereafter Wang’966).
Regarding claim 5, Wang does not teach forming a first contact etch stop layer over the spacer layer before forming the first ILD layer; and
forming a second contact etch stop layer over the over the epitaxial structure before forming the second ILD layer.
Wang’966, in Fig.6 and Fig.14, teaches forming a first contact etch stop layer 610 (para.0025) over the spacer layer 310 (para.0025) before forming the first ILD layer 620 (para.0026); and
forming a second contact etch stop layer 1410 (para.0037) over the over the epitaxial structure 420 (para.0021) before forming the second ILD layer 1420 (para.0038).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the second contact etch stop layer of Wang’966 in the teachings of Wang in order to prevent epitaxial features 250 from getting etched.
Regarding claim 7, Fig.3C of Wang teaches the method as claimed in claim 5, wherein recessing (para.0052, forming a recess in the semiconductor) the fin structure 204 (para.0020) comprises removing a portion of the first contact etch stop layer and a portion of the spacer layer 222 (para.0038).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US20200135932A1) in view of Wang et al. (US20190164966A1; hereafter Wang’966) and in further view of Tsai et al. (US9443757B1).
Regarding claim 6, Wang does not teach wherein forming the second contact etch stop layer comprises forming the second contact etch stop layer lower than a top surface of the first contact etch stop layer.
Tsai teaches, in Fig.3, wherein a fin-shaped structure 14 on the substrate 12, an epitaxial layer 32 on the fin-shaped structure 14, a spacer 26 adjacent to the epitaxial layer 32 and fin-shaped structure 14, a cap layer 34 on the epitaxial layer 32, spacer 26, and STI 16, a first CESL 36 on the cap layer 34, a cap layer 38 on the first CESL 36, a second CESL 42 on the cap layer 38, and a cap layer 44 on the second CESL 42. The first CESL 36 (the second contact etch stop layer) is formed lower than the second CESL 42 (the first contact etch stop layer).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the second contact etch stop layer lower than a top surface of the first contact etch stop layer as taught by Tsai because the first CESL 36 and second CESL 42 could have different stress depending on the demand of the product. (Tsai, [col.4, lines 1-3]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US20200135932A1) in view of Huang’s et al. (US20190371898A1).
Regarding claim 8, Wang does not teach wherein forming the epitaxial structure in the opening comprises forming the epitaxial structure having a height of about 30 nm to about 70 nm.
Fig.3A of Huang teaches the epitaxial source/drain regions are formed where portions of fin 274 were removed and wherein the cross-sectional area of the epitaxial source/drain regions along A-A line may have a height 292h that ranges from 40nm and 50nm. (Huang, [para.0029]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the height of Huang’s epitaxial source/drain regions in the teachings of Wang in order to allow enough room for forming recesses that can have increased contact area between the source/drain region and the conductive feature, and can enable reduced resistance therebetween. (Huang, [para.0012]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US20200135932A1) in view of Xiao et al. (US20170110580A1).
Regarding claim 10, Wang teaches the method as claimed in claim 1, further comprising:
Wang does not teach performing a gas treatment prior to forming the epitaxial structure, wherein the gas treatment comprises introducing a gas into the opening, and the gas comprises Si(CH3)4.
Xiao teaches, in paragraph 0043, wherein silicon-germanium (SiGe) 610 is formed in the source-drain trench in the PMOS device region 110 as a source-drain epitaxial material, in which the reactant gas for forming SiGe 610 is the mixed gas of germane (GeH.sub.4) and more than one of silane (SiH.sub.4), disilane (Si.sub.2H.sub.6), dichlorosilane (SiH.sub.2Cl.sub.2), trichlorosilane (SiHCl.sub.3), tetrachlorosilane (SiCl.sub.4) and tetramethylsilane (Si(CH.sub.3).sub.4). (Xiao, [para.0043])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Xiao’s tetramethylsilane (Si(CH.sub.3).sub.4) as part of the reactant gas for forming a silicon-germanium (SiGe) 610 in the teachings of Wang in order to act as a precursor that provides silicon.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT KIPKEMOI RONO whose telephone number is (571)270-5977. The examiner can normally be reached Mon-Fri, 8am-5pm.
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VINCENT KIPKEMOI. RONO
Examiner
Art Unit 2891
/V.K.R./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
Prosecution Insights