DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, line 8 recites “surrounding a portion of the isolation”. It is unclear which portion the claim refers to since line 7 of the claim recites “a first portion and a second portion”.
Claim 4, line 2 recites “the portion of the isolation”. It is unclear which portion the claim refers to, since claim 1 recites “a first portion and a second portion” in line 7, and “a portion” in line 8.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-12, 14, and 21-26, as best understood, are rejected under 35 U.S.C. 103 as being unpatentable over Sharma et al. in US 2023/0008261 A1 (hereinafter Sharma).
Regarding claim 1, Sharma teaches in the embodiment of FIG. 3A and related text, a memory structure (300, [0037]), comprising:
a gate structure (304, [0039]), disposed over a substrate (302, [0038]);
a ferroelectric material (312, [0039]/[0045]), disposed over the gate structure (304);
a source structure (308/310, [0039], see annotated FIG. 3A below) and a drain structure (308/310, [0039], see annotated FIG. 3A below), respectively disposed above the ferroelectric material (312);
an isolation (314, [0039]), surrounding the source structure (308/310) and the drain structure (308/310) and comprising a first portion and a second portion (annotated FIG. 3A); and
an oxide semiconductor (306, [0039]/[0041]), surrounding a portion of the isolation (314) between the source structure (308/310) and the drain structure (308/310), wherein a top surface of a middle portion of the oxide semiconductor (306) is in contact with the bottom surface of the first portion (annotated FIG. 3A), and the top surface of the middle portion of the oxide semiconductor (306) is substantially aligned with the bottom surface of the source structure (bottom surface of 300).
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Annotated FIG. 3A (Sharma)
Sharma does not teach in the embodiment of FIG. 3A that the source structure and drain structure are in contact with the ferroelectric layer.
However, Sharma teaches in the embodiment of FIG. 4A that the source structure (308/310 on left) and drain structure (308/310 on right) are in contact with the ferroelectric layer (312). Sharma additionally teaches source/drain regions 308 of source/drain structures 308/310 may be formed by etching the oxide semiconductor (channel) layer 306 and epitaxially depositing a source/drain material ([0043]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device in FIG. 3A of Sharma such that the source structure and drain structure are in contact with the ferroelectric layer, as taught by Sharma in the embodiment of FIG. 4A, since the embodiment of FIG. 4A teaches this is well-known alternative method of forming an equally reliable source and drain structure.
Regarding claim 2, Sharma teaches the memory structure of claim 1. Sharma does not teach in FIG. 3A wherein the memory structure is disposed in an interconnect structure vertically overlapping a logic device.
However, Sharma teaches in FIG. 11 a memory structure (transistor 2140 may include the materials in memory structure 300, [0087]/[0088]/[0092]) is disposed in an interconnect structure (2106-2110, [0093]) vertically overlapping a logic device (2140).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sharma’s memory structure in FIG. 3 such that the memory structure is disposed in an interconnect structure vertically overlapping a logic device, as taught by FIG. 11, with the purpose of routing electrical signals to and/or from transistors to other device components ([0093]-[0094]).
Regarding claim 3, Sharma teaches the memory structure of claim 1. Sharma does not explicitly state in the embodiment of FIG. 3A wherein a thickness of a horizontal portion of the oxide semiconductor (306) is the same as a thickness of a vertical portion of the oxide semiconductor (306).
However, Sharma appears to teach in FIG. 3a wherein a thickness of a horizontal portion of the oxide semiconductor (316-3, [0049]) is the same as a thickness of a vertical portion of the oxide semiconductor (316-2, [0049]). Additionally, Sharma teaches the oxide semiconductor (306) may be conformal to the shape of the ferroelectric layer ([0050]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a thickness of a horizontal portion of the oxide semiconductor be the same as a thickness of a vertical portion of the oxide semiconductor, as taught by Sharma, in order to simplify the manufacturing process. Although the drawings are not to scale, they may be relied upon for what they would reasonably teach one of ordinary skill in the art when interpreted in view of the specification. (MPEP 2125(II); In re Wright, 569 F.2d 1124, 1127-28, 193 USPQ 332, 335-36 (CCPA 1977)).
Regarding claim 4, Sharma teaches the memory structure of claim 1, wherein a bottom surface of the portion of the isolation (see annotated FIG. 3A in rejection of claim 1) is respectively coplanar with a bottom surface of the source structure (308/310) and a bottom surface of the drain structure (308/310).
Regarding claim 5, Sharma teaches the memory structure of claim 1, wherein a portion of the oxide semiconductor (316-1, 316-2, 316-3, [0049]) is embedded within the ferroelectric material (312; embedded can mean to fix firmly or deeply within a surrounding mass; 316-1, 316-2, 316-3 are fixed firmly within the surrounding trench/mass formed by 312).
Regarding claim 6, Sharma teaches the memory structure of claim 1, wherein the oxide semiconductor (306) is in physical contact with the ferroelectric material (312).
Regarding claim 7, Sharma teaches in FIGS. 2, 3A and related text, a semiconductor structure (300, [0037]), comprising:
a first channel layer (306, [0039]) surrounding a first portion of a dielectric layer (314, [0039]/[0048], see annotated FIG. 3A below) disposed between a first source line (SL1/308/310, [0035]/[0039], noting 310 in FIG. 3A is coupled to SL1 in FIG. 2, [0044]/[0035]) and a first bit line (BL1/308/310, [0035]/[0039], noting 310 in FIG. 3A is coupled to BL1 in FIG. 2, [0044]/[0035]);
a ferroelectric layer (312, [0039]/[0045]), overlapped by the first channel layer (306), the first source line (SL1/310) and the first bit line (BL1/310), wherein the first source line (SL1/308/310) and the first bit line (BL1/308/310) are respectively disposed above the ferroelectric layer (312); and
a first word line (WL1/304, [0035]/[0039], noting 304 in FIG. 3A is coupled to WL1 in FIG. 2, [0044]/[0035]), disposed below the first ferroelectric layer (312), wherein a top surface of a middle portion of the first channel layer is in contact with the bottom surface of the dielectric layer, and the top surface of the middle portion of the first channel layer is substantially aligned with the bottom surface of the first source line.
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Annotated FIG. 3A (Sharma)
Sharma does not teach in the embodiment of FIG. 3A that the first source line and the first bit line are in contact with the ferroelectric layer.
However, Sharma teaches in the embodiment of FIG. 4A that the first source line (SL1/308/310 on left) and first bit line (BL1/308/310 on right) are in contact with the ferroelectric layer (312). Sharma additionally teaches source/drain regions 308 of source/drain structures 308/310 may be formed by etching the oxide semiconductor (channel) layer 306 and epitaxially depositing a source/drain material ([0043]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device in FIG. 3A of Sharma such that the first source line and the first bit line are in contact with the ferroelectric layer, as taught by Sharma in the embodiment of FIG. 4A, since the embodiment of FIG. 4A teaches this is well-known alternative method of forming an equally reliable source and drain structure.
Regarding claim 8, Sharma teaches the semiconductor structure of claim 7, wherein the first word line (WL1/304) is overlapped by the first source line (SL1/310) and the first bit line (BL1/310).
Regarding claim 9, Sharma teaches the semiconductor structure of claim 7, wherein the first channel layer (306, FIG. 3A) encircles the first portion of the dielectric layer (314) from a top-view perspective (FIG. 3B; to encircle can mean to surround, and 306 at least partially surrounds the first portion of 314 in FIG. 3B).
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Regarding claim 10, Sharma teaches the semiconductor structure of claim 7. Sharma further teaches in FIG. 2, a second source line (SL2, [0035]), a second bit line (BL2, [0035]), and a second word line (WL2, [0035]).
Sharma does not teach in FIG. 3A a second channel layer surrounding a second portion of the dielectric layer disposed between a second source line and a second bit line, wherein the second channel layer, the second source line and the second bit line vertically overlap the ferroelectric layer; and a second word line, overlapped by the second source line and the second bit line.
However, Sharma teaches in [0039] that the IC device 300 of FIG. 3A corresponds to the transistor 110 in FIG. 1. Sharma further teaches a plurality of transistors in FIG. 2 ([0035]), each transistor connected to lines SL1/BL1/WL1, SL2/BL2/WL2, etc.
It would therefore have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the device of Sharma further comprise a second channel layer surrounding a second portion of the dielectric layer disposed between a second source line and a second bit line, wherein the second channel layer, the second source line and the second bit line vertically overlap the ferroelectric layer; and a second word line, overlapped by the second source line and the second bit line, as taught by Sharma in FIGS. 1, 2 and 3A, in order to provide a plurality of memory cells that function as a memory device (Sharma, [0034]).
Regarding claim 11, Sharma teaches the semiconductor structure of claim 10. Sharma further teaches wherein a portion of the first channel layer (316-1, 316-2, 316-3, [0049]) is embedded with the ferroelectric layer (312; embedded can mean to fix firmly or deeply within a surrounding mass; 316-1, 316-2, 316-3 are fixed firmly within the surrounding trench/mass formed by 312).
Regarding claim 12, Sharma teaches the semiconductor structure of claim 7. Sharma does not explicitly teach wherein a thickness of the first channel layer (306) is in a range of 1 to 50 nanometers, and a thickness of the ferroelectric layer (312) is in a range of 1 to 50 nanometers.
However, Sharma teaches wherein a thickness of the first channel layer (306) is in a range of 1 to 75 nanometers [0041], and a thickness of the ferroelectric layer (312) is in a range of 0.5 to 15 nanometers [0045].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first channel layer and ferroelectric layer such that a thickness of the first channel layer is in a range of 1 to 50 nanometers, and a thickness of the ferroelectric layer is in a range of 1 to 50 nanometers, in order to optimize the FE or AFE properties of the device (Sharma, [0045]), since in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)).
Regarding claim 14, Sharma teaches the semiconductor structure of claim 7, wherein a bottom surface of the first portion of the dielectric layer (314, see annotated FIG 3A in the rejection of claim 7) is respectively coplanar with a bottom surface of the first source line (SL1/310) and a bottom surface of the first bit line (BL1/310).
Regarding claim 21, Sharma teaches in FIG. 3A and related text, a memory structure (300, [0037]), comprising:
a gate structure (304, [0039]), disposed over a substrate (302, [0038]);
a ferroelectric material (312, [0039]/[0045]), disposed over the gate structure ([304]);
a source structure (308/310, [0039], see annotated FIG. 3A in the rejection of claim 1) and a drain structure (308/310, [0039], annotated FIG. 3A), respectively disposed above the ferroelectric material (312);
an isolation (314, [0039]), surrounding the source structure (308/310) and the drain structure (308/310), wherein the isolation (314) comprises a first portion and a second portion (annotated FIG. 3A); and
an oxide semiconductor (306, [0039]/[0041]), surrounding the first portion (annotated FIG. 3A) between the source structure (308/310) and the drain structure (308/310), wherein a bottom surface of the first portion (annotated FIG. 3A) is respectively coplanar with a bottom surface of the source structure (308/310) and a bottom surface of the drain structure (308/310), wherein a top surface of a middle portion of the oxide semiconductor (306) is in contact with the bottom surface of the first portion (annotated FIG. 3A), and the top surface of the middle portion of the oxide semiconductor (306) is substantially aligned with the bottom surface of the source structure (bottom surface of 310, annotated FIG. 3A).
Sharma does not teach in the embodiment of FIG. 3A that the source structure and drain structure are in contact with the ferroelectric layer.
However, Sharma teaches in the embodiment of FIG. 4A that the source structure (308/310 on left) and drain structure (308/310 on right) are in contact with the ferroelectric layer (312). Sharma additionally teaches source/drain regions 308 of source/drain structures 308/310 may be formed by etching the oxide semiconductor (channel) layer 306 and epitaxially depositing a source/drain material ([0043]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device in FIG. 3A of Sharma such that the source structure and drain structure are in contact with the ferroelectric layer, as taught by Sharma in the embodiment of FIG. 4A, since the embodiment of FIG. 4A teaches this is well-known alternative method of forming an equally reliable source and drain structure.
Regarding claim 22, Sharma teaches the memory structure of claim 21, wherein a portion of the oxide semiconductor (316-1, 316-2, and 316-3, [0049]) is recessed below the bottom surface of source structure (308/310) and the bottom surface of a drain structure (308/310).
Regarding claim 23, Sharma teaches the memory structure of claim 22, wherein the portion of the oxide semiconductor (316-1, 316-2, and 316-3) is embedded within the ferroelectric material (312; embedded can mean to fix firmly or deeply within a surrounding mass; 316-1, 316-2, 316-3 are fixed firmly within the surrounding trench/mass formed by 312).
Regarding claim 24, Sharma teaches the memory structure of claim 21, wherein a material of the oxide semiconductor (306) includes one of indium zinc oxide (IZO), indium tin oxide (ITO), indium oxide (In2O3), gallium oxide (Ga2O3), indium gallium zinc oxide (InGaZnO), zinc oxide (ZnO), aluminum zinc oxide (A1205Zn2), aluminum doped zinc oxide (AZO), indium tungsten oxide (IWO), titanium oxide (TiOx), or a combination thereof ([0041]).
Regarding claim 25, Sharma discloses the memory structure of claim 21, wherein a material of the first portion (the silicon material of silicon oxide, 314, annotated FIG. 3A, [0048]) is different than a material of the second portion (the oxygen material of silicon oxide, 314, annotated FIG. 3A, [0048]).
Regarding claim 26, Sharma teaches the memory structure of claim 21. Sharma does not teach in the embodiment of FIG. 3A wherein the memory structure is disposed in an interconnect structure vertically overlapping a logic device.
However, Sharma teaches in FIG. 11 a memory structure (transistor 2140 may include the materials in memory structure 300, [0087]/[0088]/[0092]) is disposed in an interconnect structure (2106-2110, [0093]) vertically overlapping a logic device (2140).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sharma’s memory structure in FIG. 3 such that the memory structure is disposed in an interconnect structure vertically overlapping a logic device, as taught by FIG. 11, with the purpose of routing electrical signals to and/or from transistors to other device components ([0093]-[0094]).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Sharma et al. in US 2023/0008261 A1 (hereinafter Sharma) in view of Kobayashi in US 2022/0157833 A1 (hereinafter Kobayashi).
Regarding claim 13, Sharma teaches substantially the entire claimed semiconductor structure of claim 7. Sharma does not explicitly state wherein a distance between the first source line (SL1/310) and the first bit line (BL1/310) is in a range of 10 to 100 nanometers. Sharma is silent regarding the dimension of this distance (332 in FIG. 3A, [0054]).
Kobayashi teaches in FIGS. 16-19 and related text, a distance between a first source line (170, [0047]) and a first bit line (180, [0047]) is in a range of 50 to 1000 nanometers ([0096], [0102]), in order to improve the width of a memory window in a ferroelectric field-effect transistor ([0098]).
Sharma and Kobayashi are analogous art to the claimed invention because they are directed to ferroelectric field-effect transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Sharma in view of Kobayashi because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Sharma such that a distance between the first source line and the first bit line is in a range of 10 to 100 nanometers, as taught by Kobayashi with the purpose of improving the width of a memory window in a ferroelectric field-effect transistor (Kobayashi, [0098]). This benefits the device of Sharma, as Sharma is also concerned with the size of the memory window (Sharma, [0019]). Kobayashi’s range overlap’s the range of the claim, but in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)).
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2020/0098887 A1 teaches a bottom-gate transistor including an oxide semiconductor surrounding a portion of an isolation between a source and a drain.
Response to Arguments
Applicant’s remarks on page 1 regarding the status of the claims in the reply filed on 09/12/2025 are acknowledged.
Applicant’s remarks regarding claim objections for minor informalities made in the Non-Final Office Action mailed on 06/16/2025 (hereinafter previous Office Action) are acknowledged. In response, the amendments to claims 2, 10, 25 and 26 in the Instant Application remedy the minor informalities and overcome the objections.
Applicant’s arguments on pages 1-2 regarding rejections made under 35 USC 112 in the previous Office Action are acknowledged. Applicant has amended claims 21-24 to overcome the rejections.
In response, the Examiner finds the amendments sufficient to overcome the 112 rejections. However, the Examiner notes additional 112(b) rejections in the Instant Office Action in light of Applicant’s amendments.
Applicant’s arguments on pages 2-5 regarding the rejections made under 35 USC 102 and 103 are acknowledged. Applicant specifically argues on pages 2-3 that FIG. 3A of Sharma does not teach the features “a source structure and a drain structure, respectively disposed above and in contact with the ferroelectric material”.
In response, the Examiner notes although FIG. 3A of Sharma appears to show the source/drain region 308 not in contact with ferroelectric layer 312, Sharma teaches an embodiment (FIG. 4A) in which the source/drain region 308 is in contact with ferroelectric layer 312. Additionally, Sharma teaches the source/drain region 308 may be formed by etching the oxide semiconductor (channel) layer 306 and epitaxially depositing a source/drain material ([0043]). It would have therefore been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device in FIG. 3A of Sharma such that the source structure and drain structure are in contact with the ferroelectric layer, as taught by Sharma in the embodiment of FIG. 4A, in order to simplify the manufacturing process.
Applicant argues on page 3 Sharma does not disclose the features “wherein a top surface of a middle portion of the oxide semiconductor is in contact with the bottom surface of the first portion, and the top surface of the middle portion of the oxide semiconductor is substantially aligned with the bottom surface of the source structure”.
In response, the Examiner finds this argument non persuasive as explained in the Instant Office Action (see, e.g., annotated FIG. 3A in the rejection of claim 1). The claim does not require “the bottom surface of the first portion” to be the bottommost surface, for example.
Applicant’s arguments on pages 4-5 regarding independent claims 7 and 21 mirror the arguments made with respect to independent claim 1. The Examiner’s response to those arguments are the same as noted in the preceding paragraphs.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEPHEN LEE JOHNSON JR whose telephone number is (571)270-3217. The examiner can normally be reached Mon-Fri: 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at (571)272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S.L.J./ Examiner, Art Unit 2811
/LYNNE A GURLEY/ Supervisory Patent Examiner, Art Unit 2811