Prosecution Insights
Last updated: April 19, 2026
Application No. 18/153,553

BARRIER LAYER FOR WEAKENED BOUNDARY EFFECT

Non-Final OA §102§103
Filed
Jan 12, 2023
Examiner
ENAD, CHRISTINE A
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
2y 1m
To Grant
94%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allow Rate
1105 granted / 1312 resolved
+16.2% vs TC avg
Moderate +10% lift
Without
With
+10.1%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
68 currently pending
Career history
1380
Total Applications
across all art units

Statute-Specific Performance

§101
1.5%
-38.5% vs TC avg
§103
61.5%
+21.5% vs TC avg
§102
21.1%
-18.9% vs TC avg
§112
7.7%
-32.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1312 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Invention I in the reply filed on 11/26/2025 is acknowledged. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 21-25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by More et al (US Publication No. 2021/0407862). Regarding claim 21, More discloses a method comprising: providing a substrate Fig 2, 50 comprising an N-type structure, a P-type structure, and a boundary region between the N-type structure and the P-type structure Fig 24-25 ¶0028;depositing a high-K dielectric layer Fig 17, 116 over the N-type structure, the P-type structure, and the boundary region¶0057;forming a first metal layer Fig 17, 118 over the high-K dielectric layer Fig 17, 116 in the boundary region Fig 17;depositing a second metal layer Fig 18, 120 over the N-type structure, the P-type structure, and the boundary region Fig 18; removing the second metal layer from over the N-type structure while retaining the second metal layer in the boundary region ¶0058-0061; and depositing a third metal layer Fig 21, 128 over the N-type structure, the P-type structure, and the boundary region Fig 21; wherein a barrier structure is formed in the boundary region comprising the first metal layer, the second metal layer, and the third metal layer Fig 24-25. Regarding claim 22, More discloses wherein the first metal layer has a dimension a that is greater than 0 nm (nanometer) and less than 70 nm (0 < a < 70 nm) in the barrier structure ¶0057-0058 Fig 19 and Fig 24-25. Regarding claim 23, More discloses wherein the second metal layer has a dimension b that is greater than 0 nm (nanometer) and less than 70 nm (0 < b < 70 nm) between an edge of the barrier structure to an edge of the second metal layer on a sidewall of the P-type structure ¶0058-0059 Fig 19 and Fig 24-25. Regarding claim 24, More discloses wherein the third metal layer has a dimension c that is greater than 0 nm (nanometer) and less than 70 nm (0 < c < 70 nm) between an edge of the barrier structure to an edge of the third metal layer on a sidewall of the N-type structure ¶0072 Fig 19 and Fig 24-25. Regarding claim 25, More discloses wherein the dimension b plus the dimension c is less than 70 nm (b + c < 70 nm) ¶0057-0058, 0072. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 26-28 are rejected under 35 U.S.C. 103 as being unpatentable over More et al (US Publication No. 2021/0407862). Regarding claims 26-27, More discloses wherein a first line segment extends from a boundary point that is between the N-type structure and the P-type structure and extends to a bottom edge of the third metal layer in the barrier structure Fig 19 and Fig 24-25, and wherein an angle d between the first line segment and a bottom of the third metal layer in the barrier structure Fig 19 and Fig 24-25. More discloses all the limitations but silent on the optimum range. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the angle, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (1955). it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F. 2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F .2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F .2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F .2d 669, 149 USPQ 47 (CCPA 1966). Regarding claim 28, More discloses wherein forming the first metal layer over the high-K dielectric layer in the boundary region comprises: depositing the first metal layer over the N-type structure and the P-type structure ¶0057 Fig 17; patterning a first photolithographic layer over the first metal layer that exposes the first metal layer over the P-type structure up to a first predetermined distance to a boundary between the N-type structure and the P-type structure¶0057 Fig 17;removing the first metal layer exposed by the first photolithographic layer Fig 17;depositing a second metal layer over the N-type structure and the P-type structure Fig 18;patterning a second patterned photolithographic layer over the second metal layer that exposes the second metal layer over the N-type structure up to a second predetermined distance to the boundary between the N-type structure and the P-type structure ¶0059-0065 Fig 20; and removing the second metal layer exposed by the second patterned photolithographic layer and the first metal layer underlying the second metal layer exposed by the second patterned photolithographic layer¶0059-0065 Fig 20. Allowable Subject Matter Claims 1-9, 18-20 are allowed over the prior art of record. The following is a statement of reasons for the indication of allowable subject matter: After further search and consideration, it is determined that the prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach or suggest “forming a second patterned photolithographic layer over the second metal layer with an opening that exposes a portion of the second metal layer over the second semiconductor structure but not completely to a boundary between the first semiconductor structure and the second semiconductor structure; removing the portion of the second metal layer and underlying portions of the first metal layer that is over the second semiconductor structure; wherein a barrier structure is generated between the first semiconductor structure and the second semiconductor structure that includes remaining portions of the first metal layer and a portion of the second metal layer overlying the remaining portions of the first metal layer; removing the second patterned photolithographic layer”, as recited in independent claim 1 and “forming a second patterned photolithographic layer over the second metal layer using a patterning rule that exposes a portion of the second metal layer over the second semiconductor structure up to a second predetermined distance to a boundary between the first semiconductor structure and the second semiconductor structure; removing the portion of the second metal layer, underlying portions of the first metal layer that is over the second semiconductor structure, and the second patterned photolithographic layer; wherein a barrier structure is generated between the first semiconductor structure and the second semiconductor structure that includes remaining portions of the first metal layer and a portion of the second metal layer overlying the remaining portions of the first metal layer”, as recited in independent claim 18. Claims 2-9, 19-20 are also allowed as being directly or indirectly dependent of the allowed independent base claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTINE A ENAD whose telephone number is (571)270-7891. The examiner can normally be reached Monday-Friday, 7:30 am -4:30 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571 272 1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTINE A ENAD/Primary Examiner, Art Unit 2811
Read full office action

Prosecution Timeline

Jan 12, 2023
Application Filed
Feb 03, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
94%
With Interview (+10.1%)
2y 1m
Median Time to Grant
Low
PTA Risk
Based on 1312 resolved cases by this examiner. Grant probability derived from career allow rate.

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