DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
1. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/24/2026 has been entered.
Status of the Application
2. Acknowledgement is made of the amendment received on 3/12/2026. Claims 1-16 & 21-24 are pending in this application. Claims 17-20 are canceled.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 10-15 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2020/0343362) in view of Julien et al. (US 2022/0139782).
Re claim 10, Wu teaches, under BRI, Figs. 1A-1K, [0017, 0023, 0024, 0039-0041, 0045, 0062], a method comprising:
-forming a gate structure (106, 108) over a portion of a semiconductor structure (102) extending from a substrate (100), wherein the gate structure includes a dummy gate (106, 108) and gate spacers (110), wherein the dummy gate (106, 108) has a gate height (H2) above the semiconductor structure (102) (Fig. 1C);
-recessing a dummy gate electrode (108) of the dummy gate to form a gate opening (118) having a depth (H1) that is less than the gate height (H2), wherein the gate opening (118) that exposes portions of the gate spacers (110) at least above a top surface of the semiconductor structure (102);
-performing a treatment process on the gate spacers (110) (e.g., using plasma), wherein the treatment process changes a composition of treated portions of the exposed portions of the gate spacers (110) to enable selective etching of the treated portions of the exposed portions of the gate spacers (110) with respect to non-treated portions of the gate spacers (110) (Figs. 1D-E);
-selectively etching the treated portions of the exposed portions of the gate spacers (110) to enlarge the gate opening (form 118’);
-removing a remainder of the dummy gate electrode (108) and a dummy gate dielectric (106) of the dummy gate (106, 108) to further enlarge the gate opening (118’) and expose the semiconductor structure (102) (Fig. 1E-I); and
-forming a gate stack (126, 128, 130) that fills the enlarged gate opening (Fig. 1J).
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Wu does not explicitly teach performing the treatment process on the gate spacers without etching the gate spacers; and after performing the treatment process, selectively etching the treated portion of exposed portions of the gate spacers.
Julien teaches, Figs. 1-2, [0024, 0061-0063], performing the treatment process (e.g., to modify etching rate of spacer prior to the wet etching) on the gate spacers (SP) without etching the gate spacers (SP); and after performing the treatment process, selectively etching (e.g. wet etch) the treated portion of exposed portions of the gate spacers (SP).
As taught by Julien, one of ordinary skill in the art would utilize & modify the above teaching into Wu to obtain steps of performing the treatment process on the gate spacers without etching the gate spacers; and after performing the treatment process, selectively etching the treated portion of exposed portions of the gate spacers as claimed, because it aids in precisely controlling/removing desired to-be etched portions of the spacer without damaging the substrate & underlying structures.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Julien in combination Wu due to above reason.
Re claim 11, Wu teaches, under BRI, the treatment process is an O2 oxygen plasma treatment and the treated portions are silicon oxide portion of the gate spacers (110) [0029, 0045].
Re claim 13, Wu teaches, Figs. 1D-E, the gate spacers (110) include inner spacers (in 118) and outer spacers (covered by 114) and the treatment process performed on the inner spacers.
Re claim 14, Wu teaches, Fig. 1E, the recessing of the dummy gate electrode (108) of the dummy gate and the treatment process are tuned to provide the enlarged gate opening (118’) with a funnel-shaped profile.
Re claim 15, Wu teaches, under BRI, Figs. 1D-E, including configuring the treatment process to control (as intended use or base on similar teaching) a profile of the treated portions of the exposed portions of the gate spacers (110), such that the gate opening (118) is provided with a minimum width and a maximum width after removing the treated portions of the exposed portions of the gate spacers (110) (change to 118’), wherein a ratio of the maximum width to the minimum width is greater than 1 and at most 1.5.
4. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2020/0343362) in view of Kang et al. (US 2018/0323276).
Re claim 10, Wu teaches, under BRI, Figs. 1A-1K, [0017, 0023, 0024, 0039-0041, 0045, 0062], a method comprising:
-forming a gate structure (106, 108) over a portion of a semiconductor structure (102) extending from a substrate (100), wherein the gate structure includes a dummy gate (106, 108) and gate spacers (110), wherein the dummy gate (106, 108) has a gate height (H2) above the semiconductor structure (102) (Fig. 1C);
-recessing a dummy gate electrode (108) of the dummy gate to form a gate opening (118) having a depth (H1) that is less than the gate height (H2), wherein the gate opening (118) that exposes portions of the gate spacers (110) at least above a top surface of the semiconductor structure (102);
-performing a treatment process on the gate spacers (110) (e.g., using plasma), wherein the treatment process changes a composition of treated portions of the exposed portions of the gate spacers (110) to enable selective etching of the treated portions of the exposed portions of the gate spacers (110) with respect to non-treated portions of the gate spacers (110) (Figs. 1D-E);
-selectively etching the treated portions of the exposed portions of the gate spacers (110) to enlarge the gate opening (form 118’);
-removing a remainder of the dummy gate electrode (108) and a dummy gate dielectric (106) of the dummy gate (106, 108) to further enlarge the gate opening (118’) and expose the semiconductor structure (102) (Fig. 1E-I); and
-forming a gate stack (126, 128, 130) that fills the enlarged gate opening (Fig. 1J).
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Wu does not explicitly teach performing the treatment process on the gate spacers without etching the gate spacers; and after performing the treatment process, selectively etching the treated portion of exposed portions of the gate spacers.
Kang teaches, Figs. 1F & 1I, abstract, claims 1 & 17, [0037, 0046], performing the treatment process (e.g., plasma and/or thermal anneal) on the gate spacers without etching the gate spacers (low-k spacer); and after performing the treatment process, selectively etching (e.g., subsequent etching) the treated portion of exposed portions of the gate spacers.
As taught by Kang, one of ordinary skill in the art would utilize & modify the above to obtain the steps of performing the treatment process on the gate spacers without etching the gate spacers; and after performing the treatment process, selectively etching the treated portion of exposed portions of the gate spacers as claimed, because it aids in reducing etching rates of the spacer and facilitating the etching process in subsequent steps.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kang in combination Wu due to above reason.
5. Claim 11 is, alternatively, rejected under 35 U.S.C. 103 as being unpatentable over Wu as modified by Kang as applied to claim 10 above, and further in view of Raley et al. (US 2015/0249017).
The teachings of Wu/Kang have been discussed above.
Re claim 11, Wu/Kang does not explicitly teach wherein the treatment process is an O2 oxygen plasma treatment and the treated portions are silicon oxide portion of the gate spacers.
Raley teaches, Fig. 3A, claim 1, [0057], the treatment process is an O2 oxygen plasma treatment and the treated portions are silicon oxide portion of the gate spacers (260).
As taught by Raley, one of ordinary skill in the art would utilize & modify the above teaching to obtain the treatment process is an O2 oxygen plasma treatment and the treated portions are silicon oxide portion of the gate spacers as claimed, because oxygen is known and widely used in the art to treat insulating materials.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Raley in combination Wu/Kang due to above reason.
6. Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Wu as modified by Julien (or Kang) as applied to claim 10 above, and further in view of Ju et al. (US 2021/0134795).
The teachings of Wu/Julien (or Kang) have been discussed above.
Re claim 16, Wu teaches removing the remainder of the dummy gate electrode (108) and the dummy gate dielectric (106) of the dummy gate; and forming the gate stack (126, 128, 130) (Figs. 1F-I).
Wu/Julien (or Kang) does not teach the semiconductor structure is a semiconductor layer stack and the method further includes: performing a channel release process to remove first semiconductor layers of the semiconductor layer stack after removing the remainder of the dummy gate, thereby leaving second semiconductor layers of the semiconductor layer stack over the substrate; and forming the gate stack after performing the channel release process.
Ju teaches, Figs. 2F-H, [0076, 0081], the semiconductor structure is a semiconductor layer stack (102a-d, 104a-d) and the method further includes: performing a channel release process (144) to remove first semiconductor layers (102a-d) of the semiconductor layer stack after removing the remainder of the dummy gate (116, 118), thereby leaving second semiconductor layers (104a-d) of the semiconductor layer stack over the substrate (100); and forming the gate stack (150, 154, 156) after performing the channel release process.
As taught by Ju, one of ordinary skill in the art would utilize & modify the above teaching to obtain the semiconductor structure is a semiconductor layer stack and the method further includes: performing a channel release process to remove first semiconductor layers of the semiconductor layer stack after removing the remainder of the dummy gate, thereby leaving second semiconductor layers of the semiconductor layer stack over the substrate; and forming the gate stack after performing the channel release process as claimed, because it aids in achieving reliable semiconductor devices at smaller and smaller sizes.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Ju in combination with Wu/Julien (or Kang) due to above reason.
Allowable Subject Matter
7. Claims 1-9 & 21-24 are allowed. The allowable subject matters include: steps of
“modifying the gate profile by treating the exposed upper portions of the inner sidewalls of the gate spacers and removing treated portions of the gate spacers, wherein the treating the exposed upper portions of the inner sidewalls of the gate spacers includes:
performing an oxidation process that includes a radical-dominated oxidation followed by an ion-dominated oxidation and the removing the treated portions of the gate spacers includes removing oxidized portions of the gate spacers, wherein the oxidized portions of the gate spacers include first oxidized portions that result from the radical-dominated oxidation and second oxidized portions that result from the ion-dominated oxidation, and
removing the first oxidized portions before performing the ion-dominated oxidation and removing the second oxidized portions after performing the ion- dominated oxidation; and
after removing a remainder of the dummy gate electrode and the dummy gate dielectric to enlarge the gate opening and expose the channel layer, forming a gate stack of the gate structure in the enlarged gate opening” (claim 1); and
“oxidizing a portion of the exposed inward-facing portions of the gate spacers, wherein the oxidizing includes performing a radical-dominated plasma oxidation followed by an ion- dominated plasma oxidation, wherein the radical-dominated plasma oxidation and the ion- dominated plasma oxidation each expose the portion of the exposed inward-facing portions of the gate spacers to oxygen radicals and oxygen ions, wherein the oxygen radicals are a dominant reactive species during the radical-dominated plasma oxidation and the oxygen ions are the dominant reactive species during the ion-dominated plasma oxidation;
removing the oxidized portion of the exposed inward-facing portions of the gate spacers and a remainder of the dummy gate to form a funnel-shaped gate opening; and
forming a gate stack in the funnel-shaped gate opening” (claim 21).
Response to Arguments
8. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Conclusion
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 7/16/26
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