DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of group I and species C in the reply filed on 2/12/2026 is acknowledged. The traversal is on the ground(s) that the office has not demonstrated a serious search burden. No argument or evidence exists beyond this statement. This is not found persuasive because the requirement for restriction clearly pointed out in section 4 that the claims to the different identified groups require a different field of search (as established by the separate CPC classifications for the identified groups) and different text search strategies for the different features.
Applicant’s election of group I and species C in the reply filed on 2/12/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 11-12, 14-15, 21-23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20210305262 A1 (Wang).
Re claim 1, Wang teaches a method, comprising:
forming a circuit array comprising a plurality of circuit cells (memory cells 101, 103 Fig. 1), at least one circuit cell of the circuit cells comprising:
a first transistor (pull-up transistor PU1);
a second transistor (pull-up transistor PU2);
a third transistor (pull-down transistor PD1);
a fourth transistor (pull-down transistor PD2);
a fifth transistor (pass-gate transistor PG1); and
a sixth transistor (pass-gate transistor PG2);
forming first front-side metal layer (Fig. 4A) above the circuit array, the first front-side metal layer comprising a first power supply voltage line (Vss power line 505 [0037] Fig. 5B) and a first signal line (line connecting source/drain of PG1 and node crossing source/drain line between PU1 and PD1), the first power supply voltage line electrically coupled to the first transistor and the second transistor, and the signal line electrically coupled to the fifth transistor (Fig. 1, 4A, 5B); and
forming a back-side butt contact (vias 404/504 as made in the process depicted in Figs. 7A-7G [0055] connected to backside M0) extending from a back-side of a gate structure of the first transistor to a back-side of a source/drain region of the second transistor from a cross-sectional view (backside M0 extends from the region closest to the gate structure 708 to the s/d structures 714 in the chip base Figs. 1, 4A-4B, 5B, 7A-7G).
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Re claim 2, Wang teaches further comprising: forming a source/drain contact on a source/drain region of the fifth transistor; and forming a source/drain via on the source/drain contact, the source/drain via being in contact with the signal line (vias 504 which connect the PG1 to the BL Fig. 1, Fig. 5B).
Re claim 3, Wang teaches further comprising: forming a first back-side metal layer (BL/BLB 102 Fig. 5B) below the circuit array, the first back- side metal layer comprising a second power supply voltage line electrically coupled to the third transistor (BL/BLB 102 are formed on the backside of the chip base and are electrically connected to the current path of PD1 Fig. 1, 4B, 5B).
Re claim 4, Wang teaches wherein forming the first back-side metal layer comprises: forming a second signal line electrically coupled to the fifth transistor (BL/BLB 102 are formed on the backside of the chip base and are electrically connected to the current path of PG1 Fig. 1, 4B, 5B).
Re claim 5, Wang teaches wherein forming the first back-side metal layer comprises: forming a third power supply voltage line (BL/BLB 104 Fig. 5B) electrically coupled to the fourth transistor; and forming a third signal line electrically coupled to the sixth transistor BL (BL/BLB 104 are formed on the backside of the chip base and are electrically connected to the current path of PG2 Fig. 1, 4B, 5B).
Re claim 11, Wang teaches a method, comprising:
forming first and second channel patterns (active regions 305) over a substrate (substrate 702);
forming a first gate pattern (gates/word lines 108/307/708 Figs. 4A-4B and 7A-7G) extending across the first channel pattern, and a second gate pattern extending across the second channel pattern from a top view;
forming first source/drain patterns (source/drain regions 714 Figs. 4A-4B and 7A-7G) on the first channel pattern and at opposite sides of the first gate pattern (nominal structure of a lateral stacked multichannel GAAFET as depicted in Wang), and second source/drain patterns on the second channel pattern and at opposite sides of second gate pattern from the top view (each transistor is formed by source/channel/drain and then controlled with gate electrode and ohmic contacts for the input/output electrodes);
forming a front-side contact on a front-side of a first one of the first source/drain patterns from a cross-sectional view (frontside contacts are to the Vss which connects to PU1, PU2, PD1, PD2, PG1 and PG2); and
forming a back-side butt (vias 404/504 as made in the process depicted in Figs. 7A-7G [0055] connected to backside M0) contact extending from a back-side of the first one of the first source/drain patterns to a back-side of the second gate pattern from the cross-sectional view (backside M0 extends from the region closest to the gate structure 708 to the s/d structures 714 in the chip base Figs. 1, 4A-4B, 55B, 7A-7G).
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Re claim 12, Wang teaches further comprising: forming a third channel pattern on the substrate, wherein the first gate pattern further extends across the third channel pattern; forming third source/drain patterns on the third channel pattern and at opposite sides of the first gate pattern; and forming a back-side conductive via (vias 504 are connected to the current path electrodes of the SRAM transistors) on one of the third source/drain patterns, a back-side surface of the back-side conductive via being level with a back-side surface of the back-side butt contact (each 6T SRAM memory cell has six transistors and the embodiments of Wang having the backside contacts to BL/BLB would require any input/output electrodes of PU1, PU2, PD1, PD2 PG1, PG2 and Fig. 5B shows these vias are coplanar Figs. 1, 4A-4B, 5B, 7A-7G).
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Re claim 14, Wang teaches wherein the first channel pattern, the first gate pattern, and the first source/drain patterns form a transistor being of a first inverter, and the second channel pattern, the second gate pattern, and the second source/drain patterns form a transistor being of a second inverter (CMOS inverters are formed from PU1/PD1 and PU2/PD2 ).
Re claim 15, Wang teaches wherein the first channel pattern, the first gate pattern, and the first source/drain patterns form a gate all around (GAA) transistor, and the second channel pattern, the second gate pattern, and the second source/drain patterns form a second GAA transistor (Figs. 7A-7G).
Re claim 21, Wang teaches method, comprising:
forming a first transistor (pull-up transistor PU1) having a first source/drain, a second source/drain, and a first gate (each transistor has source/channel/drain and is controlled by a gate Figs. 1, 4A-4B, 5B and 7A-7G);
forming a second transistor having a third source/drain (pull-up transistor PU2), a fourth source/drain, and a second gate (each transistor has source/channel/drain and is controlled by a gate Figs. 1, 4A-4B, 5B and 7A-7G);
forming a front-side metal layer over the first transistor and the second transistor, the front-side metal layer comprising a first power supply voltage line (pull up transistors are connected to Vss Figs. 1, 4A-4B, 5B and 7A-7G) electrically coupled to the first source/drain and the third source/drain; and
forming a back-side via layer (backside vias 504 and metallization layers connecting to BL/BLB) under the first transistor and the second transistor (Figs. 1, 4A-4B, 5B and 7A-7G),
wherein forming the back-side via layer comprises:
forming a first butt contact electrically coupled to the first gate and the fourth source/drain; and forming a second butt contact electrically coupled to the second gate and the second source/drain (vias 504 are nodes which connect the pass gates to the bit lines which are serially connected on either side to PU1 and PU2 Figs. 1, 4A-4B, 5B and 7A-7G)).
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Re claim 22, Wang teaches comprising: forming a back-side metal layer under the back-side via layer, the back-side metal layer comprising a second power supply voltage line (BL/BLB Figs. 1, 4A-4B, 5B and 7A-7G)).
Re claim 23, Wang teaches wherein forming the back-side via layer comprises: forming a via electrically coupled to the second power supply voltage line (Fig. 5B).
Allowable Subject Matter
Claims 6-10, 13, 24-25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIGITTE A PATERSON whose telephone number is (571)272-1752. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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BRIGITTE A. PATERSON
Primary Examiner
Art Unit 2896
/BRIGITTE A PATERSON/Primary Examiner, Art Unit 2896