DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/26/2026 has been entered.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-2, 4, 6-13, 15-16, 18, 20-24, 42, and 59-72 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3-4, 6-7, 9, 11, 16-17, 19, 26, 28-29, 31, 58, and 75-79 of copending Application No. 18/456,782 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because applicant merely seeks to broaden the claims by describing the source, drain, and gate contacts found in dependent claims of the instant application as first, second, and third contacts. Regarding independent claim 1, the reference application teaches a first carrier, a second carrier, and a semiconductor die coupled to the carriers. Regarding independent claim 42, applicant merely claims a method of coupling a semiconductor die to first and second carriers. Therefore, the reference application anticipates the instant application since the reference application fully encompasses the scope of the claims in the instant application.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 59, and 73-74 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takeda (US Publication No. 2022/0093554).
Regarding claim 1, Takeda discloses a power semiconductor package (Figure 1), comprising:
a first carrier substrate (51), the first carrier substrate (51) comprising one or more conductive pads (23)
a second carrier substrate (11), the second carrier substrate (11) comprising one or more conductive leads (22), wherein the second carrier substrate is a lead frame (34) for connection to external components (Figure 1 paragraph 12)
and a power semiconductor die (20A/20B) having a first surface (upper) and an opposing second surface (lower), and an insulating layer (41) on the first surface of the power semiconductor die between the power semiconductor die and the first carrier substrate (51), the insulating layer comprising an underfill material (paragraph 32)
wherein the first surface (upper) of the power semiconductor die (20A/20B) is directly coupled to the first carrier substrate (51)
wherein the second surface (lower) of the power semiconductor die (20A/20B) is directly coupled to the second carrier substrate (11)
Regarding claim 73, Takeda discloses the first carrier substrate (51) provides a first thermally conductive path for the power semiconductor die (20A/20B), and the second carrier (11) provides a second thermally conductive path for the power semiconductor die (paragraphs 26-32).
Regarding claim 74, Takeda discloses an encapsulating (60) portion at least partially around the first carrier substrate (51) and the second carrier substrate (11), the encapsulated portion forming a housing for the power semiconductor package, wherein the first thermally conductive path and the second thermally conductive path extend towards opposing side of the housing (paragraphs 26-32; Figure 1).
Regarding claim 59, Takeda discloses a power semiconductor package, comprising:
a first carrier substrate (51), the first carrier substrate (51) comprising one or more conductive pads (23)
a second carrier substrate (11), the second carrier substrate (11) comprising one or more conductive leads (22)
a power semiconductor die (20A/20B) having a first surface (upper) and an opposing second surface (lower)
wherein the first surface (upper) of the power semiconductor die (20A/20B) is directly coupled to the first carrier substrate (51)
wherein the second surface (lower) of the power semiconductor die (20A/20B) is directly coupled to the second carrier substrate (11)
wherein the power semiconductor package is devoid of wire bonds, clips, and wire ribbons (paragraph 3)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-2, 4, 6-13, 15-16, 18, 20, and 42 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Publication No. 2020/0357729) in view of Takeda (US Publication No. 2022/0093554).
Regarding claim 1, Kim discloses a power semiconductor package (Figure 1), comprising:
a first carrier substrate (112), the first carrier substrate (112) comprising one or more conductive pads (114/116)
a second carrier substrate (104), the second carrier substrate (104) comprising one or more conductive leads (802), wherein the second carrier substrate is a lead frame for connection to external components (Figure 12; paragraph 25)
and a power semiconductor die (102) having a first surface (134) and an opposing second surface (139)
wherein the first surface (134) of the power semiconductor die (102) is directly coupled to the first carrier substrate (112)
wherein the second surface (139) of the power semiconductor die (102) is directly coupled to the second carrier substrate (104)
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Kim does not disclose an insulating layer on the first surface of the power semiconductor die between the power semiconductor die and the first carrier substrate, the insulating layer comprising an underfill material. However, Takeda discloses an insulating layer (41) between a power semiconductor die (20A/20B) and a carrier substrate (51) comprising an underfill material (resin). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the package of Kim to include the insulating layer, as taught by Takeda, since it can facilitate propagating heat from the device while maintaining bonding (paragraph 32).
Regarding claim 2, Kim discloses the power semiconductor die (102) comprises a first contact (125) on the first surface (134) and a second contact (138) on the second surface (139), wherein the first contact (125) is directly coupled to at least one of the one or more conductive pads (114) of the first carrier substrate (116), wherein the second contact (138) is directly coupled to the second carrier substrate (104) (Figure 13).
Regarding claim 4, Kim discloses the power semiconductor die comprises a third contact (125 right) on the first surface, wherein the one or more conductive pads of the first carrier substrate comprises a first conductive pad (114) and a second conductive pad (116), wherein the first contact (125 left) is directly coupled to the first conductive pad (114) and the third contact (125 right) is directly coupled to the second conductive pad (116).
Regarding claim 6, Kim discloses the first carrier substrate (112) is coupled to one or more second conductive leads (125) of the power semiconductor package (102).
Regarding claim 7, Kim discloses the power semiconductor die (102) is directly coupled to the first carrier substrate (112) in a flip chip configuration (The active side of 102 is facing up, and is therefore flipped).
Regarding claim 8, Kim discloses the first carrier substrate comprises a direct bonded copper (DBC) substrate or an active metal brazed (AMB) substrate (paragraph 29).
Regarding claim 9, Kim discloses the second carrier substrate (104) comprises a lead frame (108) for the power semiconductor package.
Regarding claim 10, Kim discloses the first carrier substrate (112) comprises a first surface (115) and an opposing second surface (113), wherein the one or more conductive pads (114/116) are on the first surface (115) of the first carrier substrate (112), wherein the first carrier substrate (112) comprises a thermally conductive cooling layer (118) on the second surface (113).
Regarding claim 11, Kim discloses the thermally conductive cooling layer (118) is exposed through an encapsulating portion (120) of the power semiconductor package (Figure 17).
Regarding claim 12, Kim discloses the thermally conductive cooling layer (118) is covered by an encapsulating portion (120) of the power semiconductor package (Encapsulant 120 at least partially covers the cooling layer 118).
Regarding claim 13, Takeda discloses the power semiconductor die (20A) comprises a first contact (42) on the first surface and a second contact (22) on the second surface, the power semiconductor package further comprising the insulating layer (41) on the first contact (42) of the power semiconductor die (20A), wherein the underfill material is a first dielectric material (paragraph 32). As discussed above, it would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified Kim in view of Takeda.
Regarding claim 15, Kim discloses an encapsulating portion (120), the encapsulating portion comprising a second dielectric material (paragraph 30, plastic).
Regarding claim 16, Kim discloses the first dielectric material (112) is different from the second dielectric material (120) such that the first dielectric material has a first dielectric constant, and the second dielectric material has a second dielectric constant, the first dielectric constant being different from the second dielectric constant (Paragraphs 27 and 30 show different materials, and therefore different dielectric constant materials).
Regarding claim 18, Kim discloses the first dielectric material is the same as the second dielectric material (Paragraphs 27 and 30 describe the dielectric materials can both be ceramic).
Regarding claim 20, Kim discloses the power semiconductor die (102) comprises a wide band gap semiconductor (paragraph 1).
Regarding claim 42, Kim discloses a method of fabricating a power semiconductor package, the method comprising:
directly coupling a power semiconductor die (102) to a first carrier substrate (104) to form a first assembly (Figure 10)
directly coupling the first assembly (102/104) to a second carrier substrate (110), the second carrier substrate comprising one or more conductive leads (114), wherein the second carrier substrate is a lead frame for connection to external components (Figure 12; paragraph 25)
encapsulating (120) at least a portion of the first carrier substrate (104), the second carrier substrate (110), and the power semiconductor die (102) to form an encapsulating portion (Figure 17)
Kim does not disclose an insulating layer on the first surface of the power semiconductor die between the power semiconductor die and the first carrier substrate, the insulating layer comprising an underfill material. However, Takeda discloses an insulating layer (41) between a power semiconductor die (20A/20B) and a carrier substrate (51) comprising an underfill material (resin). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the package of Kim to include the insulating layer, as taught by Takeda, since it can facilitate propagating heat from the device while maintaining bonding (paragraph 32).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 6-13, 15-16, 18, 20, 22, 42, and 59-70 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Publication No. 2020/0357729) in view of Broll et al. (US Publication No. 2023/0063259), and further in view of Takeda (US Publication No. 2022/0093554).
Regarding claim 1, Kim discloses a power semiconductor package (Figure 1), comprising:
a first carrier substrate (112), the first carrier substrate (112) comprising one or more conductive pads (114/116)
a second carrier substrate (104), the second carrier substrate (104) comprising one or more conductive leads (802), wherein the second carrier substrate is a lead frame for connection to external components (Figure 12; paragraph 25)
and a power semiconductor die (102) having a first surface (134) and an opposing second surface (139)
wherein the first surface (134) of the power semiconductor die (102) is directly coupled to the first carrier substrate (112)
wherein the second surface (139) of the power semiconductor die (102) is directly coupled to the second carrier substrate (104)
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Kim does not explicitly disclose the second carrier is a lead frame for connection to external components. However, Broll discloses a carrier structure (102) is a metal lead frame for external connection (142) (paragraph 46; Figure 1). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the package of Kim to include a lead frame as the carrier for external connection, since it can allow for a variety of electrical connection configurations, therefore improving versatility of the device (paragraph 46).
Regarding claim 2, Kim discloses the power semiconductor die (102) comprises a first contact (125) on the first surface (134) and a second contact (138) on the second surface (139), wherein the first contact (125) is directly coupled to at least one of the one or more conductive pads (114) of the first carrier substrate (116), wherein the second contact (138) is directly coupled to the second carrier substrate (104) (Figure 13).
Regarding claim 4, Kim discloses the power semiconductor die comprises a third contact (125 right) on the first surface, wherein the one or more conductive pads of the first carrier substrate comprises a first conductive pad (114) and a second conductive pad (116), wherein the first contact (125 left) is directly coupled to the first conductive pad (114) and the third contact (125 right) is directly coupled to the second conductive pad (116).
Regarding claim 6, Kim discloses the first carrier substrate (112) is coupled to one or more second conductive leads (125) of the power semiconductor package (102).
Regarding claim 7, Kim discloses the power semiconductor die (102) is directly coupled to the first carrier substrate (112) in a flip chip configuration (The active side of 102 is facing up, and is therefore flipped).
Regarding claim 8, Kim discloses the first carrier substrate comprises a direct bonded copper (DBC) substrate or an active metal brazed (AMB) substrate (paragraph 29).
Regarding claim 9, Kim discloses the second carrier substrate (104) comprises a lead frame (108) for the power semiconductor package.
Regarding claim 10, Kim discloses the first carrier substrate (112) comprises a first surface (115) and an opposing second surface (113), wherein the one or more conductive pads (114/116) are on the first surface (115) of the first carrier substrate (112), wherein the first carrier substrate (112) comprises a thermally conductive cooling layer (118) on the second surface (113).
Regarding claim 11, Kim discloses the thermally conductive cooling layer (118) is exposed through an encapsulating portion (120) of the power semiconductor package (Figure 17).
Regarding claim 12, Kim discloses the thermally conductive cooling layer (118) is covered by an encapsulating portion (120) of the power semiconductor package (Encapsulant 120 at least partially covers the cooling layer 118).
Regarding claim 13, Takeda discloses the power semiconductor die (20A) comprises a first contact (42) on the first surface and a second contact (22) on the second surface, the power semiconductor package further comprising the insulating layer (41) on the first contact (42) of the power semiconductor die (20A), wherein the underfill material is a first dielectric material (paragraph 32). As discussed above, it would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified Kim in view of Takeda.
Regarding claim 15, Kim discloses an encapsulating portion (120), the encapsulating portion comprising a second dielectric material (paragraph 30, plastic).
Regarding claim 16, Kim discloses the first dielectric material (112) is different from the second dielectric material (120) such that the first dielectric material has a first dielectric constant, and the second dielectric material has a second dielectric constant, the first dielectric constant being different from the second dielectric constant (Paragraphs 27 and 30 show different materials, and therefore different dielectric constant materials).
Regarding claim 18, Kim discloses the first dielectric material is the same as the second dielectric material (Paragraphs 27 and 30 describe the dielectric materials can both be ceramic).
Regarding claim 20, Kim discloses the power semiconductor die (102) comprises a wide band gap semiconductor (paragraph 1).
Regarding claim 42, Kim discloses a method of fabricating a power semiconductor package, the method comprising:
directly coupling a power semiconductor die (102) to a first carrier substrate (104) to form a first assembly (Figure 10)
directly coupling the first assembly (102/104) to a second carrier substrate (110), the second carrier substrate comprising one or more conductive leads (114), wherein the second carrier substrate is a lead frame for connection to external components (Figure 12; paragraph 25)
encapsulating (120) at least a portion of the first carrier substrate (104), the second carrier substrate (110), and the power semiconductor die (102) to form an encapsulating portion (Figure 17)
Kim does not explicitly disclose the second carrier is a lead frame for connection to external components. However, Broll discloses a carrier structure (102) is a metal lead frame for external connection (142) (paragraph 46; Figure 1). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the package of Kim to include a lead frame as the carrier for external connection, since it can allow for a variety of electrical connection configurations, therefore improving versatility of the device (paragraph 46).
Regarding claim 22, Kim discloses the limitations as discussed in the rejection of claim 1 above. Kim does not disclose the power semiconductor package does not include any wire bonds. However, Broll discloses optionally using wire bonds or metal clips (paragraph 27). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the package of Kim to avoid using wire bonds, as taught by Broll, since it can improve current carrying capacity to use metal clips or bond pads (paragraphs 1-2).
Regarding claim 59, Kim discloses a power semiconductor package, comprising:
a first carrier substrate 112), the first carrier substrate (112) comprising one or more conductive pads (114/116)
a second carrier substrate (104), the second carrier substrate (104) comprising one or more conductive leads (802)
a power semiconductor die (102) having a first surface (134) and an opposing second surface (139)
wherein the first surface (134) of the power semiconductor die (102) is directly coupled to the first carrier substrate (112)
wherein the second surface (139) of the power semiconductor die (102) is directly coupled to the second carrier substrate (104)
wherein the power semiconductor package does not include any wire bonds
Kim does not disclose the power semiconductor package is devoid of wire bonds. However, Broll discloses optionally using wire bonds or metal clips (paragraph 27). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the package of Kim to avoid using wire bonds, as taught by Broll, since it can improve current carrying capacity to use metal clips or bond pads (paragraphs 1-2).
Regarding claim 60, Kim discloses the second carrier substrate (104) is a lead frame for connection to external components (Figure 12; paragraph 25).
Regarding claim 61, Kim discloses the power semiconductor die (102) comprises a first contact (125) on the first surface (134) and a second contact (138) on the second surface (139), wherein the first contact (125) is directly coupled to at least one of the one or more conductive pads (114) of the first carrier substrate (116), wherein the second contact (138) is directly coupled to the second carrier substrate (104) (Figure 13).
Regarding claim 62, Kim discloses the power semiconductor die comprises a third contact (125 right) on the first surface, wherein the one or more conductive pads of the first carrier substrate comprises a first conductive pad (114) and a second conductive pad (116), wherein the first contact (125 left) is directly coupled to the first conductive pad (114) and the third contact (125 right) is directly coupled to the second conductive pad (116).
Regarding claim 63, Kim discloses the first carrier substrate (112) is coupled to one or more second conductive leads (125) of the power semiconductor package (102).
Regarding claim 64, Kim discloses the power semiconductor die (102) is directly coupled to the first carrier substrate (112) in a flip chip configuration (The active side of 102 is facing up, and is therefore flipped).
Regarding claim 65, Kim discloses the first carrier substrate comprises a direct bonded copper (DBC) substrate or an active metal brazed (AMB) substrate (paragraph 29).
Regarding claim 66, Takeda discloses the power semiconductor die comprises a first contact on the first surface and a second contact on the second surface, the power semiconductor package further comprising an insulating layer (41) on the first contact (42) of the power semiconductor die (20A), wherein the insulating layer comprises a first dielectric material (paragraph 32); and an encapsulating portion (60), the encapsulating portion comprising a second dielectric material (paragraph 41). As discussed above, it would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified Kim in view of Takeda.
Regarding claim 67, Kim discloses the thermally conductive cooling layer (118) is exposed through an encapsulating portion (120) of the power semiconductor package (Figure 17).
Regarding claim 68, Kim discloses the first carrier substrate (112) comprises a thermally conductive cooling layer (118) that is covered (laterally covered) by the encapsulating portion (120).
Regarding claim 69, Kim discloses the first dielectric material (112) is different from the second dielectric material (120) (Paragraphs 27 and 30 show different materials, and therefore different dielectric constant materials).
Regarding claim 70, Kim discloses the first dielectric material is the same as the second dielectric material (Paragraphs 27 and 30 describe the dielectric materials can both be ceramic).
Claims 21, 23, and 71 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Publication No. 2020/0357729) in view of Broll et al. (US Publication No. 2023/0063259), in view of Takeda (US Publication No. 2022/0093554), and further in view of Stella et al. (US Publication No. 2022/0199563).
Regarding claim 21, Kim discloses the limitations as discussed in the rejection of claim 1 above. Kim is silent regarding the wide band gap semiconductor is silicon carbide. However, Stella discloses a wide band gap semiconductor that is silicon carbide (paragraph 5). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the semiconductor die of Kim to be made of silicon carbide, as taught by Stella, since for their use in high voltage/high power applications that can allow for fast power conversion and rapid switching (paragraphs 2-3).
Regarding claim 23, Stella discloses the power semiconductor die comprises a silicon carbide-based MOSFET (paragraph 5).
Regarding claim 71, Kim discloses the limitations as discussed in the rejection of claim 59 above. Kim also discloses the power semiconductor die (102) comprises a wide band gap semiconductor (paragraph 1). Kim is silent regarding the wide band gap semiconductor is silicon carbide. However, Stella discloses a wide band gap semiconductor that is silicon carbide (paragraph 5). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the semiconductor die of Kim to be made of silicon carbide, as taught by Stella, since for their use in high voltage/high power applications that can allow for fast power conversion and rapid switching (paragraphs 2-3).
Claims 24 and 72 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Publication No. 2020/0357729) in view of Broll et al. (US Publication No. 2023/0063259) in view of Takeda (US Publication No. 2022/0093554), and further in view of Seal et al. (US Publication No. 2022/0238426).
Regarding claim 24, Kim discloses the limitations as discussed in the rejection of claim 1 above. Kim is silent regarding the power semiconductor die comprises a silicon carbide-based Schottky diode. However, Seal discloses a silicon carbide-based Schottky diode (paragraph 2). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the semiconductor die of Kim to comprise a SiC Schottky diode, as taught by Seal, for its high reliability and wide applications in high voltage devices (paragraphs 2-5).
Regarding claim 72, Kim discloses the limitations as discussed in the rejection of claim 59 above. Kim is silent regarding the power semiconductor die comprises a silicon carbide-based MOSFET or Schottky diode. However, Seal discloses a silicon carbide-based Schottky diode (paragraph 2). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the semiconductor die of Kim to comprise a SiC MOSFET or Schottky diode, as taught by Seal, for its high reliability and wide applications in high voltage devices (paragraphs 2-5).
Conclusion
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/N.R.P/ 8/17/2026Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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