Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Amendment, received 1/28/2026, has been entered.
Claims 1-12 are presented for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 7 and 9-12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nagai et al. (US Pub. No. 2001/0054725 A1).
As to claim 7, Nagai discloses a method of manufacturing a semiconductor device (figs 7-12 and [0033]-[0038]), comprising:
forming a first MOS device (fig 8, MOS device 9B [0069]) and a second MOS device (fig 8, MOS device 9A; [0069]) on a substrate (1);
forming a first dielectric layer (4; [0074]) beside the first MOS device and the second MOS device (MOS devices 9A and 9B);
forming a first stop layer (fig 9, 15) on the first dielectric layer (4);
removing at least part of the first stop layer to form an opening in the first stop layer (opening in 15 corresponding to region B), wherein the opening corresponds to the first MOS device (9B in region B), and the second MOS device is not exposed by the first stop layer (9A is not exposed by 15);
performing a sintering process ([0078]); and
forming a second dielectric layer (19; [0078]) covering the stop layer (15).
As to claim 9, Nagai discloses the method of manufacturing the semiconductor device according to claim 7 (paragraphs above).
Nagai further discloses wherein the formed second dielectric layer is further filled in the opening (fig 12, 19 is filled in the opening in 15 in region B).
As to claim 10, Nagai discloses the method of manufacturing the semiconductor device according to claim 7 (paragraphs above).
Nagai further discloses forming a second stop layer (19 is considered to be a dielectric stop layer) on the first stop layer (15) and filling the second stop layer in the opening (19 fills the opening in 15 in region B).
As to claim 11, Nagai discloses the method of manufacturing the semiconductor device according to claim 10 (paragraphs above).
Nagai further discloses wherein at least part of the first stop layer is removed, and a bottom of the opening exposes the first stop layer (fig 9, 15 is removed from region B and bottom of opening exposes 15 at an angle).
As to claim 12, Nagai discloses the method of manufacturing the semiconductor device according to claim 7 (paragraphs above).
Nagai further discloses wherein at least part of the first stop layer is removed, and a bottom of the opening exposes the first MOS device (fig 9, 15 is removed in region B and bottom exposes first MOS device).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nagai in view of Isogai et al. (US Pub. No. 2014/0004690 A1), hereafter referred to as Isogai.
As to claim 8, Nagai discloses the method of manufacturing the semiconductor device according to claim 7 (paragraphs above).
Nagai does not disclose wherein a gas used in the sintering process comprises hydrogen.
Nonetheless, Isogai discloses wherein a gas used in a sintering process comprises hydrogen ([0003] and [0044]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to perform the sintering process comprising hydrogen as taught by Isogai in the method of manufacturing the semiconductor device of Nagai since this will improve the interface level density by terminating dangling bond by stabilizing with hydrogen.
Allowable Subject Matter
Claims 1-6 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: Applicant’s arguments with respect to claims 1 and 4 on pages 6-7 of the remarks received 1/28/2026 are persuasive. Claims 2-3 and 5-6 are allowable because of their dependence from one of allowable claims 1 or 4.
Response to Arguments
Applicant’s arguments with respect to claim(s) 7-12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent No. 6,787,417 B2; and US Pub. No. 2005/0263825 A1.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Purvis, Sue can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 2/23/2026