Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 1-2, 6-7, 9-12, 15-16, 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Yen (US 20180358362 A1) in view of Ping (US 20210343720 A1) and Ryu (US 20190259839 A1).
Regarding claim 1, Yen discloses a memory structure (Fig. 1I), comprising:
a semiconductor substrate (100) having a first trench (104 on left. See annotated figure for direction designation.), a second trench (104 on right), a first top surface (See annotated figure), a second top surface (See annotated figure) between (horizontally between) the first trench and the second trench, wherein the second top surface is lower than the first top surface;
first and second word line structures (112 on left, 112 on right), wherein the first word line structure is located in a lower portion of the first trench (See annotated figure for direction designation), and the second word line structure is located in a lower portion of the second trench (See annotated figure for direction designation), wherein the first word line structure comprises a lower gate electrode (112), an upper gate electrode overlapping the lower gate electrode, and a barrier layer between the upper gate electrode and the lower gate electrode;
an isolation structure (111) located in the first trench and the second trench and on the first and second word line structures (vertically on), in contact with a sidewall of the first trench and a sidewall of the second trench (horizontal contact), and extending onto the first top surface of the semiconductor substrate (vertically on), wherein the isolation structure has a top surface (See annotated figure) extending to and coplanar (coplanar in the horizontal direction) with the second top surface of the semiconductor substrate;
a bit line contact layer (160) on the second top surface of the semiconductor substrate (directly on) and surrounded by the isolation structure (horizontally surrounded);
an outer oxide layer located between the upper gate electrode of the first word line structure and the barrier layer of the first word line structure and extending to the isolation structure along a sidewall of the upper gate electrode of the first word line structure; and
an inner oxide layer (110) located between the outer oxide layer and the sidewall of the first trench and between the barrier layer of the first word line structure and the sidewall of the first trench, wherein a top surface of the inner oxide layer is higher than a top surface of the lower gate electrode of the first word line structure, the top surface of the inner oxide layer (See annotated figure) is lower than a top surface of the isolation structure (See annotated figure, lower in the vertical direction), and the top surface of the inner oxide layer and a top surface of the outer oxide layer are in contact (direct contact) with the isolation structure;
wherein the outer oxide layer comprises silicon dioxide.
Illustrated below is a marked and annotated figure of Fig. 1I of Yen.
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Yen fails to teach “wherein the first word line structure comprises a lower gate electrode, an upper gate electrode overlapping the lower gate electrode,”, “an outer oxide layer located between the upper gate electrode of the first word line structure and the barrier layer of the first word line structure and extending to the isolation structure along a sidewall of the upper gate electrode of the first word line structure;”, and “a top surface of the outer oxide layer are in contact with the isolation structure; wherein the outer oxide layer comprises silicon dioxide”.
Ping discloses:
[…] the first word line structure (Fig. 10) comprises a lower gate electrode (200), an upper gate electrode (400) overlapping (vertically overlapping) the lower gate electrode, and a barrier layer between the upper gate electrode and the lower gate electrode;
[…]
an outer oxide layer (300) located between (horizontally between) the upper gate electrode of the first word line structure and the barrier layer of the first word line structure and extending to the isolation structure (700) along (vertically along) a sidewall of the upper gate electrode of the first word line structure; and
[…] and a top surface of the outer oxide layer are in contact with the isolation structure (direct “contact” at least at the edge. Note: this edge/point contact is incorporated as a possible configuration produced by the combination of this feature among Yen: Fig. 1I: isolation structure 111);
wherein the outer oxide layer comprises silicon dioxide ([0064]: “silicon oxide”)
Modifying the first and second word line structures of Yen by including the lower and upper gate electrodes and the outer oxide layer of Ping would substantially arrive at the claimed word line configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the gate is performing the same function as a gate within a memory device (Yen: [0015]: “memory device”; Ping: [0072]: “active areas of a storage element”). Ping teaches motivation for one of ordinary skill in the art before the effective filing date to include the upper word line and outer oxide layer in that it would reduce current leakage during operation, thereby improving operational characteristics of the device ([0077]: “can properly address the problem of the gate-induced drain leakage current”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed word line structures and outer oxide layer because it would improve operational characteristics of the device. MPEP 2143 (I)(G).
Illustrated below is a marked and annotated figure of Fig. 10 of Ping.
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Yen in view of Ping fails to teach “[…], and a barrier layer between the upper gate electrode and the lower gate electrode;” and “an outer oxide layer located between the upper gate electrode of the first word line structure and the barrier layer of the first word line structure and extending to the isolation structure along a sidewall of the upper gate electrode of the first word line structure; and an inner oxide layer located between the outer oxide layer and the sidewall of the first trench and between the barrier layer of the first word line structure and the sidewall of the first trench, wherein a top surface of the inner oxide layer is higher than a top surface of the lower gate electrode of the first word line structure,”.
Ryu discloses:
[…] a barrier layer (Fig. 6: 121/107) between (121 is vertically between) the upper gate electrode (110) and the lower gate electrode (108);
an outer oxide layer (109) located between (vertically between) the upper gate electrode of the first word line structure and the barrier layer of the first word line structure and extending (vertically extending) to the isolation structure along a sidewall of the upper gate electrode of the first word line structure; and
an inner oxide layer (106; [0066]: “may include a silicon oxide, a silicon nitride, a silicon oxynitride, a high-k material, or a combination thereof”) located between (horizontally between) the outer oxide layer and the sidewall of the first trench and between (horizontally between) the barrier layer of the first word line structure and the sidewall of the first trench, wherein a top surface of the inner oxide layer is higher (vertically higher) than a top surface of the lower gate electrode of the first word line structure,”
Modifying the first and second word line structures of Yen in view of Ping by including the barrier layer of Ryu would arrive at the claimed barrier layer configuration. A person of ordinary skill in the art before the effective filing date would have had predictable results because the inclusion of the barrier layer does not change the function of the gate, which is performing the same function as a gate within a memory device (Yen: [0015]: “memory device”; Ryu: [0056]: “a cell transistor of a DRAM”). Ryu teaches motivation for one of ordinary skill in the art before the effective filing date to include the barrier layer in that it would protect the lower gate electrode from degradation by oxidation ([0125]: “may prevent the first gate electrode 108 from being oxidized”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed barrier layer configuration because it would protect the gate from oxidation. MPEP 2143 (I)(G).
Illustrated below is a marked and annotated figure of Fig. 6 of Ryu.
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Regarding claim 2, Yen in view of Ping and Ryu discloses the memory structure of claim 1 (Yen: Fig. 1I), wherein the isolation structure is in contact with top surfaces of the first and second word line structures (direct contact).
Regarding claim 6, Yen in view of Ping and Ryu discloses the memory structure of claim 1 (Yen: Fig. 1I), wherein the bit line contact layer has no portion below the second top surface of the semiconductor substrate (the entirety of 160 is above the second top surface).
Regarding claim 7, Yen in view of Ping and Ryu discloses the memory structure of claim 1 (Yen: Fig. 1I), wherein the bit line contact layer has a trapezoid profile in cross-section (the shape of 160 being a quadrilateral illustrated with at least one pair of parallel sides, therefore a trapezoid).
Regarding claim 9, Yen in view of Ping and Ryu discloses the memory structure of claim 1 (Ping: Fig. 10), wherein a material of the lower gate electrode ([0059]: “a metal material layer”) is different from a material of the upper gate electrode ([0067]: “a semiconductor conductive layer”).
Regarding claim 10, Yen in view of Ping and Ryu discloses the memory structure of claim 9 (Ping: Fig. 10), wherein the material of the lower gate electrode comprises tungsten ([0059]: “tungsten”), and the material of the upper gate electrode comprises polysilicon ([0067]: “polycrystalline silicon”).
Regarding claim 11, Yen in view of Ping and Ryu discloses the memory structure of claim 1 (Yen: Fig. 1I), wherein the upper gate electrode and the bit line contact layer comprise a same material (Yen disclose the bit line contact layer 160 comprises polysilicon [0017]: “polysilicon or another suitable electrode material”; Ping discloses the upper gate electrode 20 may comprise polysilicon [0067]: “polycrystalline silicon”. Therefore, these materials are “a same material”).
Regarding claim 12, Yen in view of Ping and Ryu discloses the memory structure of claim 1 (Ryu: Fig. 6), wherein a material of the barrier layer comprises titanium nitride ([0126]: “titanium nitride”).
Regarding claim 15, Yen in view of Ping and Ryu discloses the memory structure of claim 1 (Yen: Fig. 1I), wherein the isolation structure has a first portion in the first trench (See annotated figure) and a second portion in the second trench (See annotated figure above), a width of the first portion is the same as a width of the first trench (exactly matches as measured in the horizontal direction), and a width of the second portion is the same as a width of the second trench (exactly matches as measured in the horizontal direction).
Regarding claim 21, Yen in view of Ping and Ryu discloses the memory structure of claim 1 (Yen: Fig. 1I; Ping: Fig. 10), wherein the upper gate electrode has a top surface in contact with the isolation structure (direct contact).
Regarding claim 22, Yen in view of Ping and Ryu discloses the memory structure of claim 1 (Ryu: Fig. 6), wherein the barrier layer surrounds the lower gate electrode (fully surrounds) and has a portion between the upper gate electrode and the lower gate electrode (portion 121).
Regarding claim 23, Yen in view of Ping and Ryu discloses the memory structure of claim 1 (Yen: Fig. 1I), wherein the top surface of the inner oxide layer is lower than a bottom surface of the isolation structure (lower in the vertical direction, consistent with “lower” as it applies to Fig. 2 and features 180 and 132 of the disclosure).
Regarding independent claim 16, Yen discloses a manufacturing method of a memory structure (Fig. 1I), comprising:
forming a first trench (104 on left. See annotated figure for direction designation.) and a second trench (104 on right) in a semiconductor substrate (100);
forming an inner oxide layer (110) extending along a sidewall of the first trench (directly on) and a sidewall of the second trench (directly on);
after forming the inner oxide layer ([0021]: “After the insulating liners 110 are formed, a conductive layer 112 (e.g., metal) is formed”), forming two word line structures (112 on left, 112 on right) respectively in the first trench and the second trench, wherein each of the two word line structures comprises a lower gate electrode (112), an upper gate electrode overlapping the lower gate electrode, and a barrier layer between the upper gate electrode and the lower gate electrode;
after forming the inner oxide layer, forming an outer oxide layer such that after forming the two word line structures and the inner oxide layer, the outer oxide layer has a first portion between the barrier layer and the upper gate electrode of each of the two word line structures and a second portion between the inner oxide layer and the upper gate electrode of each of the two word line structures, wherein the outer oxide layer comprises silicon dioxide;
after forming the two word line structures ([0021]: “After the conductive layers 112 are formed”) each comprising the lower gate electrode, the upper gate electrode, and the barrier layer, removing a portion of the inner oxide layer ([0021]: “the conductive layers 112 and the insulating lines 110 are successively etched back”) higher than a top surface of the upper gate electrode of each of the two word line structures (there is no portion of layer 110 higher than word lines 112);
forming an isolation structure (111) in the first trench and the second trench and on the two word line structures (vertically on), wherein the isolation structure is in contact with the sidewall of the first trench and the sidewall of the second trench (horizontal contact), and extends onto a first top surface of the semiconductor substrate (See annotated figure for surface designation);
forming a mask on the isolation structure (124; as shown in the method step of Fig. 1F);
etching, using the mask, a portion of the isolation structure and a portion of the semiconductor substrate (as shown in the method step of Fig. 1F) to form a recess (152) defined by the isolation structure and the semiconductor substrate, wherein the isolation structure has a top surface (See annotated figure for surface designation) extending to and coplanar (coplanar in the horizontal direction) with a second top surface of the semiconductor substrate (See annotated figure for surface designation), the top surface of the isolation structure and the second top surface of the semiconductor substrate collectively form a flat bottom surface of the recess (this surface of the recess is illustrated flat), the second top surface is lower than the first top surface (vertically lower), and the flat bottom surface of the recess extends (“extends” along a multi-faceted surface including the surfaces of recess 150) from a first location directly above a first one of the two word line structures to a second location directly above a second one of the two word line structures; and
forming a bit line contact layer (160) on the second top surface of the semiconductor substrate (directly on) and surrounded by the isolation structure (horizontally surrounded).
Yen fails to teach “an upper gate electrode overlapping the lower gate electrode, and a barrier layer between the upper gate electrode and the lower gate electrode;
after forming the inner oxide layer, forming an outer oxide layer such that after forming the two word line structures and the inner oxide layer, the outer oxide layer has a first portion between the barrier layer and the upper gate electrode of each of the two word line structures and a second portion between the inner oxide layer and the upper gate electrode of each of the two word line structures, wherein the outer oxide layer comprises silicon dioxide;
after forming the two word line structures each comprising the lower gate electrode, the upper gate electrode, and the barrier layer, removing a portion of the inner oxide layer higher than a top surface of the upper gate electrode of each of the two word line structures;”
Ping discloses a method (Fig. 10) comprising:
an upper gate electrode (400) overlapping the lower gate electrode (200), and a barrier layer between the upper gate electrode and the lower gate electrode;
after forming the inner oxide layer (Fig. 4 teaches forming inner oxide layer 500), forming an outer oxide layer (Fig. 7 teaches forming outer oxide layer 300 “after” forming 500) such that after forming the two word line structures and the inner oxide layer, the outer oxide layer has a first portion (See annotated figure) between the barrier layer and the upper gate electrode of each of the two word line structures and a second portion (See annotated figure) between (horizontally between) the inner oxide layer and the upper gate electrode of each of the two word line structures, wherein the outer oxide layer comprises silicon dioxide ([0064]: “silicon oxide”);
Modifying the method of Yen by forming the two word line structures each comprising the lower gate electrode, the upper gate electrode, and the outer oxide layer in the way disclosed by Ping would substantially arrive at the claimed word line formation configuration. Note: the inner oxide layer of Yen is maintained in the same way as before. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the gate is performing the same function as a gate within a memory device (Yen: [0015]: “memory device”; Ping: [0072]: “active areas of a storage element”). Ping teaches motivation for one of ordinary skill in the art before the effective filing date to include forming the upper word line and outer oxide layer in that it would reduce current leakage during operation, thereby improving operational characteristics of the device ([0077]: “can properly address the problem of the gate-induced drain leakage current”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed method forming word line structures and outer oxide layer because it would improve operational characteristics of the device. MPEP 2143 (I)(G).
Yen in view of Ping fails to teach “a barrier layer between the upper gate electrode and the lower gate electrode;
after forming the inner oxide layer, forming an outer oxide layer such that after forming the two word line structures and the inner oxide layer, the outer oxide layer has a first portion between the barrier layer and the upper gate electrode of each of the two word line structures and a second portion between the inner oxide layer and the upper gate electrode of each of the two word line structures, wherein the outer oxide layer comprises silicon dioxide;
after forming the two word line structures each comprising the lower gate electrode, the upper gate electrode, and the barrier layer…”
Ryu discloses a method (Fig. 6) comprising:
a barrier layer (121/107) between (121 is vertically between) the upper gate electrode (110) and the lower gate electrode (108);
after forming the inner oxide layer (Fig. 4B teaches forming inner oxide layer 106 as layer 16), forming an outer oxide layer (Fig. 7C teaches forming outer oxide layer 109 as layer 19A “after” forming 106/16) such that after forming the two word line structures and the inner oxide layer, the outer oxide layer has a first portion (109I) between (vertically between) the barrier layer and the upper gate electrode of each of the two word line structures and a second portion (109S1) between (horizontally between) the inner oxide layer and the upper gate electrode of each of the two word line structures, wherein the outer oxide layer comprises silicon dioxide;
after forming the two word line structures each comprising the lower gate electrode, the upper gate electrode, and the barrier layer…
Modifying the method of Yen in view of Ping by forming the word line structures with a barrier layer in the same way disclosed by Ryu would arrive at the claimed barrier layer configuration. A person of ordinary skill in the art before the effective filing date would have had predictable results because the inclusion of the barrier layer does not change the function of the gate, which is performing the same function as a gate within a memory device (Yen: [0015]: “memory device”; Ryu: [0056]: “a cell transistor of a DRAM”). Ryu teaches motivation for one of ordinary skill in the art before the effective filing date to include the barrier layer when forming the word line structures in that it would protect the lower gate electrode from degradation by oxidation ([0125]: “may prevent the first gate electrode 108 from being oxidized”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed barrier layer configuration because it would protect the gate from oxidation. MPEP 2143 (I)(G).
Claims 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Yen, Ping, and Ryu as applied to claim 1 above, and further in view of Cho (KR 20100074718 A).
Regarding claim 3, Yen in view of Ping and Ryu discloses the memory structure of claim 1 (Yen: Fig. 1I), further comprising:
a first isolation layer (120) on the first top surface of the semiconductor substrate (directly on); and
a second isolation layer on the first isolation layer,
wherein each of the first isolation layer and the second isolation layer has an inner sidewall in contact with the isolation structure (direct contact).
Yen in view of Ping and Ryu fails to teach “a second isolation layer on the first isolation layer, wherein each of the first isolation layer and the second isolation layer has an inner sidewall in contact with the isolation structure”.
Cho discloses a first isolation layer (Fig. 9: 106) on a first top surface of a semiconductor substrate (102); and further discloses a second isolation layer (110) on the first isolation layer. Modifying the memory structure of Yen in view of Ping and Ryu by including a second isolation layer upon the first isolation layer in the same way would arrive at the claimed first and second isolation layers and the claimed inner sidewall configuration. Cho provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the second isolation layer with the first isolation layer in that it would enable etching to a predetermined depth, thereby controlling the manufacturing process (pg. 5 of translation: “a predetermined depth using the hard mask layer”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed second isolation layer because it would enable controlling the manufacturing process. MPEP 2143 (I)(G).
Illustrated below is a marked and annotated figure of Fig. 9 of Cho.
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Regarding claim 4, Yen in view of Ping, Ryu, and Cho discloses the memory structure of claim 3 (Cho: Figs. 3-4), wherein the inner sidewall of the first isolation layer and the inner sidewall of the second isolation layer are perpendicular to the first top surface of the semiconductor substrate (the transition from Fig. 3 to Fig. 4 of Cho includes the method step of etching 110 and 106 to produce the resultant shapes in Fig. 4; pg. 5 of translation: “Form a pattern”; this same technique of Cho applies to the creation of the resultant shape of the inner sidewall of the first isolation layer of Yen 120: accordingly each of the first and second isolation layers would have the same resultant shape as Yen 120).
Regarding claim 5, Yen in view of Ping, Ryu, and Cho discloses the memory structure of claim 3 (Yen: Fig. 1I), wherein the bit line contact layer has no portion between the second isolation layer and the isolation structure (there is no portion of 160 between 120 or the second isolation layer included with 120).
Claims 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Yen, Ping, and Ryu as applied to claim 16 above, and further in view of Cho.
Regarding claim 17, Yen in view of Ping and Ryu discloses the manufacturing method of the memory structure of claim 16 (Yen: 1I), further comprising:
before forming the first trench and the second trench in the semiconductor substrate, forming a first isolation layer (120) and a second isolation layer on the semiconductor substrate (directly on; [0013]: “using a first masking pattern layer” teaches using when forming the trenches, thus it is formed “before”) in sequence.
Yen in view of Ping and Ryu fails to teach “forming a first isolation layer and a second isolation layer on the semiconductor substrate in sequence”.
Cho discloses forming a first isolation layer (Fig. 9: 106) and a second isolation layer (110) on the semiconductor substrate (102) in sequence. Modifying the method of Yen in view of Ping and Ryu by forming a second isolation layer in the same way would arrive at the claimed first and second isolation layer formation configuration. Cho provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include forming the second isolation layer in that it would enable etching to a predetermined depth, thereby controlling the manufacturing process (pg. 5 of translation: “a predetermined depth using the hard mask layer”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed second isolation layer formation because it would enable controlling the manufacturing process. MPEP 2143 (I)(G).
Regarding claim 18, Yen in view of Ping, Ryu, and Cho discloses the manufacturing method of the memory structure of claim 17 (Ping: Fig. 10), wherein the outer oxide layer has a third portion (an intermediately formed portion, subsequently removed and thus not shown; [0062]: “the dielectric material layer covers …the upper surface of the substrate 100”. Note: this interpretation of the third portion is consistent with Figs. 4-5 of the disclosure) on the second isolation layer (vertically on) and on the upper gate electrode (at least indirectly on).
Regarding claim 19, Yen in view of Ping, Ryu, and Cho discloses the manufacturing method of the memory structure of claim 18 (Yen: Fig. 1I), further comprising: before forming the isolation structure in the first trench and the second trench, removing the third portion of the outer oxide layer ([0062]: “The dielectric material layer located on the upper surface of the substrate 100 is removed”. Note: the removal of the third portion cannot be done after forming any subsequent structure, thus fully completing the word lines of Yen/Ping/Ryu/Cho must be done “before forming the isolation structure” of Yen.).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Yen, Ping, Ryu, and Cho as applied to claim 19 above, and further in view of Zou (US 20220037481 A1).
Regarding claim 20, Yen in view of Ping, Ryu, and Cho discloses the manufacturing method of the memory structure of claim 19 (Yen: Fig. 1I),
wherein a material of the second isolation layer comprises nitride,
a material of the semiconductor substrate comprises silicon (Yen: [0011]: “bulk silicon”), and
removing the third portion of the outer oxide layer (Ping: 300 is an oxide and the cited third portion is removed, i.e. stripped) and the portion of the inner oxide layer is performed by an oxide strip process (Yen: 110 is an oxide receiving an oxide strip process; [0021]: “silicon oxide”; and [0021] “etched back”, respectively) having a high selectivity between oxide and nitride and between oxide and silicon (oxide/silicon selectivity is shown at least by the remaining shape and dimensions of the exposed silicon of the trenches of Yen: Fig. 1A after performing the oxide strip; i.e., there is no difference in trench shape between the stripped and non-stripped portions of the trenches, therefore a high selectivity exists).
Yen in view of Ping, Ryu, and Cho fails to teach “a material of the second isolation layer comprises nitride”. Zou discloses a material of the second isolation layer comprises nitride (Zou: [0031]: “the material of the hard mask layer 132 is selected from silicon nitride”). Modifying the material of the second isolation layer of Cho by selecting nitride from the finite selection of known suitable second isolation layer materials would arrive at the claimed material configuration. A person of ordinary skill in the art would have had a reasonable expectation of success because in each situation the second isolation layer is performing the function of a mask (Cho: pg. 5 of translation: “hard mask layer”; Zou: [0031]: “hard mask layer”). Absent unexpected results, it would have been obvious to one having ordinary skill in the art before the effective filing date to try using a different material for the second isolation layer. Thus, the claim would have been obvious because “a person of ordinary skill has good reason to pursue the known options within his or her technique grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. KSR Int'l Co. v. Teleflex Inc. 550 U.S. __, 82USPQ2d 1385 (Supreme Court 2007) (KSR). MPEP 2143 (1)(E).
Further regarding claim 20, the combination of Yen, Ryu, Cho, and Zou discloses “an oxide strip process having a high selectivity between oxide and nitride” because Yen teaches the oxide strip process retains the first isolation layer (Yen: Fig. 1A retains 120 after 110 is stripped) and teaches the first isolation layer material composition may be varied ([0013]: “silicon oxide or another suitable hard masking material”). Thus, Yen teaches retention of the first isolation layer would reasonably apply in situations of alternative material compositions. Retaining the first and second isolation layers of the combination of Yen, Ping, Ryu, Cho, and Zou in the same way when stripping the inner oxide of Yen would arrive at the claimed selectivity.
Response to Arguments
Applicant's arguments filed 5/27/2026 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to amended claim 1 that “Ping does not disclose that a top surface of the dielectric layer 300 is in contact with the insulation layer 700. As such, Ping does not disclose “the top surface of the inner oxide layer and a top surface of the outer oxide laver are in contact with the isolation structure.””. Remarks at pg. 12
Examiner’s reply:
The examiner does not find the argument persuasive. Yen is relied upon to teach the inner oxide layer (Yen: Fig. 1I: 110) configured among a gate. Ping is relied upon to teach a modification of the gate, by incorporating the upper gate wrapped by the outer oxide layer (Ping: Fig. 10: upper gate 400 and outer oxide layer 300). Ping is not relied upon to teach an alternative geometry or modification of the inner oxide layer. Rather, the geometry and arrangement of Yen’s inner oxide layer is retained around the modified gate. For example: Yen’s inner oxide layer (110) has a top surface directly contacting the isolation structure (111).
Regarding “a top surface of the outer oxide layer…in contact with the isolation structure”: the claim as written reasonably includes arrangements and shapes of parts beyond those explicitly disclosed by Applicant, because “contact” may reasonably include direct or indirect contact, and may reasonably include contact at the edge/endpoint of a surface (as shown in Ping: Fig. 10) or at a planar-shaped interface (as shown in Ryu: Fig. 6). Further, the arrangement of the contended “top surface” as claimed may reasonably include arrangements beyond the arrangement explicitly disclosed by Applicant. Thus, the rejection is maintained in substantially the same way as before, though has been updated as necessitated by the claim amendments and to promote clarity of the record.
Applicant argues:
Applicant argues with respect to amended claim 1 that “As shown in Fig. 6 of Ryu, a top surface of the gate electric layer 106 is not in contact with the capping layer 111. As such, Ryu does not disclose “the top surface of the inner oxide layer and a top surface of the outer oxide layer are in contact with the isolation structure.””. Remarks at pg. 13.
Examiner’s reply:
The examiner does not find the argument persuasive. Yen is relied upon to teach the inner oxide layer (Yen: Fig. 1I: 110) configured among a gate. Ryu is relied upon to teach a modification of the gate, by incorporating a barrier layer beneath the outer oxide layer (Ryu: Fig. 6: barrier 121/107 and outer oxide layer 109). Ryu is not relied upon to teach an alternative geometry or modification of the inner oxide layer or the outer oxide layer. Rather, the geometry and arrangement of Yen’s inner oxide layer is retained around the modified gate. For example: Yen’s inner oxide layer (110) has a top surface directly contacting the isolation structure (111).
Regarding “a top surface of the outer oxide layer…in contact with the isolation structure”: the claim as written reasonably includes arrangements and shapes of parts beyond those explicitly disclosed by Applicant, because “contact” may reasonably include direct or indirect contact, and may reasonably include contact at the edge/endpoint of a surface or at a planar-shaped interface. Further, the arrangement of the contended “top surface” as claimed may reasonably include arrangements beyond the arrangement explicitly disclosed by Applicant. Thus, the rejection is maintained in substantially the same way as before, though has been updated as necessitated by the claim amendments and to promote clarity of the record.
Applicant argues:
Applicant argues with respect to amended claim 16 that “As shown in Fig. 1F of Yen, an upper surface of the insulating cap layer 122 and sidewalls and an upper surface of the semiconductor substrate 100 within the second and third trenches 150 and 152 collectively form a step surface, not a flat surface. As such, Yen does not disclose “the top surface of the isolation structure and the second top surface of the semiconductor substrate collectively form a flat bottom surface of the recess,...and the flat bottom surface of the recess extends from a first location directly above a first one of the two word line structures to a second location directly above a second one of the two word line structures.””. Remarks at pg. 16.
Examiner’s reply:
The examiner does not find Applicant’s arguments persuasive. The examiner finds the claim amendment attempting to differentiate Applicant’s disclosed “flat bottom surface” from the surface found in the prior art. However, the claim as written reasonably includes shapes beyond the shapes explicitly disclosed by Applicant. Thus, the rejection is maintained in substantially the same way as before, though has been updated as necessitated by the claim amendments and to promote clarity of the record.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
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