DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Acknowledgement is made of the amendment received on 10/19/2025. Claims 1-4, 6-8, 11-13, and 21-30 are pending in this application. Claims 1, 8, 21, and 25 are amended. Claims 5 and 9-10 are canceled. Claims 28-30 are new.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6-7, and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Ju (US 2021/0135011) in view of Kwon et al. (US 2013/0175635; hereinafter ‘Kwon’) and Dentoni Litta et al. (US 2021/0028068; hereinafter ‘Dentoni Litta’).
Regarding claim 1, Ju teaches a method for forming a semiconductor device structure ([0007-0008]), comprising:
forming nanostructures (104b-104d, FIG. 2B, [0030, 0067]; hereinafter ‘NS’) in a first region (a region in 106A; hereinafter ‘FR’) and a second region (a region in 106B; hereinafter ‘SR’) over a substrate (100, [0020]);
forming a gate dielectric layer (150, FIG. 2K, [0082]; hereinafter ‘150GDL’) surrounding the nanostructures (NS);
forming dummy structures (120A and 120B, FIGS. 2D and 3A, [0038]) between the nanostructures (NS);
forming a dielectric layer (116, FIGS. 2D, [0038]) over the nanostructures (NS);
forming a dielectric structure (134, FIG. 3E, [0048]) between the nanostructures (NS) in the first region (FR) and nanostructures (NS) in the second region (SR);
removing the dummy structures (120A, FIGS. 2G and 3K, [0066]) in the first region (FR);
depositing a first work function layer (152 in the left 142, FIGS. 2K and 3O, [0081]; hereinafter ‘152L’) over the nanostructures (NS);
removing the dummy structures (120B, FIGS. 2G and 3K) in the second region (SR); and
depositing a second work function layer (152 in the right 142; hereinafter ‘152R’) over the nanostructures (NS).
Ju does not teach the method for forming a semiconductor device structure, comprising: forming a dielectric structure to form a wall structure including the dielectric layer and the dielectric structure, removing the first work function layer in the second region, and the second work function layer protrudes toward the wall structure.
Kwon teaches a method for forming a semiconductor device structure (FIG. 5, [0015]), comprising: removing the first work function layer in the second region (removing 34L over 12B, [0056]).
As taught by Kwon, one of ordinary skill in the art would utilize and modify the above teaching into Ju to obtain and achieve the method for forming a semiconductor device structure, comprising: removing the first work function layer and the dummy structures in the second region; and depositing a second work function layer over the nanostructures as claimed, because depositing the first metal across the entire area, then selectively removing it, reduces process steps, lowers alignment error risks, and simplifies dual metal gate fabrication overall [0005, 0009].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kwon in combination with Ju due to above reason.
Ju in view of Kwon does not teach the method for forming a semiconductor device structure, comprising: forming a dielectric structure to form a wall structure including the dielectric layer and the dielectric structure and the second work function layer protrudes toward the wall structure.
Dentoni Litta teaches a method for forming a method for forming a semiconductor device structure [0002], comprising: forming a dielectric structure (120, Fig. 4, [0090]) to form a wall structure (a wall including 120 and 116, [0088, 0095]; hereinafter ‘W’) including the dielectric layer (116) and the dielectric structure (120) and the second work function layer (138 in 10, Fig. 10, [0099]) protrudes toward the wall structure (W, shown in Fig. 10).
As taught by Dentoni Litta, one of ordinary skill in the art would utilize and modify the above teaching into Ju in view of Kwon to obtain and achieve the method for forming a semiconductor device structure, comprising: forming a dielectric structure to form a wall structure including the dielectric layer and the dielectric structure and the second work function layer protrudes toward the wall structure as claimed, because the wall structure protects the boundary between semiconductor regions subjected to different processing conditions, forming the wall using two dielectric components provides enhanced isolation and increased process margin at the interface [0095], and it enables lateral shielding for the work function layer by the wall structure during selective etching of an adjacent gate region [0100].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Dentoni Litta in combination with Ju in view of Kwon due to above reason.
Regarding claim 2, Ju in view of Kwon and Dentoni Litta teaches the method for forming the semiconductor device structure as claimed in claim 1, further comprising: recessing the dielectric layer after removing the dummy structures in the first region (Ju: recessing 116 after removing 120A, FIG. 3K).
Regarding claim 3, Ju in view of Kwon and Dentoni Litta teaches the method for forming the semiconductor device structure as claimed in claim 1, wherein the dielectric layer and the dielectric structure are made of different materials (Ju: 116 is made of silicon oxide and 150DS is made of hafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-alumina alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, [0038, 0082]).
Regarding claim 6, Ju in view of Kwon and Dentoni Litta teaches the method for forming the semiconductor device structure as claimed in claim 1, further comprising: depositing a dummy layer (Ju: 124, FIGS. 2D and 3A, [0039]) over the nanostructures and the dummy structure (124 over NS and 120A and 120B).
Regarding claim 7, Ju in view of Kwon and Dentoni Litta teaches the method for forming the semiconductor device structure as claimed in claim 1, wherein the first work function layer surrounds the nanostructures in the first region (Ju: 152L surrounds NS in FR, FIGS. 2K and 3O), and the second work function layer surrounds the nanostructures in the second region (152R surrounds NS in SR).
Regarding claim 28, Ju in view of Kwon and Dentoni Litta teaches the method for forming the semiconductor device structure as claimed in claim 1, Ju in view of Kwon does not teach the method wherein the first work function layer protrudes toward the wall structure.
Dentoni Litta teaches the method wherein the first work function layer (138 in 20, Fig. 10, [0099]) protrudes toward the wall structure (W, shown in Fig. 10).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Dentoni Litta to obtain and achieve the method wherein the first work function layer protrudes toward the wall structure as claimed, because it enables lateral shielding for the work function layer by the wall structure during selective etching of an adjacent gate region [0100].
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Ju (US 2021/0135011) in view of Kwon (US 2013/0175635) and Dentoni Litta (US 2021/0028068), and further in view of Miura et al. (US 2021/0082766; hereinafter ‘Miura’).
Regarding claim 4, Ju in view of Kwon and Dentoni Litta teaches the method for forming the semiconductor device structure as claimed in claim 1, but does not teach the method for forming the semiconductor device structure further comprising: forming a blocking structure through the dielectric structure, wherein the blocking structure is narrower than the dielectric structure .
Miura teaches a method for forming a semiconductor device structure (FIG. 1A, [0018]), further comprising: forming a blocking structure (7, [0061]) through the dielectric structure (23, [0068, 0080]), wherein the blocking structure is narrower than the dielectric structure (7 is narrower than 23).
As taught by Miura, one of ordinary skill in the art would utilize and modify the above teaching into Ju in view of Kwon and Dentoni Litta to obtain and achieve the method for forming a semiconductor device structure, further comprising: forming a blocking structure through the dielectric structure, wherein the blocking structure is narrower than the dielectric structure as claimed, because the blocking structure is intentionally placed to electrically and physically isolate two neighboring nanostructures, preventing interference and ensuring gate structure separation [0061].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Miura in combination with Ju in view of Kwon and Dentoni Litta due to above reason.
Claims 8, 11, and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Ju (US 2021/0135011) in view of Dentoni Litta (US 2021/0028068).
Regarding claim 8, Ju teaches a method for forming a semiconductor device structure ([0007-0008]), comprising:
forming first nanostructures (104b-104d in 106A, FIG. 2B, [0030, 0067]; hereinafter ‘NSA’) and second nanostructures (104b-104d in 106B; hereinafter ‘NSB’) over a substrate (100, [0020]);
forming a dummy structure (120A, 120B, and 102b-102d, FIGS. 2D and 3A, [0023, 0038]) over and between the first nanostructures (NSA) and the second nanostructures (NSB);
removing the dummy structure (120A and 120B, FIGS. 2G and 3K, [0066]) over the first nanostructures (NSA) and the second nanostructures (NSB);
depositing a dielectric layer (116, FIGS. 2D, [0038]) between the first nanostructures (NSA) and the second nanostructures (NSB);
forming a dielectric structure (134, FIG. 3E, [0048]) over the dielectric layer (116);
removing the dummy structure (102b-102d, FIGS. 2H and 3L) between the first nanostructures (NSA);
forming a first gate structure (156A, FIGS. 2K and 3O, [0080]) surrounding the first nanostructures (NSA), wherein the first gate structure (156A) comprises a first work function layer (152, [0081]; hereinafter ‘152L’);
removing the dummy structural (102b-102d, FIGS. 2H and 3L) between the second nanostructures (NSB);
forming a second gate structure (156B) surrounding the second nanostructures (NSB).
Ju does not teach the method for forming a semiconductor device structure, comprising: forming a dielectric structure to form a wall structure including the dielectric layer and the dielectric structure and a sidewall of the first work function layer interfaces a first sidewall of the wall structure.
Dentoni Litta teaches a method for forming a method for forming a semiconductor device structure [0002], comprising: forming a dielectric structure (120, Fig. 4, [0090]) to form a wall structure (a wall including 120 and 116, [0088, 0095]; hereinafter ‘W’) including the dielectric layer (116) and the dielectric structure (120) and a sidewall of the first work function layer (a sidewall portion of 138 in 20, Fig. 11, [0099]) interfaces a first sidewall of the wall structure (a left sidewall of W, shown in Fig. 11).
As taught by Dentoni Litta, one of ordinary skill in the art would utilize and modify the above teaching into Ju to obtain and achieve the method for forming a semiconductor device structure, comprising: forming a dielectric structure to form a wall structure including the dielectric layer and the dielectric structure and the second work function layer protrudes toward the wall structure as claimed, because the wall structure protects the boundary between semiconductor regions subjected to different processing conditions, forming the wall using two dielectric components provides enhanced isolation and increased process margin at the interface [0095], and it enables lateral shielding for the work function layer by the wall structure during selective etching of an adjacent gate region [0100].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Dentoni Litta in combination with Ju due to above reason.
Regarding claim 11, Ju in view of Dentoni Litta teaches the method for forming the semiconductor device structure as claimed in claim 8, Ju does not teach the method further comprising: forming a dummy layer over the first nanostructures, the second nanostructure, and the dielectric structure.
Dentoni Litta teaches the method further comprising: forming a dummy layer (140, Fig. 11, [0100]) over the first nanostructures (134 in 20, Fig. 10, [0038, 0099]; hereinafter ‘13420’), the second nanostructure (134 in 10; hereinafter ‘13410’), and the dielectric structure (120).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Dentoni Litta to obtain and achieve the method further comprising: forming a dummy layer over the first nanostructures, the second nanostructure, and the dielectric structure as claimed, because it enables an additional selective etch process for removing the first work function layer from a selected semiconductor region [0100].
Regarding claim 29, Ju in view of Dentoni Litta teaches the method for forming the semiconductor device structure as claimed in claim 8, wherein the second gate structure (Ju: 156B, FIGS. 2K and 3O) comprises a second work function layer (152, [0081]; hereinafter ‘152R’).
Ju does not teach the method wherein a sidewall of the second work function layer interfaces a second sidewall of the wall structure.
Dentoni Litta teaches the method wherein a sidewall of the second work function layer (a sidewall portion of 138 in 10, Fig. 11, [0099]) interfaces a first sidewall of the wall structure (a right sidewall of W, shown in Fig. 11).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Dentoni Litta to obtain and achieve the method wherein a sidewall of the second work function layer interfaces a second sidewall of the wall structure as claimed, because it enables lateral shielding for the work function layer by the wall structure during selective etching of an adjacent gate region [0100].
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Ju (US 2021/0135011) in view of Dentoni Litta (US 2021/0028068), and further in view of Kanakasabapathy et al. (US 2021/0017643; hereinafter ‘Kanakasabapathy’).
Regarding claim 13, Ju in view of Dentoni Litta teaches the method for forming the semiconductor device structure as claimed in claim 11, but does not teach the method for forming the semiconductor device structure wherein the dummy layer and the dummy structure are made of the same material.
Kanakasabapathy teaches a method for the semiconductor device structure ([0004, 0098]) wherein the dummy layer (hard mask) and the dummy structural (sacrificial layer) are made of the same material (hard mask and sacrificial layer are the same material).
As taught by Kanakasabapathy, one of ordinary skill in the art would utilize and modify the above teaching into Ju in view of Dentoni Litta to obtain and achieve the method for the semiconductor device structure wherein the dummy layer and the dummy material are made of the same material as claimed, because using identical materials for the dummy layer and the dummy material enables their simultaneous removal, the manufacturing process is simplified [0098].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kanakasabapathy in combination with Ju in view of Dentoni Litta due to above reason.
Claims 21, 24-25, and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Ju (US 2021/0135011) in view of Yang et al. (US 2022/0173097; hereinafter ‘Yang’).
Regarding claim 21, Ju teaches a method for forming a semiconductor device structure ([0009]), comprising:
forming first nanostructures (104b-104d in 106A, FIG. 2B, [0030, 0067]; hereinafter ‘NSA’) and second nanostructures (104b-104d in 106B; hereinafter ‘NSB’) over a substrate (100, [0020]);
forming a wall structure (136, FIG. 3F, [0049]);
forming a first gate structure (156A, FIGS. 2K and 3O, [0080-0081]) surrounding the first nanostructures (NSA) and over the wall structure (136), wherein a top surface of the wall structure (the top surface of uppermost 136) is lower than a top surface of the topmost nanostructure of the first nanostructures (the top surface of 104d); and
forming a second gate structure (156B) surrounding the second nanostructures (NSB) and over the wall structure (136).
Ju does not teach the method comprising: forming a wall structure between the first nanostructures and the second nanostructures, wherein a top surface of the wall structure is higher than a bottom surface of a topmost nanostructure of the first nanostructures.
Yang teaches a method (FIGS. 3 and 25, [0144]) comprising:
forming a wall structure (150C, [0035]) between the first nanostructures (NSS over F1, [0025]; hereinafter ‘NSS1’) and the second nanostructures (NSS over F2; hereinafter ‘NSS2’), wherein a top surface of the wall structure (a top surface of 150C) is higher than a bottom surface of a topmost nanostructure of the first nanostructures (a bottom surface of N3 of NSS1).
As taught by Yang, one of ordinary skill in the art would utilize and modify the above teaching into Ju to obtain and achieve the method comprising: forming a wall structure between the first nanostructures and the second nanostructures, wherein a top surface of the wall structure is higher than a bottom surface of a topmost nanostructure of the first nanostructures as claimed, because the inter-region wall structure allows selective isolation of the gate at a lower portion between the first and second nanostructure while maintaining gate continuity above the wall [0041, 0045].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Yang in combination with Ju due to above reason.
Regarding claim 24, Ju in view of Yang teaches the method for forming the semiconductor device structure as claimed in claim 21, wherein the first gate structure (Ju: 156A, FIGS. 2K and 3O) comprises a first work function layer (152, [0081]; herein after ‘152L’), and the first work function layer covers a first portion of a top surface of the wall structure (152L covers the side surface of 136).
Regarding claim 25, Ju in view of Yang teaches the method for forming the semiconductor device structure as claimed in claim 24, wherein the second gate structure (Ju: 156B, FIGS. 2K and 3O) comprises a second work function layer (152, [0081]; hereinafter ‘152R’), and the first work function layer covers a second portion of the top surface of the wall structure (152R covers the side surface of 136).
Regarding claim 30, Ju in view of Yang teaches the method for forming the semiconductor device structure as claimed in claim 21, Ju does not teach the method wherein the wall structure covers sidewalls of the first nanostructures and the second nanostructures (Ju: 136 covers the sidewalls of NSA and NSB, FIG. 3O).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Ju (US 2021/0135011) in view of Yang (US 2022/0173097), and further in view of Cheng et al. (US 2020/0027959; hereinafter ‘Cheng’).
Regarding claim 22, Ju in view of Yang teaches the method for forming the semiconductor device structure as claimed in claim 21, but does not teach the method wherein the wall structure comprises a first dielectric layer and a second dielectric layer surrounded by the first dielectric layer.
Cheng teaches a method for forming a semiconductor device structure (FIG. 14, [0021]) wherein a wall structure (26 and 44, [0052, 0064]) comprises a first dielectric layer (44) and a second dielectric layer (26) surrounded by the first dielectric layer (44).
As taught by Cheng, one of ordinary skill in the art would utilize and modify the above teaching into Ju in view of Su to obtain and achieve the method for forming a semiconductor device structure wherein a wall structure comprises a first dielectric layer and a second dielectric layer surrounded by the first dielectric layer as claimed, because the first dielectric layer formed adjacent to the second dielectric layer physically separates and protects the second spacer during contact formation, preventing direct gate-to-contact interaction [0062-0063].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Cheng in combination with Ju in view of Su due to above reason.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Ju (US 2021/0135011) in view of Yang (US 2022/0173097) and Cheng (US 2020/0027959), and further in view of Koldiaev et al. (US 2005/0040479; hereinafter ‘Koldiaev’).
Regarding claim 23, Ju in view of Yang and Cheng teaches the method for forming the semiconductor device structure as claimed in claim 22, but does not teach the method wherein the first dielectric layer and the second dielectric layer are made of different materials.
Koldiaev teaches a method for forming a semiconductor device structure [0054] comprising the wall structure (2, FIG. 16, [0059]) wherein the first dielectric layer (16 having oxide layer, FIG. 13, [0056]) and the second dielectric layer (18 having silicon nitride layer, FIG. 14, [0057]) are made of different materials.
As taught by Koldiaev, one of ordinary skill in the art would utilize and modify the above teaching into Ju in view of Yang and Cheng to obtain and achieve the method for forming a semiconductor device structure comprising the wall structure wherein the first dielectric layer and the second dielectric layer are made of different materials as claimed, because the oxide layer is required to isolate the silicon surface form nitride-induced stress, while the nitride layer is required to provide etch selectivity for spacer width control, and the combination of the oxide layer and the nitride layer enables both functions to be achieved within the spacer structure [0032, 0038].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Koldiaev in combination with Ju in view of Yang and Cheng due to above reason.
Claims 26-27 are rejected under 35 U.S.C. 103 as being unpatentable over Ju (US 2021/0135011) in view of Yang (US 2022/0173097), and further in view of Kwon (US 2013/0175635).
Regarding claim 26, Ju in view of Yang teaches the method for forming the semiconductor device structure as claimed in claim 25, but does not teach the method for forming the semiconductor device structure wherein the second work function layer covers the first work function layer.
Kwon teaches a method for forming a semiconductor device structure (FIG. 6, [0016]) wherein the second work function layer (38L, [0057]) covers the first work function layer (38L covers 34L).
As taught by Kwon, one of ordinary skill in the art would utilize and modify the above teaching into Ju in view of Yang to obtain and achieve the method for forming a semiconductor device structure, wherein the second work function layer covers the first work function layers as claimed, because it enables forming a dual-work-function transistor, where two different gate metals are used to independently tune the threshold voltages of both p-type and n-type devices [0061].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kwon in combination with Ju in view of Yang due to above reason.
Regarding claim 27, Ju in view of Yang teaches the method for forming the semiconductor device structure as claimed in claim 25, but does not teach the method for forming the semiconductor device structure wherein the second work function layer covers a top surface of the first nanostructures.
Kwon teaches a method for forming a semiconductor device structure (FIG. 6, [0016]) wherein the second work function layer (38L, [0057]) covers a top surface of the first nanostructures (38L covers a top surface of over 12A, [0029])
As taught by Kwon, one of ordinary skill in the art would utilize and modify the above teaching into Ju in view of Yang to obtain and achieve the method for forming a semiconductor device structure, wherein the second work function layer covers a top surface of the first nanostructures as claimed, because it enables forming a dual-work-function transistor, where two different gate metals are used to independently tune the threshold voltages of both p-type and n-type devices [0061].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kwon in combination with Ju in view of Yang due to above reason.
Allowable Subject Matter
Claim 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The applied prior art neither anticipates nor renders the claimed subject matter obvious because it fails to teach the claimed method of making a semiconductor device structure,
“removing the dummy layer over the first nanostructures when removing the dummy structure between the first nanostructures; and
removing the dummy layer over the second nanostructure when removing the dummy structure between the second nanostructure” in combination with all other limitations, as recited in claim 12.
Claim 12 is objected as being dependent from claim 8.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 1/28/26