DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 28 is objected to because of the following informalities: “the first plurality of bonding layers comprises a first plurality of bonding pad structures” should read -- the first plurality of bonding layers comprises the first plurality of bonding pad structures—(emphasis added) since “a first plurality of bonding pad structures” is previously recited in the claim. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21-23, 25 and 27-32 are rejected under 35 U.S.C. 103 as being unpatentable over Wan et al. (of record, US 20140042298 A1) in view of Kwon (of record, US 20190123088 A1) and Lee et al. (US 20160056200 A1).
Regarding claim 21, Wan discloses (Figs. 9 and 10) a device structure, comprising:
a first die (200/202) comprising a first substrate (220) and a first interconnect structure (unlabeled) disposed over the first substrate;
a second die (100/102) comprising a second substrate (120) and a second interconnect structure (unlabeled) disposed over the second substrate; and
a third die (20/22) comprising a third interconnect structure (at least 34) and a third substrate (26) disposed over the third interconnect structure,
wherein the first interconnect structure is bonded to the second substrate by way of a first plurality of bonding layers (annotated below)
wherein the second interconnect structure is bonded to the third interconnect structure by way of a second plurality of bonding layers (annotated above),
wherein the third substrate comprises a plurality of photodiodes (24), a first transistor (28) disposed over the third substrate, and a plurality of floating diffusion regions (32) adjacent the plurality of photodiodes,
wherein the second die (Fig. 10) comprises:
a second transistor (130) having a source electrically (indirectly at least) connected to a drain of the first transistor (28),
a third transistor (128) having a gate electrically connected (indirectly at least) to the drain of the first transistor (28) and the source of the second transistor (130), and
a fourth transistor (126) having a drain electrically connected (indirectly at least) to a source of the third transistor (128),
wherein the first plurality of bonding layers comprise a first bonding layer (annotated below) adjacent the first interconnect structure and a second bonding layer (annotated below) adjacent the second substrate,
wherein the first bonding layer comprises a first plurality of bonding pad structures (annotated below) disposed at a first pitch (Pitch A),
wherein the second bonding layer comprises a second plurality of bonding pad structures (annotated below) disposed at the first pitch (Pitch A),
wherein the plurality of floating diffusion regions (32) are disposed at a second pitch (Pitch B) different from the first pitch,
wherein the second plurality of bonding layers comprises a third plurality of bonding pad structures (annotated) disposed at the second pitch (Pitch B) (Note: per MPEP 2125, the pitch of 32 appears to be the same of the third plurality of bonding pad structures; both having Pitch B. Alternatively, in the event the pitch of 32 is not the same of the third plurality of bonding pad structures, which the examiner does not concede, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to ensure a common pitch as claimed is included in Wan so as to ensure the floating diffusion regions are interconnected to elements in the second die with short and vertical routing features).
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Wan fails to disclose (a) wherein four of the plurality of photodiodes are arranged in a square formation to center around one of the plurality of floating diffusion regions, and, (b) wherein the plurality of photodiodes are separated by deep trench isolation (DTI) features, wherein the DTI features comprise a metal liner and a fill material.
Regarding (a), Kwon discloses (Fig. 2B) wherein four of the plurality of photodiodes (PD1-PD4) are arranged in a rectangle formation (MPEP 2125) to center around one of the plurality of floating diffusion regions (FD, Fig. 2B, [0048] – “For example, the shared pixel SP may have a structure in which four photodiodes PD1 to PD4 surround and share one floating diffusion area FD.”).
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It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the photodiode and floating diffusion arrangement of Kwon in Wan so as to maximize the number of photodiodes while reducing the number of floating diffusion areas and the number of transistors associated with said photodiodes (Kwon, [0046-0050]).
Wan/Kwon discloses wherein four of the plurality of photodiodes (PD1-PD4) are arranged in a rectangular formation (MPEP 2125, Fig. 2B) but fails to disclose “a square formation”.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to arrive at a square formation in Wan/Kwon so as to maximize the number of photodiodes while reducing the number of floating diffusion areas and the number of transistors associated with said photodiodes (Kwon, [0046-0050]) and/or because it has been held that such modification would have involved a mere change in size/shape of a component which is prima-facie obvious. See MPEP 2144.04 IV.
Regarding (b), Lee discloses wherein the plurality of photodiodes (121 to 124) are separated by deep trench isolation (DTI) features (131 to 134, Fig. 3), wherein the DTI features comprise a
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the DTI arrangement of Lee in Wan/Kwon and arrive at the claimed structure so as to “prevent an electrical crosstalk phenomenon” (Lee, [0061]).
Wan/Kwon/Lee fail to disclose a metal liner instead of the “high-reflectance” liner of 137.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to select a metal because metals are well-known to comprise high reflectivity and therefore “prevent an electrical crosstalk phenomenon” (Lee, [0061]).
Regarding claim 22, Wan/Kwon/Lee discloses wherein each of the third plurality of bonding pad structures (Fig. 9 annotated above) is vertically aligned (definition below) with one of the plurality of floating diffusion region (32, Fig. 9. See https://www.thefreedictionary.com/align; To adjust (parts of a mechanism, for example) to produce a proper relationship or orientation).
Regarding claim 23, Wan/Kwon/Lee discloses wherein the second pitch (Pitch B) is smaller than the first pitch (Pitch A, Fig. 9 above).
Regarding claim 25, Wan/Kwon/Lee fails to wherein a ratio of the second pitch to the first pitch is between about 0.2 and about 0.75.
However, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to arrive at a value within the claimed ranges in the device of Wan/Kwon/Lee so as to allow for maximizing the number of photodiodes in the third die which affects the second pitch (B) while maintaining circuitry capable of addressing said photodiodes in separate dies which affects the first pitch (A), and/or, as a matter of routine experimentation (MPEP 2144.05).
Regarding claim 27, Wan/Kwon/Lee discloses wherein the second die comprises a plurality of through-substrate-vias (TSVs) (146) extending through the second substrate (120, Fig. 9) to interface the second plurality of bonding pad structures (which are at the respective ends of each 146).
Regarding claim 28, Wan discloses (Figs. 9-10) a device structure, comprising:
a logic die (200/202) comprising a first substrate (220) and a first interconnect structure (unlabeled) disposed over the first substrate;
a pixel device die (100/102) comprising a second substrate (120) and a second interconnect structure (unlabeled) disposed over the second substrate; and
a pixel die (20/22) comprising a third interconnect structure (at least 34) and a third substrate (26) disposed over the third interconnect structure,
wherein the first interconnect structure is bonded to the second substrate by way of a first plurality of bonding layers (annotated below),
wherein the first plurality of bonding layers comprise a first plurality of bonding pad structures (annotated below),
wherein the second interconnect structure is bonded to the third interconnect structure by way of a second plurality of bonding layers (annotated below),
wherein the third substrate comprises a plurality of photodiodes (24), a first transistor (28) disposed over the third substrate, and a plurality of floating diffusion regions (32) adjacent the plurality of photodiodes,
wherein the pixel device die (Fig. 10) comprises:
a second transistor (130) having a source electrically (indirectly at least) connected to a drain of the first transistor (28),
a third transistor (128) having a gate electrically connected (indirectly at least) to the drain of the first transistor and the source of the second transistor, and
a fourth transistor (126) having a drain electrically connected (indirectly at least) to a source of the third transistor,
wherein the plurality of floating diffusion regions (32) are disposed at a first pitch (B),
wherein the first plurality of bonding layers comprises a first plurality of bonding pad structures (annotated below) disposed at a second pitch (A) different from the first pitch (Fig. 9 below).
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Wan does not disclose (a) wherein each of the plurality of floating diffusion regions is surrounded and shared by four of the plurality of photodiodes and (b) wherein the plurality of photodiodes are separated by deep trench isolation (DTI) features, wherein each of the plurality of floating diffusion regions is aligned with one of the DTI features.
Regarding (a), Kwon discloses (Fig. 2B) wherein each of the plurality of floating diffusion regions (FD) is surrounded and shared by four of the plurality of photodiodes (PD1-PD4, Fig. 2B, [0048] – “For example, the shared pixel SP may have a structure in which four photodiodes PD1 to PD4 surround and share one floating diffusion area FD.”).
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It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the photodiode and floating diffusion arrangement of Kwon in Wan so as to maximize the number of photodiodes while reducing the number of floating diffusion areas and the number of transistors associated with said photodiodes (Kwon, [0046-0050]).
Regarding (b), Lee discloses (Fig. 3) wherein the plurality of photodiodes (121 to 124) are separated by deep trench isolation (DTI) features (131 to 134), wherein each of the plurality of floating diffusion regions (160, plurality per “unit pixels 1 according to embodiments of the present inventive concepts may constitute the pixel array 810 of FIG. 1”) is aligned (broad term per https://www.thefreedictionary.com/aligned) with (at least) one of the DTI features (Fig. 3).
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It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the DTI arrangement of Lee in Wan/Kwon and arrive at the claimed structure so as to “prevent an electrical crosstalk phenomenon” (Lee, [0061]).
Regarding claim 29, Wan/Kwon/Lee discloses wherein the second plurality of bonding layers comprise a second plurality of bonding pad structures (annotated) disposed at the first pitch (B, per MPEP 2125, pitch B appears to be in both 32 and the second plurality of bonding pad structures. Alternatively, in the event the pitch of 32 is not the same of the second plurality of bonding pad structures, which the examiner does not concede, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to ensure a common pitch as claimed is included in Wan/Kwon so as to ensure the floating diffusion regions are interconnected to elements in the second die with short and vertical routing features).
Regarding claim 30, Wan/Kwon/Lee discloses wherein each of the second plurality of bonding pad structures (annotated) is vertically aligned (definition below) with one of the plurality of floating diffusion regions (32, Fig. 9. See https://www.thefreedictionary.com/align; To adjust (parts of a mechanism, for example) to produce a proper relationship or orientation).
Regarding claim 31, Wan/Kwon/Lee discloses wherein the plurality of photodiodes (24) are disposed at a third pitch smaller than the second pitch (A; Fig. 9, the pitch between 24 is less than A).
Regarding claim 32, Wan/Kwon/Lee discloses wherein the plurality of photodiodes (PD1-PD4) are grouped into a plurality of clusters (SP, Figs. 2A-2B), and wherein each of the plurality of clusters comprises four of the plurality of photodiodes (four PDs in Fig. 2B) surrounding one of the plurality of floating diffusion regions (FD, Fig. 2B).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Wan et al. (of record, US 20140042298 A1) in view of Kwon (of record, US 20190123088 A1) and Lee et al. (US 20160056200 A1) as applied to claim 21 above, and further in view of Hwang (of record, US 20090065828 A1).
Regarding claim 24, Wan/Kwon/Lee fails to disclose wherein the third substrate and the plurality of floating diffusion regions are doped with an n-type dopant, and wherein a concentration of the n-type dopant in the plurality of floating diffusion regions is greater than a concentration of the n-type dopant in the third substrate.
Hwang discloses wherein a substrate (100, [0029] – “can be a substrate doped with p-type impurities or n-type impurities” and/or including 143, [0033] – “N- (143 “) and a floating diffusion region (FD/131, [0037] - “floating diffusion FD 131, which is an N+ junction”) are doped with an n-type dopant, and wherein a concentration of the n-type dopant in the floating diffusion region (as N+) is greater than a concentration of the n-type dopant in the substrate (as N or N-, Figs. 1-2).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the dopant arrangement of Hwang in Wan/Kwon/Lee and arrive at the claimed invention so as to minimize dark current (Hwang, [0079]) and/or provide arrangements suitable for incorporating photodiodes and circuitry within the same substrate.
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Wan et al. (of record, US 20140042298 A1) in view of Kwon (of record, US 20190123088 A1) and Lee et al. (US 20160056200 A1) as applied to claim 21 above, and further in view of Yamada et al. (of record, US 20230254608 A1).
Regarding claim 26, Wan/Kwon/Lee fails to disclose wherein a gate structure of the first transistor extends into one of the plurality of photodiodes along a direction perpendicular to a top surface of the third substrate.
Yamada discloses (Fig. 2) wherein a first transistor (TG) extends into one of the plurality of photodiodes (PD) along a direction perpendicular to a top surface of the third substrate (11).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the arrangement of Yamada in Wan/Kwon/Lee and ensure a gate structure extends into the photodiode as claimed so as to facilitate transferring of charge between the floating diffusion region and the photodiode (Yamada, [0042] – “When the transfer transistor TG is turned on, the charge stored in the photodiode PD is transferred to the floating diffusion FD”).
Allowable Subject Matter
Claims 1-7 and 33 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record fails to disclose or suggest (claim 1) wherein the first plurality of bonding layers comprises a bonding dielectric layer interfacing the second substrate and a bonding contact disposed in the bonding dielectric layer, wherein the second die comprises a through-substrate-via (TSV) extending through the second substrate to contact the bonding contact as recited within the context of the claim; claims 2-7 and 33 are dependent claims.
Response to Arguments
Applicant's arguments filed 5.8.2026 have been fully considered but they are not persuasive.
The applicant alleges the prior art of record fails to disclose or suggest the claimed DTI features of claims 21 and 28. Lee et al. (US 20160056200 A1) is employed by the examiner to address the claimed DTI features of claims 21 and 28; see rejection above for details.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRES MUNOZ whose telephone number is (571)270-3346. The examiner can normally be reached 8AM-5PM Central Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571)270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Andres Munoz/Primary Examiner, Art Unit 2818
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