Prosecution Insights
Last updated: April 19, 2026
Application No. 18/155,682

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Non-Final OA §103
Filed
Jan 17, 2023
Examiner
PAGE, STEVEN MITCHELL CHR
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Winbond Electronics Corp.
OA Round
3 (Non-Final)
83%
Grant Probability
Favorable
3-4
OA Rounds
2y 4m
To Grant
92%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allow Rate
359 granted / 433 resolved
+14.9% vs TC avg
Moderate +9% lift
Without
With
+8.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
33 currently pending
Career history
466
Total Applications
across all art units

Statute-Specific Performance

§101
3.4%
-36.6% vs TC avg
§103
38.4%
-1.6% vs TC avg
§102
36.1%
-3.9% vs TC avg
§112
21.5%
-18.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 433 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1 and 3-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu et al. (US 20220278063 A1, hereinafter Hu) in view of Shih et al (US 10049877 B1, hereinafter Shih) With regards to claim 1, Hu discloses a semiconductor structure (FIGS. 4-7A) comprising: a substrate; (substrate 100, see FIG. 4) a plurality of first pads (pads 122) disposed on the substrate and separated from each other; (see FIG. 7A, which is an alternate embodiment of the base structure shown in FIG. 4) and a plurality of second pads (pads 121) disposed on the substrate and separated from each other, wherein each of the first pads is separated from each of the second pads, (see FIG. 7A, showing the separations) a top-view shape of the each of the first pads is different from a top-view shape of the each of the second pads, (see FIG. 7A, where the first pads are rectangular, and the second pads are square) and a portion of the first pads surrounds the same second pad, (See FIG. 7A, showing the surrounding of pads 121 via pads 122). However, Hu does not explicitly teach the first pads of the portion of the first pads are arranged in a circular ring-shape to enclose only one of the second pads. Shih teaches the first pads (layers 126) of the portion of the first pads are arranged in a circular ring-shape to enclose only one of the second pads. (layer 106, see FIG. 11A where the layers 126 only surround the layers 106) It would have been obvious to one of ordinary skill in the art to modify the device of hu to have the placement of the pads as recited in Shih, as both references are in the same field of endeavor. One of ordinary skill would appreciate that the shape can be used to reduce the patterned size and the spacing between the patterns. (see Col. 7, ll. 10-20) With regards to claim 3, Hu in view of Shih teaches the semiconductor structure according to claim 1. Hu further teaches wherein the first pads and the second pads are arranged in a first direction (up and down the page of FIG. 7A) and a second direction, (left and right of the page of FIG. 7A) and the first direction intersects with the second direction. (See FIG. 7A) With regards to claim 4, Hu in view of Shih teaches the semiconductor structure according to claim 3. Hu further teaches wherein two of the first pads are between adjacent two of the second pads arranged in the first direction. (see FIG. 7A, where the middle pads 122 are between two adjacent pads 121 that are in the innermost and outermost portions of the device) With regards to claim 5, Hu in view of Shih teaches the semiconductor structure according to claim 3. Hu further teaches, wherein a virtual straight line passing through a center point of adjacent two of the first pads arranged in the second direction does not pass through any one of the second pads. (See FIG. 7A, where a line drawn through the center of two pads does not pass through any other pad, as there is a large gap contained between every pad) With regards to claim 6, Hu in view of Shih teaches the semiconductor structure according to claim 3. Hu further teaches wherein a virtual straight line passing through a center point of adjacent two of the second pads arranged in the second direction does not pass through any one of the first pads. (See FIG. 7A, where a line drawn through the center of two pads does not pass through any other pad, as there is a large gap contained between every pad) With regards to claim 7, Hu in view of Shih teaches the semiconductor structure according to claim 1. Hu further teaches wherein the first pads and the second pads are derived from the same material layer.(See Paragraphs [0025]-[0026], where the first and second pads are made of the same material, metal) Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu et al. (US 20220278063 A1, hereinafter Hu) in view of Shih et al (US 10049877 B1, hereinafter Shih) With regards to claim 2, Hu in view of Shih teaches the semiconductor structure according to claim 1. However, while Hu teaches teach wherein the first pads have the same top-view shape, the second pads have the same top-view shape, (see FIG. 7A), Hu does not explicitly the top-view shape of the first pads is approximately triangular, and the top-view shape of the second pads is approximately circular. Hu does teach circular pads (see FIGS. 5-6, showing different circular shapes), which suggests a motivation to try different shapes. Therefore, it would have been obvious to one of ordinary skill in the art to modify the device of Hu to have the differently shaped pads, such as circles and triangles, as Hu has a direct suggestion that other shapes can be used (see Hu Paragraph [0032]). It should also be noted that the court held that the configuration of the claimed [device] was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed [device] was significant.). (See MPEP 2144.04 IV B. Changes in Shape) In the instant case, the current device would not perform differently with the relative dimensions than the prior art device, and thus is not patentably distinct. Therefore, it would have been obvious to one of ordinary skill in the art to modify the device of Hu to have the shape as recited in the above recited claim. Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu et al. (US 20220278063 A1, hereinafter Hu) in view of Shih et al (US 10049877 B1, hereinafter Shih), as applied to claim 1, and further in view of Gwak (US 20140273471 A1, hereinafter Gwak) With regards to claim 8, Hu in view of Shih teaches the semiconductor structure according to claim 1. However, Hu does not explicitly teach further comprising: a plurality of contact structures; a bit line structure disposed between adjacent two of the contact structures; and a plurality of capacitor structures, wherein the contact structures are closer to the substrate than the capacitor structures, the each of the first pads is located between a corresponding one of the contact structures and a corresponding one of the capacitor structures, and is electrically connected to the corresponding one of the contact structures and the corresponding one of the capacitor structures, and the each of the second pads is located between a corresponding one of the contact structures and a corresponding one of the capacitor structures, and is electrically connected to the corresponding one of the contact structures and the corresponding one of the capacitor structures. Gwak teaches a plurality of contact structures; (bit contacts BC) a bit line structure (bit line BL) disposed between adjacent two of the contact structures; and a plurality of capacitor structures, (capacitor 190) wherein the contact structures are closer to the substrate than the capacitor structures, (see FIG. 20, where the bit contacts BC directly contact the substrate 100/103) the each of the first pads (middle pads CP) is located between a corresponding one of the contact structures and a corresponding one of the capacitor structures, and is electrically connected to the corresponding one of the contact structures and the corresponding one of the capacitor structures, (see FIG. 20, showing the electrical connection) and the each of the second pads (outermost pads CP) is located between a corresponding one of the contact structures and a corresponding one of the capacitor structures, and is electrically connected to the corresponding one of the contact structures and the corresponding one of the capacitor structures. (see FIG. 20, showing the electrical connection) It would have been obvious to one of ordinary skill in the art to modify the device of Hu to have the memory structure of Gwak, as both references are in the same field of endeavor. One of ordinary skill would appreciate that using Gwak with hu has the benefit of forming fine patterns for better lithography in memory devices (see Gwak paragraph [0003]-[0004]) Response to Arguments Applicant's arguments filed 10/09/2025 have been fully considered but they are moot, as Examiner is using a new reference, Shih, to teach the circular surrounding shape. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN M Page whose telephone number is (571)272-3249. The examiner can normally be reached M-F: 10:00AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8548. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812
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Prosecution Timeline

Jan 17, 2023
Application Filed
Jul 11, 2025
Non-Final Rejection — §103
Oct 09, 2025
Response Filed
Oct 23, 2025
Final Rejection — §103
Dec 23, 2025
Request for Continued Examination
Jan 15, 2026
Response after Non-Final Action
Jan 26, 2026
Non-Final Rejection — §103
Mar 24, 2026
Interview Requested
Mar 25, 2026
Examiner Interview Summary
Mar 25, 2026
Applicant Interview (Telephonic)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604513
SEMICONDUCTOR DEVICE
2y 5m to grant Granted Apr 14, 2026
Patent 12581643
SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
2y 5m to grant Granted Mar 17, 2026
Patent 12575089
MEMORY DEVICE WITH TAPERED BIT LINE CONTACT
2y 5m to grant Granted Mar 10, 2026
Patent 12568611
MEMORY DEVICE WITH CELL PADS HAVING DIAGONAL SIDEWALLS
2y 5m to grant Granted Mar 03, 2026
Patent 12568845
CHIP SCALE SEMICONDUCTOR PACKAGE HAVING BACK SIDE METAL LAYER AND RAISED FRONT SIDE PAD AND METHOD OF MAKING THE SAME
2y 5m to grant Granted Mar 03, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
83%
Grant Probability
92%
With Interview (+8.6%)
2y 4m
Median Time to Grant
High
PTA Risk
Based on 433 resolved cases by this examiner. Grant probability derived from career allow rate.

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