Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Spitzlsperger et al., hereinafter Spitz (US 2016/0379936 A1) in view of in view of Feng et al. (US 2014/0357050 A1).
Regarding independent claim 14: Spitz teaches (e.g., Figs. 2A-2J; Figs. 3-4 are manufacturing flow charts; [0016]-[0017]) a method of manufacturing a semiconductor device, comprising:
providing a substrate ([0025]: 100) having a first surface (upper surface; [0031]: 100a) and a second surface (lower surface; [0031]: 100b) opposite to the first surface;
forming an isolation structure ([0025] and [0038]: 101 includes 101a; 101b) in the substrate at the first surface;
forming a first doped region (Fig. 2C; [0025], [0033], [0040] and [0055]: 103/104/105) along the first surface,
the isolation structure surrounding the first doped region (Fig. 2A-2C; [0025]-[0027], [0033] and [0051]: “while FIG. 2J shows only a cross-section of the deep trench and shallow trench isolations, one of ordinary skill in the art, will understand that such trenches form a continuous and contiguous isolation ring surrounding the LDMOS transistor”);
forming an interconnect structure ([0025], [0036] and [0043]-[0045]: 110/110a) within a dielectric layer ([0025]-[0026] and [0039]: 111) on the first surface (100a), the interconnect structure being coupled to the first doped region (103/104/105);
removing a portion of the substrate from the second surface to form a first trench ([0038]: forming first trench 146a from the lower side/backside) that exposes a portion of the isolation structure ([0038]: 101 includes 101a and 101b), and
removing another portion of the substrate from the second surface to form a second trench ([0038] and [0045]: forming a second trench 149 from the lower side/backside) that exposes a portion of the interconnect structure ([0043]-[0045] and [0054]: portion 110a/110 of the interconnect structure is exposed);
filling the first trench with a dielectric material ([0040]: dielectric material 132 ) and disposing the dielectric material conformally on a sidewall of the second trench ([0046]: 133); and
filling the second trench with a conductive material ([0046]: 134), wherein the conductive material is surrounded by the dielectric material ([0040], [0046] and [0051]: the dielectric material used in the filling the first trench and the second trench is ozone/TEOS).
Note Spitz teaches that that while FIG. 2J shows only a cross-section of the deep trench and shallow trench isolations, a skilled person will understand that such trenches form a continuous and contiguous isolation ring surrounding the LDMOS transistor ([0051]).
Spitz does not expressly teach concurrently filling the first trench with a dielectric material, and forming the dielectric material conformally on a sidewall of the second trench and on a part of the interconnect structure.
Feng teaches (e.g., Figs. 2-10) a method comprising
concurrently filling a first trench ([0015]: 20) with a dielectric material ([0015]: 24), and forming the dielectric material (24) conformally on a sidewall of a second trench ([0015]: 22) and on a part of an interconnect structure ([0016]-[0017]: 34).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the method of Splitz, the method of concurrently filling the first trench with a dielectric material, and forming the dielectric material conformally on a sidewall of the second trench and on a part of an interconnect structure, as taught by Feng, for the benefits of reducing the number of masking steps during the manufacturing process and thus increase manufacturing throughput.
Furthermore, it would have been obvious because all the claimed elements were known in the prior art and one skilled in the art before the effective filing date of the claimed invention, could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the filing date. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007). "If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person's skill." Id.
Regarding claim 18: Spitz teaches the claim limitation of the method of claim 14, on which this claim depends,
wherein the second trench filled with the conductive material forms a through silicon via (TSV) structure ([0046] and [0049]: 134) electrically coupled to the interconnect structure ([0043]: 110a).
Regarding claim 19: Spitz teaches the claim limitation of the method of claim 18, on which this claim depends,
wherein the first doped region is configured to be supplied a first potential voltage (Fig. 2C; [0025], [0033] and [0055]: the first doped region 103/104/105 is capable of being supplied a first potential voltage due to its inherent structure; see [0042], [0046] and [0049]) that is a same as a second potential voltage that is applied to the TSV structure ([0046]-[0048]: “accordingly, the drain connection of the [0048] LDMOS transistor is routed to the rear or backside of the wafer so that it can be connected to features accessible from the backside [0048] LDMOS transistor is routed to the rear or backside of the wafer so that it can be connected to features accessible from the backside; [0004]-[0005]).
Regarding claim 20: Spitz teaches the claim limitation of the method of claim 18, on which this claim depends,
wherein the first trench filled with the dielectric material (132) forms an insulating feature surrounding the TSV structure (134) and the first doped region (103/104/105).
Claims 21-23, 27 and 29-30 are rejected under 35 U.S.C. 103 as being unpatentable over Spitzlsperger et al., hereinafter Spitz (US 2016/0379936 A1) in view of in view of Carothers et al. (US 2017/0117356 A1).
Regarding independent claim 21: Spitz teaches (e.g., Figs. 2A-2J; Figs. 3-4 are manufacturing flow charts; [0016]-[0017]) a method of forming a semiconductor device, comprising:
forming one or more interconnects ([0025], [0036] and [0043]-[0045]: 110/110a) within a dielectric structure ([0025]-[0026] and [0039]: 111) along a first side (upper surface; [0031]: 100a) of a substrate ([0025]: 100);
etching a second side of the substrate ([0038] and [0045]: etching the lower side/backside 100b) to form a via opening ([0045]: 149) extending through the substrate to expose the one or more interconnects ([0043]-[0045] and [0054]: interconnects 110a/110 structure(s) is/are exposed), the second side of the substrate opposing the first side of the substrate (the backside of the substrate opposing the upper side);
etching the second side of the substrate to form one or more trenches ([0038]: etching the second side/lower side/backside of the substrate to form one or more trenches 146a) along opposing sides of the via opening;
forming an insulating material ([0040]: 132; material) within the one or more trenches; and
forming a conductive material ([0046]: 134) within the via opening.
Splitz does not expressly teach
etching the second side of the substrate to form one or more trenches that laterally surround the via opening along opposing sides in a cross-sectional view.
Carothers teaches (e.g., Figs. Figs. 6A-6D and Figs. 8A-8G; [0042] FIG. 6A through FIG. 6D are cross sections of the integrated circuit of FIG. 4, depicting successive stages of an example method of continued formation of the integrated circuit after the isolation structure is formed) a method comprising:
etching a second side of a substrate ([0031]: backside of substrate 402) to form one or more trenches ([0043]: 466; the trenches are not shown in Fig. 8A-8G; however, the process goes into forming trenches in the backside of the substrate; as a shown in Fig. 6B which is depicting Fig. 4; Fig. 4 shows preceding steps before etching process to form trench on the backside of the substrate) that laterally surround the via opening ([0061]: 894) along opposing sides in a cross-sectional view (Fig. 6B and Fig 8G).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the method of Splitz, the method of etching the second side of the substrate to form one or more trenches that laterally surround the via opening along opposing sides in a cross-sectional view, as taught by Carothers, for the benefits of more effectively isolate signal interferences from adjacent devices.
Regarding claim 22: Spitz teaches the claim limitation of the method of claim 21, on which this claim depends, further comprising:
Spitz as modified by Carothers teaches that the one or more trenches (Carothers: Fig. 6B-6D, Fig. 8A-8G: [0043]: 466) laterally surround the via opening (Carothers: Fig. 6B-6D, Fig. 8A-8G: [0061]: 894) along opposing sides in a second cross-sectional view that is taken along a direction that is perpendicular to the cross-sectional view in a top-view (Carothers: Fig. B, Fig. 8A-8G: [0043]: 466).
Regarding claim 23: Spitz teaches the claim limitation of the method of claim 22, on which this claim depends, further comprising:
Spitz as taught by Carothers teaches forming a doped region (Spitz: Fig. 2C; [0025], [0033], [0040] and [0055]: 103/104/105) within the substrate,
wherein the one or more trenches (Spitz: [0038]: 146a and 146b) have interior sidewalls that face towards opposing sides of the via opening (Spitz: 149),
the doped region (Spitz: 103/104/105) being laterally between one of the interior sidewalls the via opening (Spitz: 149).
Regarding claim 27: Spitz teaches the claim limitation of the method of claim 21, on which this claim depends, further comprising:
etching the second side of the substrate to form an additional via opening ([0045]: 148) extending through the substrate to expose the one or more interconnects (interconnect 110a/110 on the side of trench 149),
wherein the one or more trenches are disposed along opposing sides (from left side to right side) of the additional via opening (148).
Regarding claim 29: Spitz teaches the claim limitation of the method of claim 21, on which this claim depends, further comprising:
depositing the insulating material within the one or more trenches and within the via opening ([0040] and [0046]: the dielectric material used in the filling the first trench and the second trench is ozone/TEOS).
Regarding claim 30: Spitz teaches the claim limitation of the method of claim 21, on which this claim depends, further comprising:
forming one or more conductive features ([0049]: 138) onto the conductive material within the via opening (149).
Claims 15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Spitzlsperger et al., hereinafter Spitz (US 2016/0379936 A1) in view of Feng et al. (US 2014/0357050 A1) as applied above and further in view of Hung et al. (US 2016/0211194 A1).
Regarding claim 15: Spitz teaches the claim limitation of the method of claim 14, on which this claim depends.
wherein the first doped region ([0025], [0033], [0040] and [0055]: 103/104/105) is laterally between the first trench ([0038]: 146a) and the second trench (149) in a cross-sectional view.
Spitz does not expressly teach that
the interconnect structure being electrically coupled to the first doped region by a conductive contact arranged vertically between the interconnect structure and the first doped region.
Hung teaches (e.g., Fig. 1) a method comprising
an interconnect structure ([0022]: 252) electrically coupled to a first doped region ([0023]: 242) by a conductive contact ([0021]: 238) arranged vertically between the interconnect structure (252) and the first doped region (242).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include the method of Splitz,
the interconnect structure being electrically coupled to the first doped region by a conductive contact arranged vertically between the interconnect structure and the first doped region, as taught by Hung, for the benefits of reducing the risk of uneven electric fields, blocking outside noise from affecting signals, keeping systems reliable and preventing interference; thus, improving system performance.
Regarding claim 17: Spitz teaches the claim limitation of the method of claim 14, on which this claim depends.
Splitz, does not expressly teach that the interconnect structure continuously and laterally extends from the conductive material to laterally overlap the first doped region in a cross-sectional.
Hung teaches (e.g., Fig. 1) a method comprising
an interconnect structure ([0022]: 252) continuously and laterally extends from a conductive material ([0018]: 234) to laterally overlap a first doped region ([0023]: 242) in a cross-sectional (Fig. 1).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the method of Splitz, the interconnect structure continuously and laterally extends from the conductive material to laterally overlap the first doped region in a cross-sectional, as taught by Hung, for the benefits of reducing the risk of uneven electric fields, blocking outside noise from affecting signals, keeping systems reliable and preventing interference; thus, improving system performance.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Spitzlsperger et al., hereinafter Spitz (US 2016/0379936 A1) and Feng et al. (US 2014/0357050 A1) as applied above and further in view of Kuo (US 2010/0093169 A1).
Regarding claim 16: Spitz teaches the claim limitation of the method of claim 14, on which this claim depends, further comprising:
forming a gate structure ([0049] and [0055]; elements 106 and 107 of Fig. 2J) along the first surface of the substrate (100); and
forming a second doped region (103/104/105 on the opposite side from the first doped region; corresponding source/drain regions [0004], [0024]-[0025]) on a side of the gate structure;
Spitz does not expressly teach
wherein after the forming of the interconnect structure, one end of the interconnect structure is electrically coupled to the first doped region, and another end of the interconnect structure is electrically coupled to the second doped region.
Kuo teaches (e.g., Figs. 1B-1D) a method comprising forming an interconnect ([0028]: 126/124/123);
Kuo further teaches that after forming of an interconnect structure ([0028]: 126/124/123), one end of the interconnect structure is electrically coupled to the first doped region ([0028]: left side doped region 118), and another end of the interconnect structure (126/124/123) is electrically coupled to the second doped region ([0028]: left side doped region 118).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include the method of Spitz, the method of forming an interconnect, wherein after the forming of the interconnect structure, one end of the interconnect structure is electrically coupled to the first doped region, and another end of the interconnect structure is electrically coupled to the second doped region, as taught by Kuo, for the benefits of simultaneously and efficiently driving the transistor with a redundancy scheme.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Spitzlsperger et al., hereinafter Spitz (US 2016/0379936 A1) in view of Carothers et al. (US 2017/0117356 A1).
Regarding claim 23: Spitz teaches the claim limitation of the method of claim 22, on which this claim depends, further comprising:
Spitz as taught by Carothers teaches forming a doped region (Spitz: Fig. 2C; [0025], [0033], [0040] and [0055]: 103/104/105) within the substrate,
wherein the one or more trenches (Spitz: [0038]: 146a and 146b) have interior sidewalls that face towards opposing sides of the via opening (Spitz: 149),
the doped region (Spitz: 103/104/105) being laterally between one of the interior sidewalls the via opening (Spitz: 149).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Spitzlsperger et al., hereinafter Spitz (US 2016/0379936 A1) in view Carothers et al. (US 2017/0117356 A1) and further in view of Morii et al. (US 2018/0294265 A1).
Regarding claim 24: Spitz teaches the claim limitation of the method of claim 21, on which this claim depends.
Spitz does not expressly teach that the one or more trenches extend along multiple sides of the via opening in a plan-view.
Morii teaches (e.g., Figs. 1-3 and Figs. 12-16) a method comprising
one or more trenches ([0047] and [0101]: DTR) extend along multiple sides of the via opening ([0096]: TI/CH1A);
Morii further teaches that the one or more trenches extend along multiple sides of the via opening in a plan-view (Figs. 1-2; [0047], [0096] and [0101]: DTR is formed around the area DFR that includes the via opening).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include the method of Spitz, the method of forming the one or more trenches extending along multiple sides of the via opening in a plan-view, as taught by Morii, for the benefits of reducing signal interferences from adjacent devices.
Claims 25-26 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Spitzlsperger et al., hereinafter Spitz (US 2016/0379936 A1) and Carothers et al. (US 2017/0117356 A1) as applied above and further in view of Shih (US 2021/0134655 A1).
Regarding claim 25: Spitz teaches the claim limitation of the method of claim 21, on which this claim depends.
Spitz does not expressly teach that the one or more trenches comprise
a first trench extending in a first closed loop; and
a second trench extending in a second closed loop that wraps around the first trench and the via opening.
Shih teaches (e.g., Figs. 1A-1B) a method comprising:
a first trench ([0015]-[0018]: inner side 108) extending in a first closed loop; and
a second trench ([0015]-[0016]: outer side 108) extending in a second closed loop that wraps around the first trench ([0015]-[0018]) and a via opening ([0015]-[0018]: 112).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include the method of Spitz, the method of forming a first trench extending in a first closed loop; and a second trench extending in a second closed loop that wraps around the first trench and the via opening, as taught by Shih, for the benefits of isolating the central device from the peripheral devices and thus reducing the signal interference from surrounding device.
Regarding claim 26: Spitz and Shih teach the claim limitation of the method of claim 25, on which this claim depends,
wherein the first trench wraps around a device area comprising one or more transistor devices (Shih: [0017]: 120).
Regarding claim 28: Spitz teaches the claim limitation of the method of claim 27, on which this claim depends.
Spitz does not expressly teach that the method further comprises that the one or more trenches comprise:
a first trench extending in a first closed loop around the via opening and the additional via opening in a plan view.
Shih teaches (e.g., Figs. 1A-1B) a method comprising:
a first trench ([0015]-[0018]: inner side trench 108) extending in a first closed loop around a via opening (112); and
a second trench ([0015]-[0016]: 108) extending in a second closed loop that wraps around the first trench and a via opening ([0015]-[0021]: trench 110).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include the method of Spitz, the method of forming a first trench extending in a first closed loop; and a second trench extending in a second closed loop that wraps around the first trench and the via opening, as taught by Shih, for the benefits of isolating the central device from the peripheral devices and thus reducing the signal interference from surrounding device.
Claim 31 is rejected under 35 U.S.C. 103 as being unpatentable over Spitzlsperger et al., hereinafter Spitz (US 2016/0379936 A1) in view of in view of Yang et al. (US 2013/0264676 A1).
Regarding independent claim 31: Spitz teaches (e.g., Figs. 2A-2J; Figs. 3-4 are manufacturing flow charts; [0016]-[0017]) a method of forming a semiconductor device, comprising:
forming one or more devices ([0025]: transistors) within a device region of a substrate ([0025]: 100);
forming one or more interconnects ([0025] and [0043]: 110/110a) within an inter-level dielectric (ILD) structure ([0025]-[0006]: 111) arranged along a first side of the substrate ([0025]: front side 100a of substrate 100);
forming a plurality of isolation structures ([0025] and [0038]: 101a) within the substrate ([0038]-[0039]: 100) as viewed in a cross-sectional view (Figs. 2B-2E);
performing one or more patterning processes on a second side of the substrate to form a via opening ([0038] and[0045]: forming first trench 149 from the backside) and one or more trenches ([0038]: forming first trench 146a/146b from the backside) within the substrate, the second side of the substrate opposing the first side of the substrate (the bottom side opposite the front side),
wherein the one or more trenches (146a/146b) are laterally between the via opening (149) and the device region; and
wherein bottoms of the via opening (149) and the one or more trenches (146a) are formed by horizontally extending surfaces of the plurality of isolation structures (101a);
performing an etching process to extend the via opening to expose the one or more interconnects ([0045]-[0047]: the initial etching process does not expose the interconnect until the process proceeds; thus the requirement of performing an etching process to extend the via opening to expose the one or more interconnects, is met);
depositing a dielectric material ([0040] and [0046]: the dielectric material used in the filling the first trench and the second trench is ozone/TEOS) within the one or more trenches and the via opening (146a/146b and 149); and
forming a conductive material ([0046]: 134) within the via opening and on the dielectric material within the via opening.
Spitz does not expressly teach
performing an etching process to extend the via opening completely through one of the plurality of isolation structures to expose the one or more interconnects, wherein the etching process forms sidewalls of the one of the plurality of isolation structures.
Yang teaches (e.g., Figs. 1-3e) a method comprising:
performing an etching process ([0028]) to extend a via opening completely through one of the plurality of isolation structures ([0028]: 244) to expose one or more interconnects ([0032]: 226),
wherein the etching process forms sidewalls of the one of the plurality of isolation structures (isolation structures 244 form sidewalls).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the method of Splitz, the method of performing an etching process to extend the via opening completely through one of the plurality of isolation structures to expose the one or more interconnects, wherein the etching process forms sidewalls of the one of the plurality of isolation structures, as taught by Carothers, for the benefits of avoiding interferences of signals near the active devices, and thus, improving device reliability.
Claim 32 is rejected under 35 U.S.C. 103 as being unpatentable over Spitzlsperger et al., hereinafter Spitz (US 2016/0379936 A1) in view of in view of Yang et al. (US 2013/0264676 A1) as applied above and further in view of Carothers et al. (US 2017/0117356 A1).
Regarding claim 32: Spitz teaches the claim limitation of the method of claim 31, on which this claim depends, further comprising:
Spitz as modified by Yang teaches forming a doped region (Spitz: Fig. 2C; [0025], [0033], [0040] and [0055]: 103/104/105) within the substrate (Spitz: [0038]),
wherein the one or more trenches (Spitz: 146a/146b) have interior sidewalls that face towards opposing sides of the via opening (Spitz: 149).
Spitz does not expressly teach that
the via opening and the doped region both being laterally surrounded by the interior sidewalls in a cross-sectional view.
Carothers teaches (e.g., Figs. Figs. 6A-6D and Figs. 8A-8G; [0042] FIG. 6A through FIG. 6D are cross sections of the integrated circuit of FIG. 4, depicting successive stages of an example method of continued formation of the integrated circuit after the isolation structure is formed) a method comprising:
etching a second side of a substrate ([0031]: backside of substrate 402) to form one or more trenches ([0043]: 466; the trenches are not shown in Fig. 8A-8G; however, the process goes into forming trenches in the backside of the substrate; as a shown in Fig. 6B which is depicting Fig. 4; Fig. 4 shows preceding steps before etching process to form trench on the backside of the substrate) that laterally surround the via opening ([0061]: 894) along opposing sides in a cross-sectional view (Fig. 6B and Fig 8G).
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the method of Splitz, the method of etching the second side of the substrate to form one or more trenches that laterally surround the via opening along opposing sides in a cross-sectional view, as taught by Carothers, for the benefits of more effectively isolate signal interferences from adjacent devices.
Claim 33 is rejected under 35 U.S.C. 103 as being unpatentable over Spitzlsperger et al., hereinafter Spitz (US 2016/0379936 A1) in view of in view of Yang et al. (US 2013/0264676 A1) and Carothers et al. (US 2017/0117356 A1) as applied above and further in view of Feng et al. (US 2014/0357050 A1).
Regarding claim 33: Spitz, Yang and Carothers teach the claim limitation of the method of claim 32, on which this claim depends,
Spitz as modified by Yang and Carothers does not expressly teach that the one or more patterning processes are performed to concurrently form the via opening and the one or more trenches within the substrate; and
wherein the etching process is performed after the one or more patterning processes are completed.
Feng teaches (e.g., Figs. 2-10) a method comprising one or more patterning processes ([0014]-[0015]: masks used for patterning process) to form a via opening ([0014]-[0015]: 22) and one or more trenches ([0014]-[0015]: 20) within a substrate ([0014]: 10);
Feng further teaches that the one or more patterning processes ([0014]-[0015]: masks used for patterning process) are performed to concurrently the via opening ([0014]-[0015]: 22) and the one or more trenches ([0014]-[0015]: 20) within the substrate ([0014]: 10); and
wherein the etching process ([0014]-[0015]: masks used for patterning process) is performed after the one or more patterning processes are completed ([0014]-[0015]: the etching process is performed after the one or more patterning processes are completed).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the method of Splitz, the method, wherein the one or more patterning processes are performed to concurrently form the via opening and the one or more trenches within the substrate; and wherein the etching process is performed after the one or more patterning processes are completed, as taught by Feng, for the benefits, of controlling the precise location of the via and the isolation structure, thus improving device reliability, and at the same time, reducing the number of masking steps during the manufacturing process, and thus, increasing manufacturing throughput.
Furthermore, it would have been obvious because all the claimed elements were known in the prior art and one skilled in the art before the effective filing date of the claimed invention, could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the filing date. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007). "If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person's skill." Id.
Response to Arguments
Applicant’s arguments with respect to claim(s) 14-33 have been considered but are moot because the new ground of rejection does not rely on any reference or combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument or of newly incorporated amendment.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HERVE-LOUIS Y ASSOUMAN whose telephone number is (571)272-2606. The examiner can normally be reached M-F: 08:30 AM-5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HERVE-LOUIS Y ASSOUMAN/ Examiner, Art Unit 2812