DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office action is in response to the amendment filed 5/8/2026 in which claims 1, 7, 8, 16, and 20 were amended.
Claims 1, 2, 4-14, 16, and 18-20 are pending and presented for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 2 are rejected under 35 U.S.C. 103 as being unpatentable over Aoki (US 2012/0091508 and Aoki hereinafter) in view of Okamoto (US 2019/0051740 and Okamoto hereinafter).
As to claims 1 and 2: Aoki discloses [claim 1] a wide band gap transistor (Fig. 13; [0039], [0041], [0042], and [0086]), comprising: a semiconductor structure (comprising 10, 11, 21, and 22; [0037]-[0042]) including: a substrate (10; [0037]-[0038]); a channel layer (21; [0040]) of gallium nitride (GaN) (undoped GaN; [0040]) on the substrate (10); and a barrier layer (22; [0041]-[0042]) of a material selected from a group of materials including aluminum gallium nitride (AlGaN) (AlGaN; [0041]), ternary alloys of aluminum and gallium, and quaternary alloys of aluminum and gallium; a trench (7; [0073]) partially extending into a first surface (top surface) of the barrier layer (22) such that a base (bottom) of the trench (7) is a second surface of the barrier layer (22); an insulating gate structure (50; [0080]) on the first surface (top surface) of the barrier layer (22) and in the trench (7), the insulating gate structure (50) including a first opening (where 3 is formed) exposing the barrier layer (22) and a second opening (where 4 is formed) exposing the barrier layer ([0083]); a gate electrode (51; [0081]) on the insulating gate structure (50), in the trench (7), and separated from the barrier layer (22) by the insulating gate structure (50); a source electrode (3; [0084]) on the first surface (top surface) of the barrier layer (22) and in the first opening (where 3 is formed) such that portions of the insulating gate structure (50) are on opposite sides (left and right sides) of the source electrode (3); and a drain electrode (4; [0084]) on the first surface (top surface) of the barrier layer (22) and in the second opening (where 4 is formed) such that portions of the insulating gate structure (50) are on opposite sides (left and right sides) of the drain electrode (4); [claim 2] wherein the semiconductor structure (comprising 10, 11, 21, and 22) includes a heterostructure (formed between 21 and 22; [0040]-[0041]) including: a heterojunction being formed at an interface between the channel layer (21) and the barrier layer (22; [0033] and [0040]-[0041]).
Aoki fails to expressly disclose [claim 1] the insulating gate structure including a mixture of aluminum, hafnium, and oxygen.
Aoki discloses a transistor with a gate electrode 50 that can comprise SiO2, SiN, Al2O3, or the like, [0057].
Okamoto discloses a transistor comprising III-nitride compounds where [claim 1] the insulating gate structure (GI; [0138]) including a mixture of aluminum, hafnium, and oxygen (GI can be HfAlO; [0138]).
Therefore, the claimed invention would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art because, as stated in KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007), a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing a HfAlO from the list of Okamoto instead of SiO2, SiN, or Al2O3 as in Aoki; if this leads to the anticipated success, in the instant case a material that provides a desired level of electrical isolation between the gate electrode and the underlying semiconductor structure, it is likely the product not of innovation but of ordinary skill.
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Aoki in view of Okamoto as applied to claim 1 above, and further in view of Fenwick et al (US 2021/0123143 and Fenwick hereinafter).
As to claims 4-6: Although the structure disclosed by Aoki in view of Wang shows substantial features of the claimed invention (discussed in paragraph 8 above), it fails to expressly disclose:
[claim 4] wherein the insulating gate structure is at least partially layered with a plurality of first regions including aluminum oxide (Al2O3) and a plurality of second regions including hafnium oxide (HfO2) that are alternated with the first regions; [claim 5] wherein each of the first regions and each of the second regions has a thickness comprised between 1 nm and 5 nm; [claim 6] wherein the insulating gate structure is amorphous.
Aoki in view of Okamoto discloses a GaN HEMT with a HfAlO gate insulator.
Fenwick discloses a method of forming a HfAlO layer on a buffer layer ([0078]), such as a layer comprising aluminum and nitrogen, [claim 4] wherein the insulating gate structure (Fig. 2C; hafnium aluminate, HfAlO; [0068] and [0077]) is at least partially layered with a plurality of first regions (239; [0068]-[0069]) including aluminum oxide (Al2O3) (can be aluminum oxide; [0069]) and a plurality of second regions (233; [0071]-[0072]) including hafnium oxide (HfO2) (can be hafnium oxide) that are alternated with the first regions (239); [claim 5] wherein each of the first regions (239) and each of the second regions (233) has a thickness comprised between 1 nm and 5 nm (239 and 233 can each be between 1 nm and 1000 nm; [0070] and [0073]); [claim 6] wherein the insulating gate structure is amorphous ([0098]).
Therefore, a person having ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to form the transistor device of Aoki in view of Okamoto with the HfAlO dielectric of Okamoto using the method of forming HfAlO taught by Fenwick since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results, namely an HfAlO layer for use in a transistor that is formed within the claimed thicknesses to provide a dielectric layer that is amorphous, uniform, continuous, conformal, and free of porosity ([0098]).
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Aoki in view of Sun et al (CN 108987277 and Sun hereinafter; a machine translation is used as an English language equivalent) in view of Sato (US 2017/0125568 and Sato hereinafter) in view of Okamoto.
As to claims 7 and 8: Aoki discloses [claim 7] a process for manufacturing a wide band gap transistor (Figs. 13-19; [0039], [0041], [0042], and [0086]), the process comprising: forming a semiconductor structure (Fig. 14; comprising 10, 11, 21, and 22; [0037]-[0042]) including a channel layer (21; [0040]) of gallium nitride (GaN) (undoped GaN; [0040]), a barrier layer (22; [0041]-[0042]), and a trench (Fig. 15; 7; [0073]) partially extending into a first surface (top surface) of the barrier layer (22) such that a base (bottom surface) of the trench (7) is a second surface of the barrier layer (22); forming an insulating gate structure (Fig. 16; 50; [0080]) on the semiconductor structure (comprising 10, 11, 21, and 22); forming a first opening (Fig. 13; where 3 is formed; [0083]) and a second opening (where 4 is formed; [0083]) in the insulating gate structure (50); forming a source electrode (Fig. 19; 3; [0084]) on the semiconductor structure (comprising 10, 11, 21, and 22) and in the first opening (where 3 is formed); forming a drain electrode (Fig. 19; 4; [0084]) on the semiconductor structure (comprising 10, 11, 21, and 22) and in the second opening (where 4 is formed); forming a gate electrode (Fig. 19; 5; [0082]) on the insulating gate structure (50); [claim 8] wherein forming the semiconductor structure (comprising 10, 11, 21, and 22) includes: forming a heterostructure (formed between 21 and 22; [0040]-[0041]) including: the channel layer (21) of gallium nitride (GaN) (undoped GaN; [0040]); and the barrier layer (22) of aluminum gallium nitride (AlGaN) (AlGaN; [0041]), a heterojunction being formed at an interface between the channel layer (21) and the barrier layer (22; [0033] and [0040]-[0041]).
Aoki fails to expressly disclose [claim 7] performing a first annealing at a first temperature of the insulating gate structure, the source electrode, and the drain electrode; forming, subsequent to the performing of the first annealing, the gate electrode on the insulating gate structure.
Aoki discloses a wide band gap transistor.
Sun discloses a method of forming wide band gap transistor including [claim 7] performing a first annealing (Fig. 18; high-temperature alloy process; [0066], [0080], and [0091]) at a first temperature ([0066] and [0091]) of the insulating gate structure (6), the source electrode (81), and the drain electrode (82); forming, subsequent to the performing of the first annealing ([0080]), the gate electrode (Figs. 19-21; 9; [0094]-[0097]) on the insulating gate structure (6).
Given the teachings of Sun, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Aoki by employing the well-known or conventional features of wide band gap transistor fabrication, such as displayed by Sun, by employing an annealing step in between forming the insulating gate structure, source electrode, and drain electrode and forming the gate electrode in order to provide good ohmic contact between the source and drain electrodes and the nitride semiconductor ([0066]).
Aoki in view of Sun fail to expressly disclose [claim 7] performing a second annealing at a second temperature of the gate electrode.
Sato discloses a HEMT on a GaN structure that comprises a method of forming the transistor by forming the source 212 and drain 213 electrodes and the gate insulating layer 205 prior to forming the gate electrode, see Figs. 4A-4C and [0049]-[0051]. After the gate electrode 211 is formed in Fig. 4F, an annealing step/heat treatment is performed, see [0054].
Given the teachings of Sato, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Aoki in view of Sun by employing the well-known or conventional features of HEMT fabrication, such as displayed by Sato, by employing an annealing step after forming the gate electrode in order to relax stress, enable low-resistance wiring, and reduce contact resistance ([0054]).
Aoki in view of Sun in view of Sato fails to expressly disclose where [claim 7] the insulating gate structure including a mixture of aluminum, hafnium, and oxygen.
Aoki in view of Sun in view of Sato discloses a HEMT with a gate insulating layer comprising Si3N4, SiO2, Al2O3, HfO2, TiO2, MgO, or Sc2O3 can be used, see [0052].
Okamoto discloses a HEMT comprising III-nitride compounds where [claim 7] the insulating gate structure (GI; [0138]) including a mixture of aluminum, hafnium, and oxygen (GI can be HfAlO; [0138]).
Therefore, the claimed invention would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art because, as stated in KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007), a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing a HfAlO from the list of Okamoto instead of SiO2, SiN, or Al2O3 as in Aoki; if this leads to the anticipated success, in the instant case a material that provides a desired level of electrical isolation between the gate electrode and the underlying semiconductor structure, it is likely the product not of innovation but of ordinary skill.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Aoki in view of Sun in view of Sato in view of Okamoto as applied to claim 7 above, and further in view of Baringhaus et al (US 2024/0055528 and Baringhaus hereinafter) in view of Fiorenza et al (US 2020/0373398 and Fiorenza hereinafter).
Although the method disclosed by Aoki in view of Sun in view of Sato in view of Okamoto shows substantial features of the claimed invention (discussed in paragraph 12 above), it fails to expressly disclose:
wherein forming the semiconductor structure includes: forming a substrate of silicon carbide (SiC) having a conductivity type and a first doping level; and forming an epitaxial layer of silicon carbide (SiC) having the conductivity type and a second doping level lower than the first doping level.
Aoki in view of Sun in view of Sato in view of Okamoto discloses forming a transistor comprising GaN and III-nitride materials.
Baringhaus discloses that processes for forming a transistor as a GaN/III-nitride based structure can apply to SiC based structures, see [0024].
Therefore, Baringhaus discloses wherein forming the semiconductor structure (Fig. 2; comprising 202 and 204; [0024]) includes: forming a substrate (202) of silicon carbide (SiC) (SiC; [0024]); and forming an layer (204; [0024]) of silicon carbide (SiC) (SiC; [0024]) having the conductivity type (n-type; [0024]) and a second doping level (weak n-type doped; [0024]).
Baringhaus fails to expressly disclose where the substrate having a conductivity type and a first doping level, the layer 204 is formed by epitaxial deposition, and the second doping level is lower than the first doping level.
Fiorenza discloses in Fig. 1 a silicon carbide-based transistor where the substrate 36 having a conductivity type (n-type; [0013]) and a first doping level (n+; [0013]), the layer 204 is formed by epitaxial deposition (38 is formed epitaxially and is analogous to Baringhaus 204; [0013]), and the second doping level (n-; [0013]) is lower than the first doping level (n+).
Therefore, a person having ordinary skill before the effective filing date of the claimed invention would have found the claim obvious because, as stated in KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007), the substitution for one known element (in this case SiC based materials) for another (in this case III-nitride based materials) would have yielded predictable results (in this case a well-studied material that has a high value of thermal conductivity, high operating frequencies, and a high saturation velocity that can be used as a base material for a wide bandgap transistor; [0002]-[0003] of Fiorenza) to one of ordinary skill in the art before the effective filing date of the claimed invention.
Claims 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Aoki in view of Sun in view of Sato in view of Okamoto as applied to claim 7 above, and further in view of Fenwick.
As to claims 10-14: Aoki in view of Sun in view of Sato in view of Okamoto discloses [claim 11] wherein performing the first annealing includes heating the insulating gate structure, the source electrode, and the drain electrode ([0091]-[0092]) to the first temperature (850°C; [0065]-[0066]) for an annealing duration (45 seconds; [0065]-[0066]); [claim 12] wherein the first temperature is between 500 °C and 950 °C (850°C; [0065]-[0066]), and the annealing duration is between 30 seconds and 600 seconds (45 seconds; [0065]-[0066]).
Given the teachings of Sun, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Aoki by employing the well-known or conventional features of wide band gap transistor fabrication, such as displayed by Sun, by employing an annealing step in between forming the insulating gate structure, source electrode, and drain electrode and forming the gate electrode in order to provide good ohmic contact between the source and drain electrodes and the nitride semiconductor ([0066]).
Aoki in view of Sun in view of Sato in view of Okamoto fail to expressly disclose [claim 10] wherein forming the insulating gate structure includes: depositing, in alternated succession, a plurality of aluminum oxide layers and a plurality of hafnium oxide layers, forming a gate stack, performing the first annealing includes diffusing aluminum oxide of the plurality of aluminum oxide layers and hafnium oxide of the plurality of hafnium oxide layers at interfaces between adjacent aluminum oxide layers and hafnium oxide layers and mix; [claim 13] wherein depositing in alternated succession include depositing by Atomic Layer Deposition; [claim 14] wherein each of the plurality of aluminum oxide layers and each of the plurality of hafnium oxide layers have a thickness comprised between 0.5 nm and 10 nm.
Aoki in view of Sun in view of Sato in view of Okamoto discloses a GaN HEMT with a HfAlO gate insulator.
Fenwick discloses a method in Fig. 2C of forming a HfAlO layer on a buffer layer ([0078]), such as a layer comprising aluminum and nitrogen, [claim 10] wherein forming the insulating gate structure includes: depositing, in alternated succession, a plurality of aluminum oxide layers (239 can be aluminum oxide; [0068]-[0069]) and a plurality of hafnium oxide layers (233 can be hafnium oxide; [0071]-[0072]), forming a gate stack (gate stack is 245; [0075]), performing the first annealing (annealing; [0089]) includes diffusing aluminum oxide of the plurality of aluminum oxide layers and hafnium oxide of the plurality of hafnium oxide layers at interfaces between adjacent aluminum oxide layers and hafnium oxide layers and mix ([0089]); [claim 13] wherein depositing in alternated succession include depositing by Atomic Layer Deposition (ALD is used; [0068]-[0072]); [claim 14] wherein each of the plurality of aluminum oxide layers (239) and each of the plurality of hafnium oxide layers (233) have a thickness comprised between 0.5 nm and 10 nm (239 and 233 can each be between 1 nm and 1000 nm; [0070] and [0073]).
Therefore, a person having ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to form the transistor device of Aoki in view of Sun in view of Sato in view of Okamoto with the HfAlO dielectric of Okamoto using the method of forming HfAlO taught by Fenwick since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results, namely an HfAlO layer for use in a transistor that is formed within the claimed thicknesses and formed using a time and temperature within the claimed respective ranges in an ALD process in order to provide a dielectric layer that is amorphous, uniform, continuous, conformal, and free of porosity ([0098]).
As to [claim 11] the first temperature and the annealing duration are selected so as to prevent the insulating gate structure from crystallizing, Fenwick discloses that the HfAlO layer formed by the method is amorphous ([0098]) and that the annealing of the amorphous hafnium aluminate layer can be performed at temperatures below 1200°C to keep it amorphous, see [0089].
Therefore, when the method of forming the gate dielectric of Fenwick is used in the method of forming the HEMT of Aoki in view of Sun in view of Sato in view of Okamoto, the first annealing of Sun, which occurs at 850°C and for 45 seconds, is within the claimed and disclosed ranges of the instant application and below the temperature to keep amorphous as in Fenwick, the method of Sun will keep the gate dielectric amorphous.
Claims 16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Aoki in view of Okamoto in view of Fenwick in view of Sato.
As to claims 16 and 18-20: Aoki discloses [claim 16] a method (Figs. 13-19; [0039], [0041], [0042], and [0086]), comprising: forming a semiconductor structure (Fig. 14; comprising 10, 11, 21, and 22; [0037]-[0042]) including a channel layer (21; [0040]) of gallium nitride (GaN) (undoped GaN; [0040]), a barrier layer (22; [0041]-[0042]), and a trench (Fig. 15; 7; [0073]) partially extending into a first surface (top surface) of the barrier layer (22) such that a base (bottom surface) of the trench (7) is a second surface of the barrier layer (22); forming an insulating gate structure (Fig. 16; 50; [0080]) on the semiconductor structure (comprising 10, 11, 21, and 22); forming a source electrode (Fig. 19; 3; [0084]) on the semiconductor structure (comprising 10, 11, 21, and 22); forming a drain electrode (Fig. 19; 4; [0084]) on the semiconductor structure (comprising 10, 11, 21, and 22); forming a gate electrode (Fig. 19; 5; [0082]) on the insulating gate structure (50); [claim 20] wherein forming the semiconductor structure (comprising 10, 11, 21, and 22) includes forming the channel layer (21) on a substrate (10), and forming the barrier layer (22) on the channel layer (21).
Aoki fails to expressly disclose where [claim 16] the forming of the insulating gate structure including: forming a first plurality of layers of aluminum oxide (Al2O3); and forming a second plurality of layers of hafnium oxide (HfO2); [claim 19] wherein each of the first plurality of layers is spaced from another layer of the first plurality of layers by a layer of the second plurality of layers.
Aoki discloses a transistor with a gate electrode 50 that can comprise SiO2, SiN, Al2O3, or the like, [0057].
Okamoto discloses a HEMT comprising III-nitride compounds where the insulating gate structure (GI; [0138]) can be HfAlO, ([0138]).
Fenwick discloses a method in Fig. 2C of forming a HfAlO layer on a buffer layer ([0078]), such as a layer comprising aluminum and nitrogen, where [claim 16] the forming of the insulating gate structure including: forming a first plurality of layers of aluminum oxide (Al2O3) (Fig. 2C; 239 can be aluminum oxide; [0068]-[0069]); and forming a second plurality of layers of hafnium oxide (HfO2) (233 can be hafnium oxide; [0071]-[0072]); [claim 19] wherein each of the first plurality of layers (239) is spaced from another layer of the first plurality of layers (239) by a layer of the second plurality of layers (233).
Therefore, a person having ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to form the transistor device of Aoki with the HfAlO dielectric of Okamoto using the method of forming HfAlO taught by Fenwick since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results, namely an HfAlO layer for use in a transistor that is formed within the claimed thicknesses and formed using a time and temperature within the claimed respective ranges in an ALD process in order to provide a dielectric layer that is amorphous, uniform, continuous, conformal, and free of porosity ([0098]) and provides a desired level of electrical isolation between the gate electrode and the underlying semiconductor structure.
Aoki in view of Okamoto in view of Fenwick fails to expressly disclose [claim 16] performing a first annealing at a first temperature of the insulating gate structure, the source electrode, and the drain electrode; and forming, subsequent to the performing of the first annealing, the gate electrode on the insulating gate structure; [claim 18] wherein the first annealing is performed at the first temperature for an annealing duration.
Aoki in view of Okamoto in view of Fenwick disclose forming a wide band gap transistor.
Sun discloses a method of forming wide band gap transistor including [claim 16] performing a first annealing (Fig. 18; high-temperature alloy process; [0066], [0080], and [0091]) at a first temperature ([0066] and [0091]) of the insulating gate structure (6), the source electrode (81), and the drain electrode (82); and forming, subsequent to the performing of the first annealing ([0080]), the gate electrode (Figs. 19-21; 9; [0094]-[0097]) on the insulating gate structure (6); [claim 18] wherein the first annealing (high-temperature alloying) is performed at the first temperature (850°C; [0065]-[0066]) for an annealing duration (45 seconds; [0065]-[0066]).
Given the teachings of Sun, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Aoki in view of Okamoto in view of Fenwick by employing the well-known or conventional features of wide band gap transistor fabrication, such as displayed by Sun, by employing an annealing step in between forming the insulating gate structure, source electrode, and drain electrode and forming the gate electrode in order to provide good ohmic contact between the source and drain electrodes and the nitride semiconductor ([0066]).
As to where [claim 16] the first annealing is performed on the first plurality of layers and the second plurality of layers, when the method of forming the HfAlO layer of Fenwick is used in the method of forming the HEMT of Aoki in view of Okamoto in view of Sun, the layers 239 and 233 will be subjected to the first annealing in [0066] and [0091] of Sun.
Aoki in view of Okamoto in view of Fenwick in view of Sun fail to expressly disclose [claim 16] performing a second annealing at a second temperature of the gate electrode.
Sato discloses a HEMT on a GaN structure that comprises a method of forming the transistor by forming the source 212 and drain 213 electrodes and the gate insulating layer 205 prior to forming the gate electrode, see Figs. 4A-4C and [0049]-[0051]. After the gate electrode 211 is formed in Fig. 4F, an annealing step/heat treatment is performed, see [0054].
Given the teachings of Sato, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Aoki in view of Okamoto in view of Fenwick in view of Sun by employing the well-known or conventional features of HEMT fabrication, such as displayed by Sato, by employing an annealing step after forming the gate electrode in order to relax stress, enable low-resistance wiring, and reduce contact resistance ([0054]).
As to [claim 18] where the first temperature and the annealing duration are selected to prevent the insulating gate structure from crystallizing, Fenwick discloses that the hafnium aluminate layer formed by the method is amorphous ([0098]) and that the annealing of the amorphous hafnium aluminate layer can be performed at temperatures below 1200°C to keep it amorphous, see [0089]. Therefore, when the method of forming the gate dielectric of Fenwick is used in the method of forming the HEMT of Sun in view of Okamoto, the first annealing of Sun, which occurs at 850°C and for 45 seconds, is within the disclosed ranges of the instant application and below the temperature to keep amorphous as in Fenwick, the method of Sun will keep the gate dielectric amorphous.
Response to Arguments
Applicant’s arguments with respect to claims 1, 2, 4-14, 16, and 18-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH C NICELY whose telephone number is (571)270-3834. The examiner can normally be reached Monday-Friday 7:30 am - 4 pm, EST.
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JOSEPH C. NICELY
Primary Examiner
Art Unit 2813
/JOSEPH C. NICELY/Primary Examiner, Art Unit 2813
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