DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
In addressing the rejection ground, each claim may not have been separately discussed to the extent the claimed features are the same as or similar to the previously-discussed features; the previous discussion is construed to apply for the other claims in the same or similar way.
In the office action, “/” should be read as and/or as generally understood. For example, “A/B” means A and B, or A or B.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 10-13 and 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Melanson (US 6,346,898) in view of Kulkarni er al. (US 2016/0379695).
Regarding claim 1, Melanson discloses an apparatus [e.g. fig. 5], comprising: a resistor ladder [e.g. 502s coupled in series] comprising a first plurality of devices [e.g. 502s], wherein the first plurality of devices comprises a plurality of resistive devices [e.g. 502s] connected in series; and a plurality of comparators [e.g. 510s] connected to the resistor ladder, wherein a first comparator [e.g. the top 510] of the plurality of comparators is connected to a connection point [e.g. the tap between the first 502 from the top and the second 502 from the top] between a first device [e.g. the first/second 502 from the top] and a second device [e.g. the second/third 502 from the top] of the plurality of devices through a first switch [e.g. a switch connected in between the first comparator and the first tap], wherein a first reference voltage applied to the first comparator is produced at the connection point between the first device and the second device, wherein a second comparator [e.g. the third 510 from the top (or the second 510 from the top)] of the plurality of comparators is connected to a connection point [e.g. the node between the third 502 from the top and the fourth 502 from the top (or the node between the second 502 from the top and the third 502 from the top)] between the second device and a third device [e.g. the third 502 from the top (or the fourth 502 from the top)] of the plurality of devices of the resistor ladder through a second switch [e.g. a switch connected in between the second comparator and the second tap], wherein a second reference voltage applied to the second comparator is produced at the connection point between the second device and the third device, and wherein the first comparator produces a first digital output [e.g. the output of the comparator] indicative of a result of a comparison between an analog input voltage [e.g the voltage at the lower input terminal] applied to the first comparator and the first reference voltage.
Melanson does not disclose the resistor ladder comprising a first plurality of non-volatile memory devices, the first plurality of non-volatile memory devices comprises a first plurality of resistive random-access memory (RRAM) devices connected in series. However, Kulkarni discloses a resistor ladder [e.g. 602s coupled in series, also see fig. 4A/4B] comprising a first plurality of non-volatile memory devices, the first plurality of non-volatile memory devices comprises a first plurality of resistive random-access memory (RRAM) devices [e.g. RRAM, and/or see at least fig. 6, paras. 0031-0033, 0051, 0096, 0099, claims 3, 6; or also in reference of Kulkarni (see at least fig. 6, paras. 0031-0033, 0099, claim 6) or 2023/0078279 by Lee et al. (see para. 0059) that MTJ is considered as a memristor RRAM, and in reference of US patent 12009026 by Ong et al. that resistive random-access memory includes memristors, see Col. 3 lines 4-11] connected in series. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Melanson in accordance with the teaching of Kulkarni regarding resistive memory elements in order to reduce space, and/or to reduce/eliminate special layout structure [para. 0003].
Regarding claim 2, the combination discussed above discloses the apparatus of claim 1, wherein a first end of the first switch is connected to the connection point between the first RRAM device and the second RRAM device, wherein a second end of the first switch is connected to the first comparator, wherein a first end of the second switch is connected to the connection point between the second RRAM device and the third RRAM device, and wherein a second end of the second switch is connected to the second comparator [see at least fig. 5 Melanson].
Regarding claim 3, the combination discussed above discloses the apparatus of claim 1, wherein a plurality of taps of the resistor ladder produces a plurality of reference voltages when the resistor ladder is connected to a predetermined voltage or a predetermined current [see at least Vin fig. 6 Kulkarni], wherein the connection point between the first RRAM device and the second RRAM device is a first tap of the resistor ladder.
Regarding claim 10, the combination discussed above discloses the apparatus of claim 3, wherein the connection point between the second RRAM device and the third RRAM device is a second tap of the resistor ladder [see at least fig. 5 Melanson].
Claims 5-8, 11-13 and 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Melanson (US 6,346,898) in view of Kulkarni er al. (US 2016/0379695) and Mountain (US 11,138,500).
Regarding claim 5, the combination discussed above discloses the apparatus of claim 1. The combination does not disclose the first comparator comprises a second non-volatile memory device, wherein the second non-volatile memory device comprises an RRAM device. However, Mountain discloses a comparator comprises a second non-volatile memory device [see at least memristors in fig. 8; in addition, in reference of US patent 12009026 by Ong et al. that resistive random-access memory includes memristors, see Col. 3 lines 4-11], wherein the second non-volatile memory device comprises an RRAM device [e.g. one of memristor in fig. 8, and in reference of US patent 12009026 by Ong et al. that resistive random-access memory includes memristors, see Col. 3 lines 4-11], such that the combination discloses wherein the first digital output represents a first resistance state [e.g. 1 or 0] of the second non-volatile memory device in response to an application of the first reference voltage and the analog input voltage to the first comparator.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Melanson and Kulkarni in accordance with the teaching of Mountain regarding a comparator in order to provide an improved comparator [Col. 7, lines 39-Col. 8, line 56].
Regarding claim 6, the combination discussed above discloses the apparatus of claim 5, wherein the second non-volatile memory device is programmed to an initial resistance state [see at least col. 7, lines 39-49 memristors need to be programmed] before the application of the first reference voltage and the application of the analog input voltage to the first comparator, wherein the initial resistance state comprises a high-resistance state or a low-resistance state [e.g. high conductive or low conductive].
Regarding claim 7, the combination discussed above discloses the apparatus of claim 6, wherein the first digital output indicates whether the first resistance state of the second non-volatile memory device is the initial resistance state the second non-volatile memory device [the output is either logic high or logic low; the initial resistance state is one of a high-resistance state corresponding to logic high/low or a low-resistance state corresponding to logic low/high, see at least paras. 0028, 0036, 0040, 0041, 0055, 0105 Kulkarni].
Regarding claim 8, the combination discussed above discloses the apparatus of claim 7, further comprising: an encoder [see at least 620 Kulkarni] to generate one or more binary values based at least in part on the first digital output generated by the first comparator.
Regarding claim 11, the combination discussed above discloses the apparatus of claim 1, wherein the second comparator produces a second digital output indicative of a result of a comparison between an analog input voltage and the second reference voltage. The combination does not disclose the second comparator comprises a third non-volatile memory device. However, Mountain discloses a comparator comprises a third non-volatile memory device [see at least memristors in fig. 8]. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Melanson and Kulkarni in accordance with the teaching of Mountain regarding a comparator in order to provide an improved comparator [Col. 7, lines 39-Col. 8, line 56].
Regarding claim 12, the combination discussed above discloses the apparatus of claim 11, wherein the second digital output represents a second resistance state [e.g. low conductive/ high conductive] of the third non-volatile memory device in response to an application of the second reference voltage and the analog input voltage to the second comparator. Also see rejection of claim 5.
Regarding claim 13, the combination discussed above discloses the apparatus of claim 12, wherein the second digital output indicates whether the third resistance state of the second non-volatile memory device is a high-resistance state or a low-resistance state [see at least paras. 0028, 0036, 0055, 0105 Kulkarni; or also can be a MTJ,].
Regarding claim 15 (as best understood), the combination discussed above discloses the apparatus of claim 6, wherein the plurality of RRAM devices is connected in series between a first voltage [e.g. V+] and a second voltage [e.g. V-].
Regarding claim 16 (as best understood), the combination discussed above discloses the apparatus of claim 15, wherein the first RRAM device of the plurality of RRAM devices is connected to the first voltage [see at least fig. 5 of Melanson, fig. 6 of Kulkarni].
Claims 5-8, 11-13 and 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Melanson (US 6,346,898) in view of Kulkarni er al. (US 2016/0379695) and Wang et al. (US 9,240,799).
Regarding claim 5, the combination discussed above discloses the apparatus of claim 1. The combination does not disclose the first comparator comprises a second non-volatile memory device, wherein the second non-volatile memory device comprises an RRAM device. However, Wang discloses a comparator comprises a second non-volatile memory device [e.g. 305; or see at least fig. 3A/3B/4, Col. 3 line 66-Col. 4 line 29], wherein the second non-volatile memory device comprises an RRAM device [e.g. 305; or see at least fig. 3A/3B/4, Col. 3 line 66-Col. 4 line 29, also in reference of Kulkarni (see at least fig. 6, paras. 0031-0033, 0099, claim 6) or 2023/0078279 by Lee et al. (see para. 0059) that MTJ is considered as a memristor RRAM, and in reference of US patent 12009026 by Ong et al. that resistive random-access memory includes memristors, see Col. 3 lines 4-11], such that the combination discloses wherein the first digital output represents a first resistance state [e.g. 1 or 0] of the second non-volatile memory device in response to an application of the first reference voltage and the analog input voltage to the first comparator.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Melanson and Kulkarni in accordance with the teaching of Wang regarding a comparator in order to provide a comparator having small power consumption and small size [see Background].
Regarding claim 6, the combination discussed above discloses the apparatus of claim 5, wherein the second non-volatile memory device [one of MTJs, Wang] is programmed to an initial resistance state [by reset, see at least Col. 15, lines 40-50, figs 10-11 Wang] before the application of the first reference voltage and the application of the analog input voltage to the first comparator, wherein the initial resistance state comprises a high-resistance state or a low-resistance state [see at least Col. 3 line 66-Col. 4 line 20, Col. 8 line 64-Col. 9 line 4, Col. 9 lines 47-57, claims 4 and 9 Wang; also see paras. 0028, 0036, 0040, 0041, 0055, 0056 Kulkarni].
Regarding claim 7, the combination discussed above discloses the apparatus of claim 6, wherein the first digital output indicates whether the first resistance state of the second non-volatile memory device is the initial resistance state the second non-volatile memory device [the output is either logic high or logic low; the initial resistance state is one of a high-resistance state corresponding to logic high/low or a low-resistance state corresponding to logic low/high, see at least Col. 3 line 66-Col. 4 line 20, Col. 8 line 64-Col. 9 line 4, Col. 9 lines 47-57, claims 4 and 9 Wang, and paras. 0028, 0036, 0040, 0041, 0055, 0105 Kulkarni].
Regarding claim 8, the combination discussed above discloses the apparatus of claim 7, further comprising: an encoder [see at least 620 Kulkarni; Col. 12 lines 39-46, Col. 14 lines 25-34, Col. 15 lines 29-39 Wang] to generate one or more binary values based at least in part on the first digital output generated by the first comparator.
Regarding claim 11, the combination discussed above discloses the apparatus of claim 1, wherein the second comparator produces a second digital output indicative of a result of a comparison between an analog input voltage and the second reference voltage. The combination does not disclose the second comparator comprises a second non-volatile memory device. However, Wang discloses a comparator comprises a third non-volatile memory device [e.g. 305; or see at least fig. 3A/3B/4, Col. 3 line 66-Col. 4 line 29]. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Melanson and Kulkarni in accordance with the teaching of Wang regarding a comparator in order to provide a comparator having small power consumption and small size [see Background].
Regarding claim 12, the combination discussed above discloses the apparatus of claim 11, wherein the second digital output represents a second resistance state [see at least Col. 3 line 66-Col. 4 line 20, Col. 8 line 64-Col. 9 line 4, Col. 9 lines 47-57, claims 4 and 9 Wang] of the third non-volatile memory device in response to an application of the second reference voltage and the analog input voltage to the second comparator. Also see rejection of claim 5.
Regarding claim 13, the combination discussed above discloses the apparatus of claim 12, wherein the second digital output indicates whether the third resistance state of the second non-volatile memory device is a high-resistance state or a low-resistance state [see at least Col. 4 lines 8-29 Wang; also can be a MTJ, see at least paras. 0028, 0036, 0055, 0105 Kulkarni].
Regarding claim 15, the combination discussed above discloses the apparatus of claim 6, wherein the plurality of RRAM devices is connected in series between a first voltage [e.g. V+] and a second voltage [e.g. V-].
Regarding claim 16, the combination discussed above discloses the apparatus of claim 15, wherein the first RRAM device of the plurality of RRAM devices is connected to the first voltage [see at least fig. 5 of Melanson, fig. 6 of Kulkarni].
Response to Arguments
The amendment filed 04/02/2026 has been addressed in the above rejection sections. Applicant's arguments have been fully considered but they are not persuasive.
Applicant argues:
‘As acknowledged in the Office Action, "Melanson does not disclose the resistor ladder comprising a first plurality of non-volatile memory devices, the first plurality of non-volatile memory devices comprises a first plurality of resistive random-access memory (RRAM) devices connected in series, and wherein the plurality of RRAM devices are programmable to one or more determined resistances." (Office Action, page 4.) Because Melanson is silent as to any mention of an RRAM device, Melanson also cannot and does not teach or suggest "a plurality of comparators connected to the resistor ladder, wherein a first comparator of the plurality of comparators is connected to a connection point between a first RRAM device and a second RRAM device of the plurality of RRAM devices through a first switch, wherein a reference voltage applied to the first comparator is produced at the connection point between the first RRAM device and the second RRAM device, wherein a second comparator of the plurality of comparators is connected to a connection point between the second RRAM device and a third RRAM device of the plurality of RRAM devices of the resistor ladder through a second switch, wherein a second reference voltage applied to the second comparator is produced at the connection point between the second RRAM device and the third RRAM device, and wherein the first comparator produces a first digital output indicative of a result of a comparison between an analog input voltage applied to the first comparator and the first reference voltage," as recited in amended claim 1. (Emphasis added.)
The Office Action refers to Kulkarni as allegedly teaching the resistor ladder and the comparators recited in claim 1. (Office Action, page 4.) In particular, the Office Action states that the resistor cells 502 and the comparators 600 described in Kulkarni teach the resistor ladder and the comparators recited in claim 1. As shown in FIG. 6 of Kulkarni, the comparators 618 are connected to reference nodes 614a-g that are external to the trimmable resistor blocks 602a-h, and are not connected to the connection points between two resistor cells 502. Furthermore, the reference voltage applied to a comparator 618 is produced at node 614a which is not a connection point between two resistor cells 502. Instead, it is sourced from a node between two multi-component circuit blocks. Accordingly, Kulkarni does not teach or suggest the resistor ladder as recited in amended claim 1 or the features of "a plurality of comparators connected to the resistor ladder, wherein a first comparator of the plurality of comparators is connected to a connection point between a first RRAM device and a second RRAM device of the plurality of RRAM devices through a first switch, wherein a first reference voltage applied to the first comparator is produced at the connection point between the first RRAM device and the second RRAM device, wherein a second comparator of the plurality of comparators is connected to a connection point between the second RRAM device and a third RRAM device of the plurality of RRAM devices of the resistor ladder through a second switch, wherein a second reference voltage applied to the second comparator is produced at the connection point between the second RRAM device and the third RRAM device, and wherein the first comparator produces a first digital output indicative of a result of a comparison between an analog input voltage applied to the first comparator and the first reference voltage," as recited in amended claim 1.’
However, as shown in FIG. 6 of Kulkarni, the comparators 618 are connected to reference nodes 614a-g that are the connection points between two MTJs 604 (or resistors 602a-h), respectively. The reference voltage applied to a comparator 618 is produced at node 614a which is a connection point between two MTJs 604 (or resistors 602a-h). Also, see fig, 4A/4B which shows a resistor. Accordingly, the combination discloses the resistor ladder as recited in amended claim 1 or the features of "a plurality of comparators connected to the resistor ladder, wherein a first comparator of the plurality of comparators is connected to a connection point between a first RRAM device and a second RRAM device of the plurality of RRAM devices through a first switch, wherein a first reference voltage applied to the first comparator is produced at the connection point between the first RRAM device and the second RRAM device, wherein a second comparator of the plurality of comparators is connected to a connection point between the second RRAM device and a third RRAM device of the plurality of RRAM devices of the resistor ladder through a second switch, wherein a second reference voltage applied to the second comparator is produced at the connection point between the second RRAM device and the third RRAM device, and wherein the first comparator produces a first digital output indicative of a result of a comparison between an analog input voltage applied to the first comparator and the first reference voltage," as recited in amended claim 1.’
Regarding claims 2-3, 5-8, 10-13, and 15-16, Applicant’s arguments are based on the arguments discussed above from claim 1. As discuss above, claim 1 is unpatentable at this point. Accordingly, claims 2-3, 5-8, 10-13, and 15-16 are unpatentable at this point.
Conclusion
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/PATRICK C CHEN/Primary Examiner, Art Unit 2836
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