DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
In addressing the rejection ground, each claim may not have been separately discussed to the extent the claimed features are the same as or similar to the previously-discussed features; the previous discussion is construed to apply for the other claims in the same or similar way.
In the office action, “/” should be read as and/or as generally understood. For example, “A/B” means A and B, or A or B.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5-8 and 15-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 5 recites “The apparatus of claim 4”. However, claim 4 has been cancelled. For the purpose of examination, it’s interpreted as --The apparatus of claim 1--.
Claims 6-8 and 15-16 are rejected based on the dependency from claim 5.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-8, 10-13 and 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Melanson (US 6,346,898) in view of Kulkarni er al. (US 2016/0379695) and Mountain (US 11,138,500).
Regarding claim 1, Melanson discloses an apparatus [e.g. fig. 5], comprising: a resistor ladder [e.g. 502s coupled in series] comprising a first plurality of devices [e.g. 502s], wherein a plurality of taps [see the taps of the resistor ladder connected to the inputs of comparator 510s, respectively] of the resistor ladder produces a plurality of reference voltages when the resistor ladder is connected to a predetermined voltage or a predetermined current [e.g. V+/V-], and wherein the first plurality of devices comprises a plurality of resistive devices [e.g. 502s] connected in series; and a plurality of comparators [e.g. 510s] connected to the plurality of taps of the resistor ladder, wherein a first comparator [e.g. the top 510] of the plurality of comparators is connected to a first tap [e.g. the tap between the first 502 from the top and the second 502 from the top] of the resistor ladder through a first switch [e.g. a switch connected in between the first comparator and the first tap], wherein a second comparator [e.g. the second 510 from the top (or the third 510 from the top)] of the plurality of comparators is connected to a second tap [e.g. the node between the third 502 from the top and the fourth 502 from the top (or the node between the second 502 from the top and the third 502 from the top)] of the resistor ladder through a second switch [e.g. a switch connected in between the second comparator and the second tap], wherein the first tap of the resistor ladder corresponds to a connection point between a first device [e.g. the first 502 from the top] and a second device [e.g. the second 502 from the top] of the plurality of devices, and wherein the second tap of the resistor ladder corresponds to a connection point between the second device and a third device [e.g. the third/fourth 502 from the top] of the plurality of devices, wherein the first comparator produces a first digital output [e.g. the output of the comparator] indicative of a result of a comparison between an analog input voltage [e.g the voltage of the bottom input] and the first reference voltage of the plurality of reference voltages.
Melanson does not disclose the resistor ladder comprising a first plurality of non-volatile memory devices, the first plurality of non-volatile memory devices comprises a first plurality of resistive random-access memory (RRAM) devices connected in series, and wherein the plurality of RRAM devices are programmable to one or more determined resistances. However, Kulkarni discloses a resistor ladder [e.g. 502s coupled in series] comprising a first plurality of non-volatile memory devices, the first plurality of non-volatile memory devices comprises a first plurality of resistive random-access memory (RRAM) devices [e.g. RRAM, and/or see at least fig. 6, paras. 0031-0033, 0051, 0096, 0099, claims 3, 6; or also in reference of Kulkarni (see at least fig. 6, paras. 0031-0033, 0099, claim 6) or 2023/0078279 by Lee et al. (see para. 0059) that MTJ is considered as a memristor RRAM, and in reference of US patent 12009026 by Ong et al. that resistive random-access memory includes memristors, see Col. 3 lines 4-11] connected in series, and wherein the plurality of RRAM devices are programmable to one or more determined resistances [see at least paras. 0028, 0036, 0040-0041, 0055-0056]. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Melanson in accordance with the teaching of Kulkarni regarding resistive memory elements in order to reduce space, and/or to reduce/eliminate special layout structure [para. 0003].
The combination does not disclose the first comparator comprises a second non-volatile memory device. However, Mountain discloses a comparator comprises a second non-volatile memory device [see at least memristors in fig. 8; in addition, in reference of US patent 12009026 by Ong et al. that resistive random-access memory includes memristors, see Col. 3 lines 4-11]. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Melanson and Kulkarni in accordance with the teaching of Mountain regarding a comparator in order to provide an improved comparator [Col. 7, lines 39-Col. 8, line 56].
Regarding claim 2, the combination discussed above discloses the apparatus of claim 1, wherein a first end of the first switch is connected to the first tap of the resistor ladder and a second end of the first switch is connected to the first comparator, and wherein a first end of the second switch is connected to the second tap of the resistor ladder and a second end of the second switch is connected to the second comparator [see at least fig. 5 Melanson].
Regarding claim 3, the combination discussed above discloses the apparatus of claim 1, wherein the first tap of the resistor ladder produces the first reference voltage of the plurality of reference voltages [see at least fig. 5 Melanson].
Regarding claim 5 (as best understood), the combination discussed above discloses the apparatus of claim 4, wherein the second non-volatile memory device comprises an RRAM device [e.g. one of memristor in fig. 8, and in reference of US patent 12009026 by Ong et al. that resistive random-access memory includes memristors, see Col. 3 lines 4-11], and wherein the first digital output represents a first resistance state [e.g. 1 or 0] of the second non-volatile memory device in response to an application of the first reference voltage and the analog input voltage to the first comparator.
Regarding claim 6 (as best understood), the combination discussed above discloses the apparatus of claim 5, wherein the second non-volatile memory device is programmed to an initial resistance state [see at least col. 7, lines 39-49 memristors need to be programmed] before the application of the first reference voltage and the application of the analog input voltage to the first comparator, wherein the initial resistance state comprises a high-resistance state or a low-resistance state [e.g. high conductive or low conductive].
Regarding claim 7 (as best understood), the combination discussed above discloses the apparatus of claim 6, wherein the first digital output indicates whether the first resistance state of the second non-volatile memory device is the initial resistance state the second non-volatile memory device [the output is either logic high or logic low; the initial resistance state is one of a high-resistance state corresponding to logic high/low or a low-resistance state corresponding to logic low/high, see at least paras. 0028, 0036, 0040, 0041, 0055, 0105 Kulkarni].
Regarding claim 8 (as best understood), the combination discussed above discloses the apparatus of claim 7, further comprising: an encoder [see at least 620 Kulkarni] to generate one or more binary values based at least in part on the first digital output generated by the first comparator.
Regarding claim 10, the combination discussed above discloses the apparatus of claim 3, wherein the second tap of the resistor ladder produces a second reference voltage of the plurality of reference voltages [see at least fig. 5 Melanson].
Regarding claim 11, the combination discussed above discloses the apparatus of claim 10, wherein the second comparator produces a second digital output indicative of a result of a comparison between an analog input voltage and the second reference voltage. The combination does not disclose the second comparator comprises a second non-volatile memory device. However, Mountain discloses a comparator comprises a second non-volatile memory device [see at least memristors in fig. 8]. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Melanson and Kulkarni in accordance with the teaching of Mountain regarding a comparator in order to provide an improved comparator [Col. 7, lines 39-Col. 8, line 56].
Regarding claim 12, the combination discussed above discloses the apparatus of claim 11, wherein the second digital output represents a second resistance state [e.g. low conductive/ high conductive] of the third non-volatile memory device in response to an application of the second reference voltage and the analog input voltage to the second comparator. Also see rejection of claim 5.
Regarding claim 13, the combination discussed above discloses the apparatus of claim 12, wherein the second digital output indicates whether the third resistance state of the second non-volatile memory device is a high-resistance state or a low-resistance state [see at least paras. 0028, 0036, 0055, 0105 Kulkarni; or also can be a MTJ,].
Regarding claim 15 (as best understood), the combination discussed above discloses the apparatus of claim 6, wherein the plurality of RRAM devices is connected in series between a first voltage [e.g. V+] and a second voltage [e.g. V-].
Regarding claim 16 (as best understood), the combination discussed above discloses the apparatus of claim 15, wherein the first RRAM device of the plurality of RRAM devices is connected to the first voltage [see at least fig. 5 of Melanson, fig. 6 of Kulkarni].
Claims 1-3, 5-8, 10-13 and 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Melanson (US 6,346,898) in view of Kulkarni er al. (US 2016/0379695) and Wang et al. (US 9,240,799).
Regarding claim 1, Melanson discloses an apparatus [e.g. fig. 5], comprising: a resistor ladder [e.g. 502s coupled in series] comprising a first plurality of devices [e.g. 502s], wherein a plurality of taps [see the taps of the resistor ladder connected to the inputs of comparator 510s, respectively] of the resistor ladder produces a plurality of reference voltages when the resistor ladder is connected to a predetermined voltage or a predetermined current [e.g. V+/V-], and wherein the first plurality of devices comprises a plurality of resistive devices [e.g. 502s] connected in series; and a plurality of comparators [e.g. 510s] connected to the plurality of taps of the resistor ladder, wherein a first comparator [e.g. the top 510] of the plurality of comparators is connected to a first tap [e.g. the tap between the first 502 from the top and the second 502 from the top] of the resistor ladder through a first switch [e.g. a switch connected in between the first comparator and the first tap], wherein a second comparator [e.g. the second 510 from the top (or the third 510 from the top)] of the plurality of comparators is connected to a second tap [e.g. the node between the third 502 from the top and the fourth 502 from the top (or the node between the second 502 from the top and the third 502 from the top)] of the resistor ladder through a second switch [e.g. a switch connected in between the second comparator and the second tap], wherein the first tap of the resistor ladder corresponds to a connection point between a first device [e.g. the first 502 from the top] and a second device [e.g. the second 502 from the top] of the plurality of devices, and wherein the second tap of the resistor ladder corresponds to a connection point between the second device and a third device [e.g. the third/fourth 502 from the top] of the plurality of devices, wherein the first comparator produces a first digital output [e.g. the output of the comparator] indicative of a result of a comparison between an analog input voltage [e.g the voltage of the bottom input] and the first reference voltage of the plurality of reference voltages.
Melanson does not disclose the resistor ladder comprising a first plurality of non-volatile memory devices, the first plurality of non-volatile memory devices comprises a first plurality of resistive random-access memory (RRAM) devices connected in series, and wherein the plurality of RRAM devices are programmable to one or more determined resistances. However, Kulkarni discloses a resistor ladder [e.g. 502s coupled in series] comprising a first plurality of non-volatile memory devices, the first plurality of non-volatile memory devices comprises a first plurality of resistive random-access memory (RRAM) devices [e.g. RRAM, and/or see at least fig. 6, paras. 0031-0033, 0051, 0096, 0099, claims 3, 6; or also in reference of Kulkarni (see at least fig. 6, paras. 0031-0033, 0099, claim 6) or 2023/0078279 by Lee et al. (see para. 0059) that MTJ is considered as a memristor RRAM, and in reference of US patent 12009026 by Ong et al. that resistive random-access memory includes memristors, see Col. 3 lines 4-11] connected in series, and wherein the plurality of RRAM devices are programmable to one or more determined resistances [see at least paras. 0028, 0036, 0040-0041, 0055-0056]. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Melanson in accordance with the teaching of Kulkarni regarding resistive memory elements in order to reduce space, and/or to reduce/eliminate special layout structure [para. 0003].
The combination does not disclose the first comparator comprises a second non-volatile memory device. However, Wang discloses a comparator comprises a second non-volatile memory device [see see at least fig. 3A/3B/4, Col. 3 line 66-Col. 4 line 29, also in reference of Kulkarni (see at least fig. 6, paras. 0031-0033, 0099, claim 6) or 2023/0078279 by Lee et al. (see para. 0059) that MTJ is considered as a memristor, and in reference of US patent 12009026 by Ong et al. that resistive random-access memory includes memristors, see Col. 3 lines 4-11]. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Melanson and Kulkarni in accordance with the teaching of Wang regarding a comparator in order to provide a comparator having small power consumption and small size [see Background].
Regarding claim 2, the combination discussed above discloses the apparatus of claim 1, wherein a first end of the first switch is connected to the first tap of the resistor ladder and a second end of the first switch is connected to the first comparator, and wherein a first end of the second switch is connected to the second tap of the resistor ladder and a second end of the second switch is connected to the second comparator [see at least fig. 5 Melanson].
Regarding claim 3, the combination discussed above discloses the apparatus of claim 1, wherein the first tap of the resistor ladder produces the first reference voltage of the plurality of reference voltages [see at least fig. 5 Melanson].
Regarding claim 5 (as best understood), the combination discussed above discloses the apparatus of claim 4, wherein the second non-volatile memory device comprises an RRAM device [e.g. 305; or see at least fig. 3A/3B/4, Col. 3 line 66-Col. 4 line 29, also in reference of Kulkarni (see at least fig. 6, paras. 0031-0033, 0099, claim 6) or 2023/0078279 by Lee et al. (see para. 0059) that MTJ is considered as a memristor RRAM, and in reference of US patent 12009026 by Ong et al. that resistive random-access memory includes memristors, see Col. 3 lines 4-11], and wherein the first digital output represents a first resistance state [see at least Col. 3 line 66-Col. 4 line 20, Col. 8 line 64-Col. 9 line 4, Col. 9 lines 47-57, claims 4 and 9 Wang] of the second non-volatile memory device in response to an application of the first reference voltage and the analog input voltage to the first comparator.
Regarding claim 6 (as best understood), the combination discussed above discloses the apparatus of claim 5, wherein the second non-volatile memory device [one of MTJs, Wang] is programmed to an initial resistance state [by reset, see at least Col. 15, lines 40-50, figs 10-11 Wang] before the application of the first reference voltage and the application of the analog input voltage to the first comparator, wherein the initial resistance state comprises a high-resistance state or a low-resistance state [see at least Col. 3 line 66-Col. 4 line 20, Col. 8 line 64-Col. 9 line 4, Col. 9 lines 47-57, claims 4 and 9 Wang; also see paras. 0028, 0036, 0040, 0041, 0055, 0056 Kulkarni].
Regarding claim 7 (as best understood), the combination discussed above discloses the apparatus of claim 6, wherein the first digital output indicates whether the first resistance state of the second non-volatile memory device is the initial resistance state the second non-volatile memory device [the output is either logic high or logic low; the initial resistance state is one of a high-resistance state corresponding to logic high/low or a low-resistance state corresponding to logic low/high, see at least Col. 3 line 66-Col. 4 line 20, Col. 8 line 64-Col. 9 line 4, Col. 9 lines 47-57, claims 4 and 9 Wang, and paras. 0028, 0036, 0040, 0041, 0055, 0105 Kulkarni].
Regarding claim 8 (as best understood), the combination discussed above discloses the apparatus of claim 7, further comprising: an encoder [see at least 620 Kulkarni; Col. 12 lines 39-46, Col. 14 lines 25-34, Col. 15 lines 29-39 Wang] to generate one or more binary values based at least in part on the first digital output generated by the first comparator.
Regarding claim 10, the combination discussed above discloses the apparatus of claim 3, wherein the second tap of the resistor ladder produces a second reference voltage of the plurality of reference voltages [see at least fig. 5 Melanson].
Regarding claim 11, the combination discussed above discloses the apparatus of claim 10, wherein the second comparator produces a second digital output indicative of a result of a comparison between an analog input voltage and the second reference voltage. The combination does not disclose the second comparator comprises a second non-volatile memory device. However, Wang discloses a comparator comprises a third non-volatile memory device [e.g. 305; or see at least fig. 3A/3B/4, Col. 3 line 66-Col. 4 line 29]. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Melanson and Kulkarni in accordance with the teaching of Wang regarding a comparator in order to provide a comparator having small power consumption and small size [see Background].
Regarding claim 12, the combination discussed above discloses the apparatus of claim 11, wherein the second digital output represents a second resistance state [see at least Col. 3 line 66-Col. 4 line 20, Col. 8 line 64-Col. 9 line 4, Col. 9 lines 47-57, claims 4 and 9 Wang] of the third non-volatile memory device in response to an application of the second reference voltage and the analog input voltage to the second comparator. Also see rejection of claim 5.
Regarding claim 13, the combination discussed above discloses the apparatus of claim 12, wherein the second digital output indicates whether the third resistance state of the second non-volatile memory device is a high-resistance state or a low-resistance state [see at least Col. 4 lines 8-29 Wang; also can be a MTJ, see at least paras. 0028, 0036, 0055, 0105 Kulkarni].
Regarding claim 15 (as best understood), the combination discussed above discloses the apparatus of claim 6, wherein the plurality of RRAM devices is connected in series between a first voltage [e.g. V+] and a second voltage [e.g. V-].
Regarding claim 16 (as best understood), the combination discussed above discloses the apparatus of claim 15, wherein the first RRAM device of the plurality of RRAM devices is connected to the first voltage [see at least fig. 5 of Melanson, fig. 6 of Kulkarni].
Response to Arguments
The amendment filed 06/25/2025 has been addressed in the above rejection sections. Applicant's arguments have been fully considered but they are not persuasive.
Applicant argues on page 7: ‘The Office action refers to FIG. 6 of Kulkarni as allegedly teaching "the resistor ladder comprising a first plurality of non-volatile memory devices, the first plurality of non-volatile memory devices comprises a first plurality of resistive random-access memory (RRAM) devices connected in series," recited in claim 1. (Office action, pg. 4.) The cited portion of Kulkarni merely concerns different type of resistive memory elements that can be used for resistor cells.
In contrast to Kulkarni, amended claim 1 recites " wherein the first plurality of non-volatile memory devices comprises a plurality of resistive random-access memory (RRAM) devices connected in series, and wherein the plurality of RRAM devices are programmable to one or more determined resistances." (Emphasis added.). The resistive memory elements described in Kulkarni do not teach or suggest the plurality of RRAM devices are programmable to one or more determined resistances as recited in amended claim 1. As such, Kulkarni lacks any teaching or suggestion of the resistor ladder as recited in amended claim 1.’
However, Kulkarni discloses wherein the plurality of RRAM devices are programmable to one or more determined resistances [see at least paras. 0028, 0036, 0040-0041, 0055-0056].
Applicant argues on page 8: ‘The Office action further refers to FIG. 5 of Melanson as allegedly teaching "a plurality of comparators connected to the plurality of taps of the resistor ladder, wherein a first comparator of the plurality of comparators is connected to a first tap of the resistor ladder through a first switch, wherein a second comparator of the plurality of comparators is connected to a second tap of the resistor ladder through a second switch, wherein the first tap of the resistor ladder corresponds to a connection point between a first RRAM device and a second RRAM device of the plurality of RRAM devices, and wherein the second tap of the resistor ladder corresponds to a connection point between the second RRAM device and a third RRAM device of the plurality of RRAM devices," as recited in amended claim 1. (Id. at pp. 3-4.). The cited portions of Melanson merely concern a possible configuration of a combined quantitizer and DEM circuitry, including describing a series of resistors, which divide voltage V+/N- into a series of reference voltages. In contrast to Melanson, amended claim 1 recites "wherein the first comparator comprises a second non-volatile memory device, and wherein the first comparator produces a first digital output indicative of a result of a comparison between an analog input voltage and a first reference voltage of the plurality of reference voltages." The combined quantitizer and DEM circuitry described in Melanson do not teach or suggest the first comparator including a non-volatile memory device, and that the first comparator produces a first digital output indicative of a result of a comparison between an analog input voltage and a first reference voltage of the plurality of reference voltages, as recited in amended claim 1. As such, Kulkarni lacks any teaching or suggestion of the resistor ladder as recited in amended claim 1.’
However, the combination of Melanson and Kulkarni discloses wherein the first comparator produces a first digital output [e.g. the output of the comparator] indicative of a result of a comparison between an analog input voltage [e.g the voltage of the bottom input] and the first reference voltage of the plurality of reference voltages.
The combination does not disclose the first comparator comprises a second non-volatile memory device. However, Mountain discloses a comparator comprises a second non-volatile memory device [see at least memristors in fig. 8; in addition, in reference of US patent 12009026 by Ong et al. that resistive random-access memory includes memristors, see Col. 3 lines 4-11]. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Melanson and Kulkarni in accordance with the teaching of Mountain regarding a comparator in order to provide an improved comparator [Col. 7, lines 39-Col. 8, line 56].
Similarly, the combination does not disclose the first comparator comprises a second non-volatile memory device. However, Wang discloses a comparator comprises a second non-volatile memory device [see see at least fig. 3A/3B/4, Col. 3 line 66-Col. 4 line 29, also in reference of Kulkarni (see at least fig. 6, paras. 0031-0033, 0099, claim 6) or 2023/0078279 by Lee et al. (see para. 0059) that MTJ is considered as a memristor, and in reference of US patent 12009026 by Ong et al. that resistive random-access memory includes memristors, see Col. 3 lines 4-11]. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Melanson and Kulkarni in accordance with the teaching of Wang regarding a comparator in order to provide a comparator having small power consumption and small size [see Background].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICK C CHEN whose telephone number is (571)270-7207. The examiner can normally be reached M-F Flexible 9:00-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lincoln Donovan can be reached at 571-272-1988. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PATRICK C CHEN/Primary Examiner, Art Unit 2842