Attorney’s Docket Number: 122750-US-PA
Filing Date: 1/19/2023
Claimed Priority Date: 10/12/2022 (US 63/415,288)
Inventors: Chang et al.
Examiner: Marcos D. Pizarro
DETAILED ACTION
This Office action responds to the amendment filed on 12/24/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 6, 7, 9, 12-15, 21, 23 and 24 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Molina (US 2023/0106976).
Regarding claim 1, Molina (see, e.g., figs. 1G and 2G) shows all aspects of the instant invention including a semiconductor package comprising:
A first semiconductor substrate 105 comprising a pad region and plurality of first pads 106 within the pad region
A plurality of bumps 119/144 disposed on the first pads
A second semiconductor substrate 260 bonded to the first substrate and comprising a plurality of second pads 261 bonded to the bumps, and
A spacing pattern 126 integrally formed on the first substrate and in contact with the second substrate
Regarding claim 9, Molina (see, e.g., figs. 1G, 1I and 2G) shows all aspects of the instant invention including a semiconductor package comprising:
A first semiconductor device 170 comprising an array of first pads 106
A second semiconductor device 260 over the first device and comprising an array of second pads 261
An array of conductive bumps 119/144 bonded between the first and second pads
A spacing pattern 126 disposed around the bumps, and integrally extended between and in contact with the first and second devices, and
An encapsulant 391 encapsulating at least one of the first and second devices.
Regarding claim 21, Molina (see, e.g., figs. 1G, 1I and 2G) shows all aspects of the instant invention including a semiconductor package 300 comprising:
A first semiconductor device 170 comprising a first pad 106
A second semiconductor device 260 over the first device and comprising a second pad 261
A conductive bump 119/144 bonded between the first and second pads
A spacing pattern 126 protruding from a topmost layer of the first device and in contact with the second device
Regarding claims 2, 12 and 24, Molina (see, e.g., fig. 1I) shows that the bumps comprise a metal pillar 119 and a solder cap 144 over the pillar, wherein a height of the spacing pattern 126 is substantially greater than the height of the pillar.
Regarding claim 3, Molina (see, e.g., fig. 1G) shows that the spacing pattern 126 comprises a plurality of spacers at least disposed at a plurality of corners of the pad region.
Regarding claims 6 and 14, Molina (see, e.g., ¶0029/l.2) teaches that the melting temperature of the material of the spacing pattern 126 is substantially equal to or greater than 200°C.
Regarding claims 7 and 15, Molina (see, e.g., ¶0029/l.2) teaches that the material of the spacing pattern comprises Cu, Ni, Au, Co, PI or BCB.
Regarding claim 13, Molina (see, e.g., fig. 1G) shows that the spacing pattern 126 is located at a periphery of a pad region where the array of first pads is disposed.
Regarding claim 23, Molina (see, e.g., fig. 2G) shows that a top surface of the spacing pattern 126 is not coplanar with the top surface of the topmost layer of the first device 170.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 5 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Molina in view of Kim (US 2023/0119548).
Regarding claims 5 and 22, Molina (see, e.g., fig. 2G) teaches a semiconductor package including first 105 and second 260 semiconductor devices. Molina further shows the supporting structure 126 formed between the first and second devices, the first device including a passivation layer 112 formed thereon, and the supporting structure contacting the passivation layer of the first device. However, Molina does not explicitly disclose that the second device 260 includes a second passivation layer such that the supporting structure contacts both passivation layers.
Like Molina, Kim (see, e.g., fig. 7) teaches a semiconductor package 1000A that include first 100A and second 100B devices. Kim, however, shows both the first and second devices including passivation layers IL1/IL2. Kim expressly teaches that the passivation layers provide a bonding surface for bonding and coupling to an external device, e.g., a semiconductor chip, a substrate, or the like” (see, e.g., Kim: ¶0039/ll.15-19). Kim thus teaches the use of passivation layers as bonding interfaces for coupling semiconductor devices and associated structures.
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the semiconductor package of Molina to include a passivation layer formed on the second device, as taught by Kim, such that the supporting structure contacts both the first and second passivation layers. Kim provides an express teaching that passivation layers serve as bonding surfaces for coupling semiconductor devices and related structures.
The proposed modification merely applies a known technique, using a passivation layer as a bonding interface, to a known device, Molina’s second semiconductor device, to yield predictable results, a suitable bonding surface between the semiconductor devices. Providing analogous bonding interfaces on both devices would have been an obvious design choice to improve bonding reliability, interface uniformity, and manufacturing consistency within the semiconductor packaging art.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Molina.
Molina (see, e.g., fig. 2G) discloses a semiconductor package having first 105 and second 260 semiconductor devices, a supporting structure 126 between the devices, passivation layers 112, and other package features. Molina, however, discloses that the package includes a lead frame instead of a redistribution structure over the encapsulant. In another embodiment, Molina (see, e.g., fig. 3) discloses a package that includes a redistribution structure 340 formed over the encapsulant 391. The two embodiments otherwise disclose substantially the same package topology and manufacturing context.
The claim limitation reciting that “the package further comprises a redistribution structure formed over the encapsulant” is met by Molina’s embodiment in figure 3 that expressly discloses a redistribution structure 340 formed over the encapsulant 391. Alternatively, the limitation is met by selecting the redistribution-structure feature from the embodiment that shows the redistribution structure and applying it to the embodiment shown in Fig. 2G that uses a lead frame, because the embodiments are not mutually exclusive, and Molina teaches both options in the context of substantially similar package structures.
The substitution is a routine design choice driven by predictable manufacturing and electrical interconnect considerations and, therefore, would have been within the routine skill of the artisan. There is no disclosure in Molina that would discourage replacing a lead frame with a redistribution structure in the related package embodiments; indeed, Molina’s disclosure of both techniques in substantially similar packages teaches such interchangeable use.
Accordingly, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to employ the redistribution structure of Molina for the same reasons Molina contemplates multiple package interconnect back-end options, and because redistribution structures and lead frames are well-known, alternative package-level interconnect solutions serving comparable electrical/interconnect functions, i.e., providing routing and external interconnects.
Claims 8 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Molina in view of Lin (US 2021/0074661).
Regarding claims 8 and 16, Molina (see, e.g., fig. 1G) shows the pad region comprises first and second regions, wherein the first pads are in the first region and have a first pitch, the second pads are in the second region and have a second pitch, and the spacing pattern 126 is disposed at a periphery of the first region.
Molina further shows that the pads in the first and second regions have the same pitch. Lin teaches that pad pitches may be varied between different regions to effectively use the device to meet different electrical connection requirements, such as signal input/output and power supply/grounding. Lin further teaches that providing different pitches may result in improved signal integrity and power integrity. See, e.g., Lin: par.0032.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to modify the package of Molina such that the pad pitch in the first region is different from the pad pitch in the second region, as taught by Lin. The motivation to do so would have been to meet different electrical connection requirements and improve signal integrity and power integrity.
Response to Arguments
Applicant’s arguments with respect to the claims have been considered but are moot in view of the new grounds of rejection
Conclusion
Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, this action is made final. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire three months from the mailing date of this action. In the event a first reply is filed within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the mailing date of this final action.
Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300. The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Marcos D. Pizarro at (571) 272-1716 and between the hours of 9:00 AM to 7:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Marcos.Pizarro@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (in USA or Canada) or 571-272-1000.
/Marcos D. Pizarro/Primary Examiner, Art Unit 2814
MDP/mdp
February 19, 2026