Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Species III corresponding to Fig. 5A-5B, reading on claims 1-20 in the reply filed on 10/22/2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “T1” has been used to designate both Transistor T1 and Transistor T2 in fig. 6B. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-14 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 7-9, 11-19 of U.S. Patent No 11569248 B2 . Although the claims at issue are not identical, they are not patentably distinct from each other as shown below.
Instant Application
US 11569248 B2
1. An integrated circuit, comprising:
a transistor formed in a first conductive layer;
a first fuse element formed in a second conductive layer and coupled between the transistor and a first data line; and
a second fuse element formed in the second conductive layer and coupled between the transistor and a second data line,
wherein the first fuse element and the second fuse element are disposed at a same side of the transistor.
2. The integrated circuit of claim 1, wherein the second conductive layer is disposed above the first conductive layer, and the first fuse element and the second fuse element are disposed above the first conductive layer.
7. An integrated circuit, comprising:
a transistor formed in a first conductive layer;
a first fuse element formed in a second conductive layer disposed above the first conductive layer; and
a second fuse element formed in the second conductive layer and coupled to the first fuse element,
wherein the transistor is coupled through the first fuse element to a first data line for receiving a first data signal, and
the transistor is coupled through the second fuse element to a second data line for receiving a second data signal,
wherein the first fuse element and the second fuse element are disposed above the transistor.
3. The integrated circuit of claim 1, further comprising: a conductive segment formed in a third conductive layer disposed between the first conductive layer and the second conductive layer, wherein the conductive segment, part of the first fuse element and part of the transistor are overlapped in a layout view, and the first fuse element is coupled through the conductive segment to the transistor.
8. The integrated circuit of claim 7, further comprising: a conductive segment formed in a third conductive layer disposed between the first conductive layer and the second conductive layer, wherein the conductive segment, part of the first fuse element and part of the transistor are overlapped in a layout view, and the first fuse element is coupled through the conductive segment to the transistor.
4. The integrated circuit of claim 1, wherein the first fuse element comprises: a fuse line; and a pair of fuse segments disposed on opposite sides of the fuse line, wherein one of the pair of fuse segments is coupled through a fuse conductive segment formed in the second conductive layer to the second fuse element.
9. The integrated circuit of claim 7, wherein the first fuse element comprises: a fuse line; and a pair of fuse segments disposed on opposite sides of the fuse line, wherein one of the pair of fuse segments is coupled through a fuse conductive segment formed in the second conductive layer to the second fuse element.
5. The integrated circuit of claim 1, wherein the first fuse element comprises: a first fuse line; and a pair of first fuse segments disposed on opposite sides of an end of the first fuse line, wherein the second fuse element comprises: a second fuse line; and a pair of second fuse segments disposed on opposite sides of an end of the second fuse line, wherein one of the pair of first fuse segments is coupled through a fuse conductive segment formed in the second conductive layer to one of the pair of second fuse segments.
11. The integrated circuit of claim 7, wherein the first fuse element comprises: a first fuse line; and a pair of first fuse segments disposed on opposite sides of an end of the first fuse line, wherein the second fuse element comprises: a second fuse line; and a pair of second fuse segments disposed on opposite sides of an end of the second fuse line, wherein one of the pair of first fuse segments is coupled through a fuse conductive segment formed in the second conductive layer to one of the pair of second fuse segments.
6. The integrated circuit of claim 5, wherein one of the pair of first fuse segments, which is coupled to one of the pair of second fuse segments, is further coupled to the transistor through a conductive segment formed in a third conductive layer disposed between the first conductive layer and the second conductive layer.
12. The integrated circuit of claim 11, wherein one of the pair of first fuse segments, which is coupled to one of the pair of second fuse segments, is further coupled to the transistor through a conductive segment formed in a third conductive layer disposed between the first conductive layer and the second conductive layer.
7. An integrated circuit, comprising:
a plurality of electrical fuse cells comprising:
a first conductive segment;
a first transistor formed in a first conductive layer; and
a pair of first fuse elements formed in a second conductive layer disposed above the first conductive layer and coupled to a pair of data lines,
wherein the pair of first fuse elements are coupled together and are coupled through the first conductive segment to the first transistor,
wherein the first conductive segment and the pair of first fuse elements are disposed at a same side of the first transistor.
13. An integrated circuit, comprising:
…wherein the plurality of electrical fuse cells comprise:
a first conductive segment;
a first transistor formed in a first conductive layer; and
a pair of first fuse elements formed in a second conductive layer disposed above the first conductive layer,
wherein the pair of first fuse elements are disposed above the first transistor,
wherein the pair of first fuse elements are coupled together and are coupled through the first conductive segment to the first transistor,
…
The missing limitation of "wherein the first conductive segment and the pair of first fuse elements are disposed at a same side of the first transistor" in the instant claim 7 is obvious from all the relative positions of the first conductive segment and the pair of first fuse elements with respect to the first transistor, cited in claim 13 of the ‘248 patent.
8. The integrated circuit of claim 7, wherein the plurality of electrical fuse cells further comprise: a second transistor formed in the first conductive layer and disposed next to the first transistor; a first program line formed in a third conductive layer disposed between the first conductive layer and the second conductive layer, wherein the first transistor is coupled to the first program line; and a second program line formed in the third conductive layer and disposed next to the first program line, wherein the second transistor is coupled to the second program line, wherein both of the first program line and the second program line are disposed above or below all of the first transistor, the second transistor and the pair of first fuse elements in a layout view.
14. The integrated circuit of claim 13, wherein the plurality of electrical fuse cells further comprise: a second transistor formed in the first conductive layer and disposed next to the first transistor; a first program line formed in a third conductive layer disposed between the first conductive layer and the second conductive layer, wherein the first transistor is coupled to the first program line; and a second program line formed in the third conductive layer and disposed next to the first program line, wherein the second transistor is coupled to the second program line, wherein both of the first program line and the second program line are disposed above or below all of the first transistor, the second transistor and the pair of first fuse elements in a layout view.
9. The integrated circuit of claim 7, further comprising: a third conductive layer disposed between the first conductive layer and the second conductive layer, wherein the first conductive segment is formed in the third conductive layer and is partially overlapped with first transistor and one of the pair of first fuse elements in a layout view.
17. The integrated circuit of claim 13, further comprising: a third conductive layer disposed between the first conductive layer and the second conductive layer, wherein the first conductive segment is formed in the third conductive layer and is partially overlapped with first transistor and one of the pair of first fuse elements in a layout view.
10. The integrated circuit of claim 7, wherein one of the pair of first fuse elements comprises: a fuse line; a first pair of fuse segments disposed on opposite sides of a first end of the fuse line; and a second pair of fuse segments disposed on opposite sides of a second end of the fuse line, wherein the first end and the second end are opposite from each other, wherein one of the first pair of fuse segments is overlapped with the first conductive segment in a layout view, and the second pair of fuse segments and part of the fuse line are overlapped.
16. The integrated circuit of claim 13, wherein one of the pair of first fuse elements comprises: a fuse line; a first pair of fuse segments disposed on opposite sides of a first end of the fuse line; and a second pair of fuse segments disposed on opposite sides of a second end of the fuse line, wherein the first end and the second end are opposite from each other, wherein one of the first pair of fuse segments is overlapped with the first conductive segment in a layout view, and the second pair of fuse segments and part of the fuse line are overlapped...
11. The integrated circuit of claim 7, wherein one of the pair of first fuse elements comprises: a first fuse line; and a pair of first fuse segments disposed on opposite sides of an end of the first fuse line, wherein the other one of the pair of first fuse elements comprises: a second fuse line; and a pair of second fuse segments disposed on opposite sides of an end of the second fuse line, wherein one of the pair of first fuse segments is coupled through a fuse conductive segment formed in the second conductive layer to one of the pair of second fuse segments, and is overlapped with the first conductive segment in a layout view.
15. The integrated circuit of claim 13, wherein one of the pair of first fuse elements comprises: a first fuse line; and a pair of first fuse segments disposed on opposite sides of an end of the first fuse line, wherein the other one of the pair of first fuse elements comprises: a second fuse line; and a pair of second fuse segments disposed on opposite sides of an end of the second fuse line, wherein one of the pair of first fuse segments is coupled through a fuse conductive segment formed in the second conductive layer to one of the pair of second fuse segments, and is overlapped with the first conductive segment in a layout view.
12. The integrated circuit of claim 7, further comprising: a first program line formed in a third conductive layer disposed between the first conductive layer and the second conductive layer, wherein the first transistor is coupled to the first program line; and a second program line formed in the third conductive layer and disposed next to the first program line, wherein both of the first program line and the second program line are disposed above or below the plurality of electrical fuse cells in a layout view, wherein the plurality of electrical fuse cells further comprise: a second transistor formed in the first conductive layer and disposed next to the first transistor, wherein the second transistor is coupled to the second program line; and a pair of second fuse elements formed in the second conductive layer and coupled together by a fuse conductive segment, wherein the pair of first fuse elements are disposed between the pair of second fuse elements and the second transistor in a layout view, wherein the second transistor is coupled through one of the pair of second fuse elements to a first data line of the pair of data lines for receiving a first data signal, and the second transistor is coupled through the other one of the pair of second fuse elements to a second data line of the pair of data lines for receiving a second data signal.
18. The integrated circuit of claim 13, further comprising: a first program line formed in a third conductive layer disposed between the first conductive layer and the second conductive layer, wherein the first transistor is coupled to the first program line; and a second program line formed in the third conductive layer and disposed next to the first program line, wherein both of the first program line and the second program line are disposed above or below the plurality of electrical fuse cells in a layout view, wherein the plurality of electrical fuse cells further comprise: a second transistor formed in the first conductive layer and disposed next to the first transistor, wherein the second transistor is coupled to the second program line; and a pair of second fuse elements formed in the second conductive layer and coupled together by a fuse conductive segment, wherein the pair of first fuse elements are disposed between the pair of second fuse elements and the second transistor in a layout view, wherein the second transistor is coupled through one of the pair of second fuse elements to the first data line for receiving the first data signal, and the second transistor is coupled through the other one of the pair of second fuse elements to the second data line for receiving the second data signal.
13. The integrated circuit of claim 12, wherein the plurality of electrical fuse cells further comprise: a second conductive segment disposed next to the first conductive segment, wherein the pair of second fuse elements are coupled through the second conductive segment to the second transistor, the first conductive segment and the second conductive segment are formed in a fourth conductive layer disposed between the second conductive layer and the third conductive layer, and the second conductive segment and the first conductive segment have different length.
20. The integrated circuit of claim 18, wherein the plurality of electrical fuse cells further comprise: a second conductive segment disposed next to the first conductive segment, wherein the pair of second fuse elements are coupled through the second conductive segment to the second transistor, the first conductive segment and the second conductive segment are formed in a fourth conductive layer disposed between the second conductive layer and the third conductive layer, and the second conductive segment and the first conductive segment have different length.
14. The integrated circuit of claim 12, further comprising: a third program line formed in the third conductive layer and disposed apart from both of the first program line and the second program line; and a fourth program line formed in the third conductive layer and disposed next to the third program line, wherein both of the third program line and the fourth program line are disposed above or below the plurality of electrical fuse cells in a layout view, wherein the plurality of electrical fuse cells further comprise: a third transistor formed in the first conductive layer, wherein the third transistor is coupled to the third program line; a fourth transistor formed in the first conductive layer and disposed next to the third transistor, wherein the fourth transistor is coupled to the fourth program line; a pair of third fuse elements formed in the second conductive layer and coupled together, wherein the pair of second fuse elements are disposed between the pair of first fuse elements and the pair of third fuse elements; and a pair of fourth fuse elements formed in the second conductive layer and coupled together, wherein the pair of third fuse elements are disposed between the pair of second fuse elements and the pair of fourth fuse elements, wherein the third transistor is coupled through one of the pair of third fuse elements to the first data line for receiving the first data signal, and the second transistor is coupled through the other one of the pair of second fuse elements to the second data line for receiving the second data signal.
19. The integrated circuit of claim 18, further comprising: a third program line formed in the third conductive layer and disposed apart from both of the first program line and the second program line; and a fourth program line formed in the third conductive layer and disposed next to the third program line, wherein both of the third program line and the fourth program line are disposed above or below the plurality of electrical fuse cells in a layout view, wherein the plurality of electrical fuse cells further comprise: a third transistor formed in the first conductive layer, wherein the third transistor is coupled to the third program line; a fourth transistor formed in the first conductive layer and disposed next to the third transistor, wherein the fourth transistor is coupled to the fourth program line; a pair of third fuse elements formed in the second conductive layer and coupled together, wherein the pair of second fuse elements are disposed between the pair of first fuse elements and the pair of third fuse elements; and a pair of fourth fuse elements formed in the second conductive layer and coupled together, wherein the pair of third fuse elements are disposed between the pair of second fuse elements and the pair of fourth fuse elements, wherein the third transistor is coupled through one of the pair of third fuse elements to the first data line for receiving the first data signal, and the second transistor is coupled through the other one of the pair of second fuse elements to the second data line for receiving the second data signal.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 15-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 15 recites the following limitations:
In lines 6-7, “the first side of the second transistor”.
In lines 8-9, “the first side of the first fuse element”.
In lines 10-11, “the first side of the second fuse element”.
There is insufficient antecedent basis for these limitations in the claim. For examination purposes, they will be interpreted as “a first side of the second transistor”, “a first side of the first fuse element” and “a first side of the second fuse element” respectively.
Dependent claims 16-20 do not cure the indefiniteness and therefore, rejected as well.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 7, 9-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang et al. (US 20170345827 A1; hereinafter “Chang”).
In re claim 1, Chang discloses in figs. 2-3, 4B, an integrated circuit, comprising:
a transistor 202 formed in a first conductive layer (transistor 202 formed in the FEOL comprising a word line, which is a conductive layer; ¶19, 24. Furthermore, Chang discloses the first metal layer (M2), the second metal layer (M0) and the FEOL structure are each on different layers of the integrated circuit; ¶20. A first conductive layer will be referred to as “COND1” hereinafter);
a first fuse element 204 formed in a second conductive layer M2 and coupled between the transistor and a first data line VDDQI (bit0) (¶27); and
a second fuse element 206 formed in the second conductive layer M2 and coupled between the transistor 202 and a second data line VDDQI (bit2) (¶27),
wherein the first fuse element 204 and the second fuse element 206 are disposed at a same side of the transistor 202.
In re claim 2, Chang discloses in figs. 2-3, 4B, the integrated circuit of claim 1,
wherein the second conductive layer M0 is disposed above the first conductive layer COND1, and
the first fuse element 204 and the second fuse element 206 are disposed above the first conductive layer COND1.
In re claim 3, Chang discloses in figs. 2-3, 4B, the integrated circuit of claim 1, further comprising:
a conductive segment 323/325 formed in a third conductive layer M1 disposed between the first conductive layer COND1 and the second conductive layer M2 (¶27),
wherein the conductive segment 323/325, part of the first fuse element 204 and part of the transistor 202 are overlapped in a layout view (fig. 3), and
the first fuse element 204 is coupled through the conductive segment 323/325 to the transistor 202.
In re claim 7, Chang discloses in figs. 2-3, 4B, an integrated circuit, comprising:
a plurality of electrical fuse cells comprising:
a first conductive segment 323/325 (¶27);
a first transistor 202 formed in a first conductive layer (transistor 202 formed in the FEOL comprising a word line, which is a conductive layer; ¶19, 24. Furthermore, Chang discloses the first metal layer (M2), the second metal layer (M0) and the FEOL structure are each on different layers of the integrated circuit; ¶20. A first conductive layer will be referred to as “COND1” hereinafter); and
a pair of first fuse elements 204, 206 formed in a second conductive layer M2 disposed above the first conductive layer COND1 and coupled to a pair of data lines bit0, bit1 (¶27),
wherein the pair of first fuse elements 204, 206 are coupled together and are coupled through the first conductive segment to the first transistor 202,
wherein the first conductive segment 323/325 and the pair of first fuse elements 204, 206 are disposed at a same side of the first transistor 202.
In re claim 9, Chang discloses in figs. 2-3, 4B, the integrated circuit of claim 7, further comprising:
a third conductive layer M1, M0 disposed between the first conductive layer COND1 and the second conductive layer M2,
wherein the first conductive segment 323/325 is formed in the third conductive layer M1, M0 and is partially overlapped with first transistor 202 and one of the pair of first fuse elements 204, 206 in a layout view (fig. 3).
In re claim 10, Chang discloses in figs. 2-3, 4B, the integrated circuit of claim 7, wherein one of the pair of first fuse elements 204 comprises:
a fuse line 308 (¶24);
a first pair of fuse segments 314, 316 disposed on opposite sides of a first end (e.g., right end) of the fuse line 308 (¶24); and
a second pair of fuse segments 310, 312 disposed on opposite sides of a second end (e.g., left end) of the fuse line 308 (¶24),
wherein the first end and the second end are opposite from each other,
wherein one of the first pair of fuse segments 314 is overlapped with the first conductive segment 322 in a layout view (fig. 3), and
the second pair of fuse segments 310, 312 and part of the fuse line 308 are overlapped (as shown in fig. 3, the second pair of fuse segments 310, 312 and part of the fuse line 308 are overlapped along a vertical direction).
Claim(s) 15-16, 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang et al. (US 20190287900 A1; hereinafter “Chang’900).
In re claim 15, Chang’900 discloses in figs. 1-7, an integrated circuit, comprising:
a first transistor 250b coupled to a first data line BL0 (¶28);
a second transistor 250a coupled to a second data line BL1 (¶28);
a first fuse element (right end portion of 202b; hereinafter “FE1”) coupled to the first transistor 250b and disposed at a first side of the first transistor 250b (¶28);
a second fuse element (left end portion of 202b; hereinafter “FE2”) coupled to the first transistor 250b and disposed at the first side of the second transistor (as best understood; the first side of the first transistor, 250b);
a third fuse element (right end portion of 202a; hereinafter “FE3”) coupled to the second transistor 250a and disposed at the first side of the first fuse element (as best understood, a first side of the first fuse element FE1); and
a fourth fuse element (left end portion of 202a; hereinafter “FE4”) coupled to the second transistor 250a and disposed at the first side of the second fuse element (as best understood, a first side of the second fuse element FE2).
In re claim 16, Chang’900 discloses in figs. 1-7, the integrated circuit of claim 15, wherein the first fuse element FE1 is between the first transistor 250b and the third fuse element FE3.
In re claim 18, Chang’900 discloses in figs. 1-7, the integrated circuit of claim 15, wherein the first fuse element FE1 is disposed at a second side (e.g., a side towards the page, in fig. 7) of the third fuse element FE3.
In re claim 19, Chang’900 discloses in figs. 1-7, the integrated circuit of claim 15, wherein the second fuse element FE2 is disposed at a second side (e.g., a side towards the page, in fig. 7) of the fourth fuse element FE4.
In re claim 20, Chang’900 discloses in figs. 1-7, the integrated circuit of claim 15, wherein the second transistor 250a is arranged next to the first transistor 250b in a layout view (based on figs. 6-7, the first transistor 250b is arranged next to the second transistor 250a in the lower metal level).
Claim(s) 15, 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hall et al. (US 20180025982 A1; hereinafter “Hall”).
In re claim 15, Hall discloses in figs. 7-8, an integrated circuit, comprising:
a first transistor 170 coupled to a first data line (e.g., a S/D node of transistor 200 of the read block 196, as shown in fig. 7) (¶38, 46);
a second transistor 174 coupled to a second data line (e.g., a S/D node of transistor 204 of the read block 196, as shown in fig. 7) (¶38, 46);
a first fuse element 132b coupled to the first transistor 170 and disposed at a first side of the first transistor 170 (¶38);
a second fuse element 132b coupled to the first transistor 170 and disposed at the first side of the second transistor 174 (¶38);
a third fuse element 132e coupled to the second transistor 174 and disposed at the first side of the first fuse element 132b; and
a fourth fuse element 132f coupled to the second transistor 174 and disposed at the first side of the second fuse element 132a.
In re claim 17, Hall discloses in figs. 7-8, wherein a second fuse element 132a is between a second transistor 174 and a fourth fuse element 143f.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang as applied to claim 1 above, and further in view of Hall et al. (US 20180025982 A1; hereinafter “Hall”).
In re claim 4, Chang discloses in figs. 2-3, 4B, the integrated circuit of claim 1,
wherein the first fuse element 204 comprises:
a fuse line 308 (¶24); and
a pair of fuse segments 314, 316 disposed on opposite sides of the fuse line 308 (¶24).
Chang does not expressly disclose wherein one of the pair of fuse segments is coupled through a fuse conductive segment formed in the second conductive layer to the second fuse element.
In the same field of endeavor, Hall discloses in figs. 7-8, an integrated circuit, wherein one of a pair of fuse segments 132a is coupled through a fuse conductive segment 134a formed in a second conductive layer to a second fuse element 132b (¶38, 58).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Hall into the integrated circuit of Chang in order to establish a low resistance conductive path between adjacent fuses and the fuse transistor and efficiently program vertical OTP fuse, or read the resistance value of the fuse (¶30 of Hall).
In re claim 5, Chang discloses in figs. 2-3, 4B, the integrated circuit of claim 1,
wherein the first fuse element 204 comprises:
a first fuse line 308 (¶24); and a pair of first fuse segments 314, 316 disposed on opposite sides of an end of the first fuse line 308 (¶24),
wherein the second fuse element 206 comprises:
a second fuse line 308 (¶24); and
a pair of second fuse segments 314, 316 disposed on opposite sides of an end of the second fuse line 308.
Chang does not expressly disclose wherein one of the pair of first fuse segments is coupled through a fuse conductive segment formed in the second conductive layer to one of the pair of second fuse segments.
In the same field of endeavor, Hall discloses in figs. 7-8, an integrated circuit, wherein one of the pair of first fuse segments 132a is coupled through a fuse conductive segment 134a formed in a second conductive layer to one of the pair of second fuse segments 132b (¶38, 58).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Hall into the integrated circuit of Chang in order to establish a low resistance conductive path between adjacent fuses and the fuse transistor and efficiently program vertical OTP fuse, or read the resistance value of the fuse (¶30 of Hall).
In re claim 6, Chang, as modified by Hall, discloses the integrated circuit of claim 5 outlined above.
Chang further discloses in figs. 2-3, 4B, the integrated circuit of claim 5,
wherein one of the pair of first fuse segments, which is coupled to one of the pair of second fuse segments, is further coupled to the transistor through a conductive segment M1 formed in a third conductive layer M1 disposed between the first conductive layer COND1 and the second conductive layer M2.
Allowable Subject Matter
Claims 8, 11-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 8, Closest prior art of record, alone or in combination, does not expressly disclose all the limitations of claim 8 including a first program line formed in a third conductive layer disposed between the first conductive layer and the second conductive layer, wherein both of the first program line and the second program line are disposed above or below all of the first transistor, the second transistor and the pair of first fuse elements in a layout view, in combination with all limitations cited in claim 7.
Regarding claim 11, Closest prior art of record, alone or in combination, does not expressly disclose all the limitations of claim 11 including wherein one of the pair of first fuse segments is coupled through a fuse conductive segment formed in the second conductive layer to one of the pair of second fuse segments, and is overlapped with the first conductive segment in a layout view, in combination with all limitations cited in claim 7.
Regarding claim 12, Closest prior art of record, alone or in combination, does not expressly disclose all the limitations of claim 12 including relative positions of the first program line and the second program line relative to the electrical fuse cells in a layout view, a pair of second fuse elements formed in the second conductive layer and coupled together by a fuse conductive segment, wherein the pair of first fuse elements are disposed between the pair of second fuse elements and the second transistor in a layout view, in combination with all limitations cited in claim 7.
Dependent claims 13-14 are indicated allowable based on their dependency on claim 12.
Conclusion
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/NILUFA RAHIM/Primary Examiner, Art Unit 2893