Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
The amendment filed on 05/12/2026 has been entered. The present Office action is made with all the suggested amendments being fully considered. Claims 1, 7, and 15 are independent claims. Claims 1, 3, 7-12, 14-15, and 20 are amended. FIG. 6B is amended. Accordingly, pending in this application are claims 1-20.
Response to Amendment
Applicant’s amendments to Claim 15 have overcome all claim rejections under 35 U.S.C. § 112 previously set forth in the Non-Final Office action mailed on 02/13/2026. Accordingly, all previous claim rejections under 35 U.S.C. § 112 have been withdrawn.
Response to Arguments
Applicant's arguments filed 05/12/2026 have been fully considered but they are not persuasive.
Applicant argues regarding Double Patenting:
“Independent claims 1 and 7 are amended such that the double patenting rejection may be rendered moot”.
Examiner disagrees with this assertion. As described below, the amended limitations of claims 1 and 7 have been found obvious in view of claims 3 and 9 of the ‘248 patent. Therefore, the double patenting rejection has been maintained.
Applicant argues regarding claim 1:
Claim 1 is amended and recites, in part: "the transistor is partially overlapped with the first fuse element in a layout view."
Based on fig. 3 of Chang, the Office Action does not show that Chang discloses that the transistor 202 is partially overlapped with the eFuse 204 in the layout view.
Accordingly, the Office Action fails to show that Chang teaches the limitations of "the transistor is partially overlapped with the first fuse element in a layout view" as explicitly shown in claim 1.
Examiner respectfully disagrees with the above assertion.
Chang discloses in fig. 4B, wherein the transistor 202 is partially overlapped with the first fuse element 204 in a cross-sectional view. One of ordinary skill in the art would have recognized the when the transistor 202 is partially overlapped with the first fuse element 204 in a cross-sectional view, then at least a portion of the transistor 202 is partially overlapped with the first fuse element 204 in a layout view as well. Therefore, the claimed feature “wherein the transistor is partially overlapped with the first fuse element in a layout view” is obvious to one of ordinary skilled in the art before the effective filing date of the claimed invention in view of Chang’s teachings shown in fig. 4B.
Therefore, the rejections of claim 1 and its dependent claims stand rejected.
Applicant argues regarding claim 7:
Claim 7 is amended to recite features corresponding to those recited in claim 1. Applicant respectfully submits that for analogous reasons as recited in the response to the rejection of claim 1, claim 7 is allowable over the cited references as well.
Examiner respectfully disagrees with the above assertion.
Chang discloses in fig. 4B, wherein the transistor 202 is partially overlapped with the first fuse element 204 in a cross-sectional view. One of ordinary skill in the art would have recognized the when the transistor 202 is partially overlapped with the first fuse element 204 in a cross-sectional view, then at least a portion of the transistor 202 is partially overlapped with the first fuse element 204 in a layout view as well. Therefore, the claimed feature “wherein the transistor is partially overlapped with the first fuse element in a layout view” is obvious to one of ordinary skilled in the art before the effective filing date of the claimed invention in view of Chang’s teachings shown in fig. 4B.
Applicant argues regarding claims 2-6:
Claims 2-6 depend from claim 1. It is respectfully submitted that these dependent claims are also allowable by reason of depending from the allowable claims 1 and 7 as well as for adding additional features.
Examiner respectfully disagrees with the above assertion. Claims 1 and 7 have been found unpatentable over Chang, not allowable in their current form.
Applicant argues regarding claim 15 over Chang’900:
Claim 15 recites, in part: "the first transistor is partially overlapped with the first fuse element in a layout view, and the second transistor is partially overlapped with the second fuse element in the layout view."
The Office Action alleged (on Page 18) that, in Figs. 1-7 of Chang'900, the transistor 250b corresponds to the "first transistor" in claim 15, the transistor 250a corresponds to the "second transistor" in claim 15, the right end portion of fuse line 202b corresponds to the "first fuse element" in claim 15, and the left end portion of fuse line13
Based on the above, in Fig. 7 of Chang'900, the right end portion of fuse line 202b and the left end portion of fuse line 202b are disposed between the transistor 250b and the transistor 25oa in the top view.
The Office Action does not show that Chang'900 discloses that the transistor 250b is partially overlapped with the right end portion of fuse line 202b in the layout view and the transistor 25oa is partially overlapped with the left end portion of fuse line 202b in the layout view.
Accordingly, the Office Action fails to show that Chang'900 teaches the limitations of "the first transistor is partially overlapped with the first fuse element in a layout view, and the second transistor is partially overlapped with the second fuse element in the layout view" as explicitly shown in claim 15.
Examiner respectfully disagrees with the above assertion.
Chang’900 discloses wherein the first transistor 250b is partially overlapped with the first fuse element (FE1) in a layout view, and the second transistor 250a is partially overlapped with the second fuse element (FE2) in the layout view (fig. 6; ¶27; “an area 308 for the NMOS program transistor of a first eFuse cell connected to word line WL0 in the M0 layer; an area 310 for the NMOS program transistor of a second eFuse cell connected to word line WL1 in the M0 layer”. As shown in fig. 6, the Program NMOS transistors and the fuse (2R) are partially overlapped in a layout view).
Applicant argues regarding claim 15 over Hall:
In addition, the Office Action alleged (on Page 19) that, in FIGs. 7-8 of Hall, the transistor 170 corresponds to the "first transistor" in claim 15, the transistor 174 corresponds to the "second transistor" in claim 15, the fuse 132b corresponds to the "first fuse element" in claim 15, and the fuse 132a corresponds to the "second fuse element" in claim 15. Fig. 7 of Hall is reproduced below for explanation.
Based on the above, in Fig. 7 of Hall, the fuse 132b and the fuse 132a are coupled to the transistor 170.
The Office Action does not show that Hall discloses that the transistor 170 is partially overlapped with the fuse 132b in the layout view, and the transistor 174 is partially overlapped with the fuse 132a in the layout view. Accordingly, the Office Action fails to show that Hall teaches the limitations of "the first transistor is partially overlapped with the first fuse element in a layout view, and the second transistor is partially overlapped with the second fuse element in the layout view" as explicitly shown in claim 15.
Examiner respectfully disagrees with the above assertion. The arguments are moot as Hall has not been applied in this current rejection, necessitated by the amendments added into claim 15.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-14 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 7-9, 11-19 of U.S. Patent No 11569248 B2 . Although the claims at issue are not identical, they are not patentably distinct from each other as shown below.
Instant Application
US 11569248 B2
1. An integrated circuit, comprising:
a transistor formed in a first conductive layer;
a first fuse element formed in a second conductive layer and coupled between the transistor and a first data line; and
a second fuse element formed in the second conductive layer and coupled between the transistor and a second data line,
wherein the first fuse element and the second fuse element are disposed at a same side of the transistor,
wherein the transistor is partially overlapped with the first fuse element in a layout view.
2. The integrated circuit of claim 1, wherein the second conductive layer is disposed above the first conductive layer, and the first fuse element and the second fuse element are disposed above the first conductive layer.
7. An integrated circuit, comprising:
a transistor formed in a first conductive layer;
a first fuse element formed in a second conductive layer disposed above the first conductive layer; and
a second fuse element formed in the second conductive layer and coupled to the first fuse element,
wherein the transistor is coupled through the first fuse element to a first data line for receiving a first data signal, and
the transistor is coupled through the second fuse element to a second data line for receiving a second data signal,
wherein the first fuse element and the second fuse element are disposed above the transistor.
3. (Original) The integrated circuit of claim 1, further comprising:
…wherein the conductive segment, part of the first fuse element and part of the transistor are overlapped in a layout view…
3. The integrated circuit of claim 1, further comprising: a conductive segment formed in a third conductive layer disposed between the first conductive layer and the second conductive layer, wherein the conductive segment, part of the first fuse element and part of the transistor are overlapped in a layout view, and the first fuse element is coupled through the conductive segment to the transistor.
8. The integrated circuit of claim 7, further comprising: a conductive segment formed in a third conductive layer disposed between the first conductive layer and the second conductive layer, wherein the conductive segment, part of the first fuse element and part of the transistor are overlapped in a layout view, and the first fuse element is coupled through the conductive segment to the transistor.
4. The integrated circuit of claim 1, wherein the first fuse element comprises: a fuse line; and a pair of fuse segments disposed on opposite sides of the fuse line, wherein one of the pair of fuse segments is coupled through a fuse conductive segment formed in the second conductive layer to the second fuse element.
9. The integrated circuit of claim 7, wherein the first fuse element comprises: a fuse line; and a pair of fuse segments disposed on opposite sides of the fuse line, wherein one of the pair of fuse segments is coupled through a fuse conductive segment formed in the second conductive layer to the second fuse element.
5. The integrated circuit of claim 1, wherein the first fuse element comprises: a first fuse line; and a pair of first fuse segments disposed on opposite sides of an end of the first fuse line, wherein the second fuse element comprises: a second fuse line; and a pair of second fuse segments disposed on opposite sides of an end of the second fuse line, wherein one of the pair of first fuse segments is coupled through a fuse conductive segment formed in the second conductive layer to one of the pair of second fuse segments.
11. The integrated circuit of claim 7, wherein the first fuse element comprises: a first fuse line; and a pair of first fuse segments disposed on opposite sides of an end of the first fuse line, wherein the second fuse element comprises: a second fuse line; and a pair of second fuse segments disposed on opposite sides of an end of the second fuse line, wherein one of the pair of first fuse segments is coupled through a fuse conductive segment formed in the second conductive layer to one of the pair of second fuse segments.
6. The integrated circuit of claim 5, wherein one of the pair of first fuse segments, which is coupled to one of the pair of second fuse segments, is further coupled to the transistor through a conductive segment formed in a third conductive layer disposed between the first conductive layer and the second conductive layer.
12. The integrated circuit of claim 11, wherein one of the pair of first fuse segments, which is coupled to one of the pair of second fuse segments, is further coupled to the transistor through a conductive segment formed in a third conductive layer disposed between the first conductive layer and the second conductive layer.
7. An integrated circuit, comprising:
a plurality of electrical fuse cells comprising:
a first conductive segment;
a first transistor formed in a first conductive layer; and
a pair of first fuse elements formed in a second conductive layer disposed above the first conductive layer and coupled to a pair of data lines,
wherein the pair of first fuse elements are coupled together and are coupled through the first conductive segment to the first transistor,
wherein the first conductive segment and the pair of first fuse elements are disposed at a same side of the first transistor,
wherein the first transistor is partially overlapped with one of the pair of first fuse elements in a layout view.
13. An integrated circuit, comprising:
…wherein the plurality of electrical fuse cells comprise:
a first conductive segment;
a first transistor formed in a first conductive layer; and
a pair of first fuse elements formed in a second conductive layer disposed above the first conductive layer,
wherein the pair of first fuse elements are disposed above the first transistor,
wherein the pair of first fuse elements are coupled together and are coupled through the first conductive segment to the first transistor,
…
The missing limitation of "wherein the first conductive segment and the pair of first fuse elements are disposed at a same side of the first transistor" in the instant claim 7 is obvious from all the relative positions of the first conductive segment and the pair of first fuse elements with respect to the first transistor, cited in claim 13 of the ‘248 patent.
Furthermore, the amended claim limitation “wherein the first transistor is partially overlapped with one of the pair of first fuse elements in a layout view” is obvious from claim 9 of the ‘248 patent, as shown below.
9. (Original) The integrated circuit of claim 7, further comprising: a third conductive layer disposed between the first conductive layer and the second conductive layer, wherein the first conductive segment is formed in the third conductive layer and is partially overlapped with first transistor and one of the pair of first fuse elements in a layout view.
8. The integrated circuit of claim 7, wherein the plurality of electrical fuse cells further comprise: a second transistor formed in the first conductive layer and disposed next to the first transistor; a first program line formed in a third conductive layer disposed between the first conductive layer and the second conductive layer, wherein the first transistor is coupled to the first program line; and a second program line formed in the third conductive layer and disposed next to the first program line, wherein the second transistor is coupled to the second program line, wherein both of the first program line and the second program line are disposed above or below all of the first transistor, the second transistor and the pair of first fuse elements in a layout view.
14. The integrated circuit of claim 13, wherein the plurality of electrical fuse cells further comprise: a second transistor formed in the first conductive layer and disposed next to the first transistor; a first program line formed in a third conductive layer disposed between the first conductive layer and the second conductive layer, wherein the first transistor is coupled to the first program line; and a second program line formed in the third conductive layer and disposed next to the first program line, wherein the second transistor is coupled to the second program line, wherein both of the first program line and the second program line are disposed above or below all of the first transistor, the second transistor and the pair of first fuse elements in a layout view.
9. The integrated circuit of claim 7, further comprising: a third conductive layer disposed between the first conductive layer and the second conductive layer, wherein the first conductive segment is formed in the third conductive layer and is partially overlapped with first transistor and one of the pair of first fuse elements in a layout view.
17. The integrated circuit of claim 13, further comprising: a third conductive layer disposed between the first conductive layer and the second conductive layer, wherein the first conductive segment is formed in the third conductive layer and is partially overlapped with first transistor and one of the pair of first fuse elements in a layout view.
10. The integrated circuit of claim 7, wherein one of the pair of first fuse elements comprises: a fuse line; a first pair of fuse segments disposed on opposite sides of a first end of the fuse line; and a second pair of fuse segments disposed on opposite sides of a second end of the fuse line, wherein the first end and the second end are opposite from each other, wherein one of the first pair of fuse segments is overlapped with the first conductive segment in a layout view, and the second pair of fuse segments and part of the fuse line are overlapped.
16. The integrated circuit of claim 13, wherein one of the pair of first fuse elements comprises: a fuse line; a first pair of fuse segments disposed on opposite sides of a first end of the fuse line; and a second pair of fuse segments disposed on opposite sides of a second end of the fuse line, wherein the first end and the second end are opposite from each other, wherein one of the first pair of fuse segments is overlapped with the first conductive segment in a layout view, and the second pair of fuse segments and part of the fuse line are overlapped...
11. The integrated circuit of claim 7, wherein one of the pair of first fuse elements comprises: a first fuse line; and a pair of first fuse segments disposed on opposite sides of an end of the first fuse line, wherein the other one of the pair of first fuse elements comprises: a second fuse line; and a pair of second fuse segments disposed on opposite sides of an end of the second fuse line, wherein one of the pair of first fuse segments is coupled through a fuse conductive segment formed in the second conductive layer to one of the pair of second fuse segments, and is overlapped with the first conductive segment in a layout view.
15. The integrated circuit of claim 13, wherein one of the pair of first fuse elements comprises: a first fuse line; and a pair of first fuse segments disposed on opposite sides of an end of the first fuse line, wherein the other one of the pair of first fuse elements comprises: a second fuse line; and a pair of second fuse segments disposed on opposite sides of an end of the second fuse line, wherein one of the pair of first fuse segments is coupled through a fuse conductive segment formed in the second conductive layer to one of the pair of second fuse segments, and is overlapped with the first conductive segment in a layout view.
12. The integrated circuit of claim 7, further comprising: a first program line formed in a third conductive layer disposed between the first conductive layer and the second conductive layer, wherein the first transistor is coupled to the first program line; and a second program line formed in the third conductive layer and disposed next to the first program line, wherein both of the first program line and the second program line are disposed above or below the plurality of electrical fuse cells in a layout view, wherein the plurality of electrical fuse cells further comprise: a second transistor formed in the first conductive layer and disposed next to the first transistor, wherein the second transistor is coupled to the second program line; and a pair of second fuse elements formed in the second conductive layer and coupled together by a fuse conductive segment, wherein the pair of first fuse elements are disposed between the pair of second fuse elements and the second transistor in a layout view, wherein the second transistor is coupled through one of the pair of second fuse elements to a first data line of the pair of data lines for receiving a first data signal, and the second transistor is coupled through the other one of the pair of second fuse elements to a second data line of the pair of data lines for receiving a second data signal.
18. The integrated circuit of claim 13, further comprising: a first program line formed in a third conductive layer disposed between the first conductive layer and the second conductive layer, wherein the first transistor is coupled to the first program line; and a second program line formed in the third conductive layer and disposed next to the first program line, wherein both of the first program line and the second program line are disposed above or below the plurality of electrical fuse cells in a layout view, wherein the plurality of electrical fuse cells further comprise: a second transistor formed in the first conductive layer and disposed next to the first transistor, wherein the second transistor is coupled to the second program line; and a pair of second fuse elements formed in the second conductive layer and coupled together by a fuse conductive segment, wherein the pair of first fuse elements are disposed between the pair of second fuse elements and the second transistor in a layout view, wherein the second transistor is coupled through one of the pair of second fuse elements to the first data line for receiving the first data signal, and the second transistor is coupled through the other one of the pair of second fuse elements to the second data line for receiving the second data signal.
13. The integrated circuit of claim 12, wherein the plurality of electrical fuse cells further comprise: a second conductive segment disposed next to the first conductive segment, wherein the pair of second fuse elements are coupled through the second conductive segment to the second transistor, the first conductive segment and the second conductive segment are formed in a fourth conductive layer disposed between the second conductive layer and the third conductive layer, and the second conductive segment and the first conductive segment have different length.
20. The integrated circuit of claim 18, wherein the plurality of electrical fuse cells further comprise: a second conductive segment disposed next to the first conductive segment, wherein the pair of second fuse elements are coupled through the second conductive segment to the second transistor, the first conductive segment and the second conductive segment are formed in a fourth conductive layer disposed between the second conductive layer and the third conductive layer, and the second conductive segment and the first conductive segment have different length.
14. The integrated circuit of claim 12, further comprising: a third program line formed in the third conductive layer and disposed apart from both of the first program line and the second program line; and a fourth program line formed in the third conductive layer and disposed next to the third program line, wherein both of the third program line and the fourth program line are disposed above or below the plurality of electrical fuse cells in a layout view, wherein the plurality of electrical fuse cells further comprise: a third transistor formed in the first conductive layer, wherein the third transistor is coupled to the third program line; a fourth transistor formed in the first conductive layer and disposed next to the third transistor, wherein the fourth transistor is coupled to the fourth program line; a pair of third fuse elements formed in the second conductive layer and coupled together, wherein the pair of second fuse elements are disposed between the pair of first fuse elements and the pair of third fuse elements; and a pair of fourth fuse elements formed in the second conductive layer and coupled together, wherein the pair of third fuse elements are disposed between the pair of second fuse elements and the pair of fourth fuse elements, wherein the third transistor is coupled through one of the pair of third fuse elements to the first data line for receiving the first data signal, and the second transistor is coupled through the other one of the pair of second fuse elements to the second data line for receiving the second data signal.
19. The integrated circuit of claim 18, further comprising: a third program line formed in the third conductive layer and disposed apart from both of the first program line and the second program line; and a fourth program line formed in the third conductive layer and disposed next to the third program line, wherein both of the third program line and the fourth program line are disposed above or below the plurality of electrical fuse cells in a layout view, wherein the plurality of electrical fuse cells further comprise: a third transistor formed in the first conductive layer, wherein the third transistor is coupled to the third program line; a fourth transistor formed in the first conductive layer and disposed next to the third transistor, wherein the fourth transistor is coupled to the fourth program line; a pair of third fuse elements formed in the second conductive layer and coupled together, wherein the pair of second fuse elements are disposed between the pair of first fuse elements and the pair of third fuse elements; and a pair of fourth fuse elements formed in the second conductive layer and coupled together, wherein the pair of third fuse elements are disposed between the pair of second fuse elements and the pair of fourth fuse elements, wherein the third transistor is coupled through one of the pair of third fuse elements to the first data line for receiving the first data signal, and the second transistor is coupled through the other one of the pair of second fuse elements to the second data line for receiving the second data signal.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 15-16, 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang et al. (US 20190287900 A1; hereinafter “Chang’900).
In re claim 15, Chang’900 discloses in figs. 1-7, an integrated circuit, comprising:
a first transistor 250b coupled to a first data line BL0 (¶28);
a second transistor 250a coupled to a second data line BL1 (¶28);
a first fuse element (right end portion of 202b; hereinafter “FE1”) coupled to the first transistor 250b and disposed at a first side of the first transistor 250b (¶28);
a second fuse element (left end portion of 202b; hereinafter “FE2”) coupled to the first transistor 250b and disposed at a first side of the second transistor 250b;
a third fuse element (right end portion of 202a; hereinafter “FE3”) coupled to the second transistor 250a and disposed at a first side of the first fuse element (FE1); and
a fourth fuse element (left end portion of 202a; hereinafter “FE4”) coupled to the second transistor 250a and disposed at a first side of the second fuse element (FE2),
wherein the first transistor 250b is partially overlapped with the first fuse element (FE1) in a layout view, and the second transistor 250a is partially overlapped with the second fuse element (FE2) in the layout view (fig. 6; ¶27; “an area 308 for the NMOS program transistor of a first eFuse cell connected to word line WL0 in the M0 layer; an area 310 for the NMOS program transistor of a second eFuse cell connected to word line WL1 in the M0 layer”. As shown in fig. 6, the Program NMOS transistors and the fuse (2R) are partially overlapped in a layout view).
In re claim 16, Chang’900 discloses in figs. 1-7, the integrated circuit of claim 15, wherein the first fuse element FE1 is between the first transistor 250b and the third fuse element FE3.
In re claim 18, Chang’900 discloses in figs. 1-7, the integrated circuit of claim 15, wherein the first fuse element FE1 is disposed at a second side (e.g., a side towards the page, in fig. 7) of the third fuse element FE3.
In re claim 19, Chang’900 discloses in figs. 1-7, the integrated circuit of claim 15, wherein the second fuse element FE2 is disposed at a second side (e.g., a side towards the page, in fig. 7) of the fourth fuse element FE4.
In re claim 20, Chang’900 discloses in figs. 1-7, the integrated circuit of claim 15, wherein the second transistor 250a is arranged next to the first transistor 250b in a layout view (based on figs. 6-7, the first transistor 250b is arranged next to the second transistor 250a in the lower metal level).
Claim(s) 15, 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang et al. (US 20190287900 A1; hereinafter “Chang’900), in an alternative interpretation.
In re claim 15, Chang’900 discloses in figs. 1-7, an integrated circuit, comprising:
a first transistor 250b coupled to a first data line BL0 (¶28);
a second transistor 250a coupled to a second data line BL1 (¶28);
a first fuse element (right end portion of 202a; hereinafter “FE1”) coupled to the first transistor 250b and disposed at a first side of the first transistor 250b (¶28);
a second fuse element (left end portion of 202a; hereinafter “FE2”) coupled to the first transistor 250b and disposed at a first side of the second transistor 250b;
a third fuse element (right end portion of 202b; hereinafter “FE3”) coupled to the second transistor 250a and disposed at a first side of the first fuse element (FE1); and
a fourth fuse element (left end portion of 202b; hereinafter “FE4”) coupled to the second transistor 250a and disposed at a first side of the second fuse element (FE2),
wherein the first transistor 250b is partially overlapped with the first fuse element (FE1) in a layout view, and the second transistor 250a is partially overlapped with the second fuse element (FE2) in the layout view (fig. 6; ¶27; “an area 308 for the NMOS program transistor of a first eFuse cell connected to word line WL0 in the M0 layer; an area 310 for the NMOS program transistor of a second eFuse cell connected to word line WL1 in the M0 layer”. As shown in fig. 6, the Program NMOS transistors and the fuse (2R) are partially overlapped in a layout view).
In re claim 17, Wang’900 discloses in figs. 1-7, the integrated circuit of claim 15, wherein the second fuse element (left end portion of 202a) is between the second transistor 250a and the fourth fuse element (left end portion of 202b).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 7, 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 20170345827 A1; hereinafter “Chang”).
In re claim 1, Chang discloses in figs. 2-3, 4B, an integrated circuit, comprising:
a transistor 202 formed in a first conductive layer (transistor 202 formed in the FEOL comprising a word line, which is a conductive layer; ¶19, 24. Furthermore, Chang discloses the first metal layer (M2), the second metal layer (M0) and the FEOL structure are each on different layers of the integrated circuit; ¶20. A first conductive layer will be referred to as “COND1” hereinafter);
a first fuse element 204 formed in a second conductive layer M2 and coupled between the transistor and a first data line VDDQI (bit0) (¶27); and
a second fuse element 206 formed in the second conductive layer M2 and coupled between the transistor 202 and a second data line VDDQI (bit2) (¶27),
wherein the first fuse element 204 and the second fuse element 206 are disposed at a same side of the transistor 202.
Furthermore, Chang discloses in fig. 4B, wherein the transistor 202 is partially overlapped with the first fuse element 204 in a cross-sectional view. One of ordinary skill in the art would have recognized the when the transistor 202 is partially overlapped with the first fuse element 204 in a cross-sectional view, then at least a portion of the transistor 202 is partially overlapped with the first fuse element 204 in a layout view as well. Therefore, the claimed feature “wherein the transistor is partially overlapped with the first fuse element in a layout view” is obvious to one of ordinary skilled in the art before the effective filing date of the claimed invention in view of Chang’s teachings shown in fig. 4B.
In re claim 2, Chang discloses in figs. 2-3, 4B, the integrated circuit of claim 1,
wherein the second conductive layer M0 is disposed above the first conductive layer COND1, and
the first fuse element 204 and the second fuse element 206 are disposed above the first conductive layer COND1.
In re claim 3, Chang discloses in figs. 2-3, 4B, the integrated circuit of claim 1, further comprising:
a conductive segment 323/325 formed in a third conductive layer M1 disposed between the first conductive layer COND1 and the second conductive layer M2 (¶27),
wherein the conductive segment 323/325, part of the first fuse element 204 and part of the transistor 202 are overlapped in a layout view (fig. 3), and
the first fuse element 204 is coupled through the conductive segment 323/325 to the transistor 202.
In re claim 7, Chang discloses in figs. 2-3, 4B, an integrated circuit, comprising:
a plurality of electrical fuse cells comprising:
a first conductive segment 323/325 (¶27);
a first transistor 202 formed in a first conductive layer (transistor 202 formed in the FEOL comprising a word line, which is a conductive layer; ¶19, 24. Furthermore, Chang discloses the first metal layer (M2), the second metal layer (M0) and the FEOL structure are each on different layers of the integrated circuit; ¶20. A first conductive layer will be referred to as “COND1” hereinafter); and
a pair of first fuse elements 204, 206 formed in a second conductive layer M2 disposed above the first conductive layer COND1 and coupled to a pair of data lines bit0, bit1 (¶27),
wherein the pair of first fuse elements 204, 206 are coupled together and are coupled through the first conductive segment to the first transistor 202,
wherein the first conductive segment 323/325 and the pair of first fuse elements 204, 206 are disposed at a same side of the first transistor 202.
Furthermore, Chang discloses in fig. 4B, wherein the transistor 202 is partially overlapped with the first fuse element 204 in a cross-sectional view. One of ordinary skill in the art would have recognized the when the transistor 202 is partially overlapped with the first fuse element 204 in a cross-sectional view, then at least a portion of the transistor 202 is partially overlapped with the first fuse element 204 in a layout view as well. Therefore, the claimed feature “wherein the transistor is partially overlapped with the first fuse element in a layout view” is obvious to one of ordinary skilled in the art before the effective filing date of the claimed invention in view of Chang’s teachings shown in fig. 4B.
In re claim 9, Chang discloses in figs. 2-3, 4B, the integrated circuit of claim 7, further comprising:
a third conductive layer M1, M0 disposed between the first conductive layer COND1 and the second conductive layer M2,
wherein the first conductive segment 323/325 is formed in the third conductive layer M1, M0 and is partially overlapped with first transistor 202 and one of the pair of first fuse elements 204, 206 in a layout view (fig. 3).
In re claim 10, Chang discloses in figs. 2-3, 4B, the integrated circuit of claim 7, wherein one of the pair of first fuse elements 204 comprises:
a fuse line 308 (¶24);
a first pair of fuse segments 314, 316 disposed on opposite sides of a first end (e.g., right end) of the fuse line 308 (¶24); and
a second pair of fuse segments 310, 312 disposed on opposite sides of a second end (e.g., left end) of the fuse line 308 (¶24),
wherein the first end and the second end are opposite from each other,
wherein one of the first pair of fuse segments 314 is overlapped with the first conductive segment 322 in a layout view (fig. 3), and
the second pair of fuse segments 310, 312 and part of the fuse line 308 are overlapped (as shown in fig. 3, the second pair of fuse segments 310, 312 and part of the fuse line 308 are overlapped along a vertical direction).
Claim(s) 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang as applied to claim 1 above, and further in view of Hall et al. (US 20180025982 A1; hereinafter “Hall”).
In re claim 4, Chang discloses in figs. 2-3, 4B, the integrated circuit of claim 1,
wherein the first fuse element 204 comprises:
a fuse line 308 (¶24); and
a pair of fuse segments 314, 316 disposed on opposite sides of the fuse line 308 (¶24).
Chang does not expressly disclose wherein one of the pair of fuse segments is coupled through a fuse conductive segment formed in the second conductive layer to the second fuse element.
In the same field of endeavor, Hall discloses in figs. 7-8, an integrated circuit, wherein one of a pair of fuse segments 132a is coupled through a fuse conductive segment 134a formed in a second conductive layer to a second fuse element 132b (¶38, 58).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Hall into the integrated circuit of Chang in order to establish a low resistance conductive path between adjacent fuses and the fuse transistor and efficiently program vertical OTP fuse, or read the resistance value of the fuse (¶30 of Hall).
In re claim 5, Chang discloses in figs. 2-3, 4B, the integrated circuit of claim 1,
wherein the first fuse element 204 comprises:
a first fuse line 308 (¶24); and a pair of first fuse segments 314, 316 disposed on opposite sides of an end of the first fuse line 308 (¶24),
wherein the second fuse element 206 comprises:
a second fuse line 308 (¶24); and
a pair of second fuse segments 314, 316 disposed on opposite sides of an end of the second fuse line 308.
Chang does not expressly disclose wherein one of the pair of first fuse segments is coupled through a fuse conductive segment formed in the second conductive layer to one of the pair of second fuse segments.
In the same field of endeavor, Hall discloses in figs. 7-8, an integrated circuit, wherein one of the pair of first fuse segments 132a is coupled through a fuse conductive segment 134a formed in a second conductive layer to one of the pair of second fuse segments 132b (¶38, 58).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Hall into the integrated circuit of Chang in order to establish a low resistance conductive path between adjacent fuses and the fuse transistor and efficiently program vertical OTP fuse, or read the resistance value of the fuse (¶30 of Hall).
In re claim 6, Chang, as modified by Hall, discloses the integrated circuit of claim 5 outlined above.
Chang further discloses in figs. 2-3, 4B, the integrated circuit of claim 5,
wherein one of the pair of first fuse segments, which is coupled to one of the pair of second fuse segments, is further coupled to the transistor through a conductive segment M1 formed in a third conductive layer M1 disposed between the first conductive layer COND1 and the second conductive layer M2.
Allowable Subject Matter
Claims 8, 11-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 8, Closest prior art of record, alone or in combination, does not expressly disclose all the limitations of claim 8 including a first program line formed in a third conductive layer disposed between the first conductive layer and the second conductive layer, wherein both of the first program line and the second program line are disposed above or below all of the first transistor, the second transistor and the pair of first fuse elements in a layout view, in combination with all limitations cited in claim 7.
Regarding claim 11, Closest prior art of record, alone or in combination, does not expressly disclose all the limitations of claim 11 including wherein one of the pair of first fuse segments is coupled through a fuse conductive segment formed in the second conductive layer to one of the pair of second fuse segments, and is overlapped with the first conductive segment in a layout view, in combination with all limitations cited in claim 7.
Regarding claim 12, Closest prior art of record, alone or in combination, does not expressly disclose all the limitations of claim 12 including relative positions of the first program line and the second program line relative to the electrical fuse cells in a layout view, a pair of second fuse elements formed in the second conductive layer and coupled together by a fuse conductive segment, wherein the pair of first fuse elements are disposed between the pair of second fuse elements and the second transistor in a layout view, in combination with all limitations cited in claim 7.
Dependent claims 13-14 are indicated allowable based on their dependency on claim 12.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NILUFA RAHIM/Primary Examiner, Art Unit 2893
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