DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1 and 19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-6 and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Ong et al. (US 20230209798 A1; hereinafter Ong) in view of Cheng et al. (US 20180212024 A1; hereinafter Cheng).
Regarding claim 1, FIGS. 3-4C & 8 of Ong teach a method of fabricating a semiconductor device, comprising: providing a plurality of fins (130, 125) extending from a substrate (301), wherein each fin of the plurality of fins (130, 125) includes a plurality of semiconductor channel layers (405, 260A-N ¶ [0072]); and performing an ion implantation process (815) into a first fin of the plurality of fins (130) to introduce a dopant species (“impurities”) into a topmost semiconductor channel layer of the plurality of semiconductor channel layers of the first fin (405/260N of 130 ¶ [0074]); wherein the ion implantation process (815) deactivates the topmost semiconductor channel layer of the plurality of semiconductor channel layers of the first fin (405/260N of 130 ¶ [0074]).
Ong does not teach performing the ion implantation process after etching-back a gate structure disposed over a channel region of a first fin of the plurality of fins.
FIGS. 3-9B of Cheng teach a method of fabricating a semiconductor device (e.g. FIGS. 3-9B), comprising: providing a plurality of fins (330, 331) extending from a substrate (301, 302), wherein each fin of the plurality of fins (330, 331) includes a plurality of semiconductor channel layers (311); and after etching-back a gate structure (e.g. replacement gate material, FIG. 6A ¶ [0016],[0044]) disposed over a channel region of a first fin of the plurality of fins (e.g. 311 of 330), performing an oxidation process (e.g. gas cluster ion beam process 710 ¶ [0056], see FIG. 7A) on a first fin of the plurality of fins (330) to oxidize a topmost semiconductor channel layer of the plurality of semiconductor channel layers of the first fin (topmost 311 of 330); wherein the oxidation process deactivates the topmost semiconductor channel layer of the plurality of semiconductor channel layers of the first fin (topmost 311 of 330 ¶ [0054]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of fabricating the semiconductor device taught by Ong with the method of exposing and deactivating the topmost channel taught by Cheng for the purpose of performing selective deactivation of channel layers (e.g. due to the presence of semiconducting material 310 beneath 720 ¶ [0061]).
Regarding claim 2, Ong as modified teaches the method of claim 1, and Ong further teaches wherein the dopant species (“impurities”) increases a first threshold voltage (Vt) of the topmost semiconductor channel layer (405 ¶ [0058]).
Regarding claim 3, Ong teaches the method of claim 2, and Ong further teaches wherein the first Vt of the topmost semiconductor channel layer (405) is greater than a second Vt of other semiconductor channel layers of the plurality of semiconductor channel layers (260A-N ¶ [0058]).
Regarding claim 4, Ong as modified teaches the method of claim 2, and Ong further teaches wherein the first fin (130) is used to form an N-type transistor (NMOS device), and wherein the dopant species includes a P-type dopant species (¶ [0059]).
Regarding claim 5, Ong as modified teaches the method of claim 2, and Ong further teaches wherein the first fin (130) is used to form a P-type transistor (p-type device), and wherein the dopant species includes an N-type dopant species (¶ [0059]).
Regarding claim 6, Ong as modified teaches the method of claim 1, and Ong further teaches wherein the deactivated topmost semiconductor channel layer (405) does not conduct current under normal operating conditions of the semiconductor device (¶ [0058]).
Regarding claim 8, Ong as modified teaches the method of claim 1, and FIGS. 4A & 4C of Ong further teach wherein a second fin of the plurality of fins (125) has N semiconductor channel layers (260A-N ¶ [0043]), and wherein the first fin (130) effectively has N-1 semiconductor channel layers (260A-N-1 ¶ [0061]).
Regarding claim 9, Ong as modified teaches the method of claim 1, and FIG. 8 of Ong further teaches further comprising: prior to performing the ion implantation process (815), forming a patterned mask layer (“mask material”) that exposes the first fin (130) while other fins of the plurality of fins (e.g. 125) remain protected by the patterned mask layer (“mask material” ¶ [0073]-[0074]); and performing the ion implantation process (815 ¶ [0074]).
Regarding claim 10, Ong as modified teaches the method of claim 1, further comprising: after performing the ion implantation process (815), performing a semiconductor channel release process (835), wherein the semiconductor channel release process (835) selectively removes silicon germanium (SiGe) layers (sacrificial layers in 130, 125 ¶ [0072], [0078]) that interpose adjacent semiconductor channel layers (405, 260A-N) within each of the plurality of fins (130, 125) to form gaps between the adjacent semiconductor channel layers (405, 260A-N) within each of the plurality of fins (130, 125 ¶ [0078]).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Ong in view of Chao et al. (US 20180047835 A1; hereinafter Chao).
Regarding claim 12, Ong teaches the method of claim 1.
Ong does not teach wherein the ion implantation process includes bombardment of germanium (Ge) or nitrogen (N) to physically destroy the topmost semiconductor channel layer.
FIGS. 2-5 of Chao teach a method of removing exposed semiconductor layers (exposed regions of 106, 108 in FIG. 2) comprising: performing a germanium implantation process on the exposed semiconductor layers (106, 108 ¶ [0043]) and removing the exposed semiconductor layers (106, 108) using an isotropic etching process (e.g. RIE ¶ [0049]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught by Ong with the germanium implantation and removal process taught by Chao for the purpose of increasing etch selectivity (¶ [0027]).
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ong in view of Leobandung (US 20150069328 A1; hereinafter Leobandung).
Regarding claim 19, FIGS. 3-4C of Ong teach a semiconductor device, comprising: a first fin (130) extending from a substrate (301) and including a first transistor (130 ¶ [0035],[0048]), wherein the first fin (130) includes a first gate structure (first instance of 285, 495 ¶ [0056]) and a first source/drain feature (first instance of 275 ¶ [0037]) adjacent to the first gate structure (first instance of 285, 495, see FIG. 3); and a second fin (125) extending from the substrate (301) and including a second transistor (125 ¶ [0035],[0048]), wherein the second fin (125) includes a second gate structure (second instance of 285, 495 ¶ [0056]) and a second source/drain feature (second instance of 275 ¶ [0037]) adjacent to the second gate structure (second instance of 285, 495, see FIG. 3); wherein the first fin (130) has a first number of semiconductor channel layers (405, first instances of 260A-260N-1 in 130) in lateral contact with the first source/drain feature (first instance of 275 ¶ [0057]), wherein the second fin (125) has a second number of semiconductor channel layers (second instances of 260A-260N in 125) in lateral contact with the second source/drain feature (second instance of 275 ¶ [0044]), wherein a topmost channel layer of the semiconductor channel layers of the first fin (405, first instances of 260A-260N-1 in 130) is electrically inert (¶ [0057],[0061]).
Ong does not teach wherein two topmost channel layers of the semiconductor channel layers of the second fin are electrically inert.
FIGS. 7 & 41-45 of Leobandung teach a semiconductor device (100), comprising: a first fin (102e) extending from a substrate (104 ¶ [0077]); and a second fin (102d) extending from the substrate (104 ¶ [0077]); wherein the first fin (102e) has a first number of semiconductor channel layers (e.g. two channel layers 108, 112), wherein the second fin (102d) has a second number of semiconductor channel layers (e.g. one channel layer), wherein a topmost channel layer of the semiconductor channel layers of the first fin (120 of region 116 including 102e) is removed (¶ [0078]), and wherein two topmost channel layers of the semiconductor channel layers of the second fin (112, 120 of region 118 including 102d) are removed (¶ [0078]).
Thus, Ong in view of Leobandung teaches wherein the topmost channel layer of the semiconductor channel layers of the first fin (405) is electrically inert, and wherein two topmost channel layers of the semiconductor channel layers of the second fin (260N, 260N-1 in 125) are electrically inert.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught by Ong with the number of active channels present in adjacent fins taught by Leobandung for the purpose of increasing design flexibility (¶ [0061],[0102]).
Regarding claim 20, Ong as modified teaches the semiconductor device of claim 19, and Ong further teaches wherein the topmost channel layer of the first fin (405) and the two topmost channel layers of the second fin (260N, 260N-1 of 125) that are electrically inert have a first threshold voltage (Vt) that is greater than a second Vt of other semiconductor channel layers (260A-260N-1 of 130 and 26A-260N-2 of 125) of respective ones of the first fin (130) and the second fin (125 ¶ [0058] “… inactive channel region 405 in an “off” state under all gate bias voltages that pass-gate transistor 130 may experience during SRAM bit-cell operation.”).
Allowable Subject Matter
Claims 7 and 11 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 7 recites the method of claim 1, wherein the ion implantation process forms an ion-implanted portion within the topmost semiconductor channel layer, and wherein the ion-implanted portion includes less than an entire thickness of the topmost semiconductor channel layer.
Ong teaches the method of claim 1.
However, the prior art fails to teach or reasonably suggest “wherein the ion implantation process forms an ion-implanted portion within the topmost semiconductor channel layer, and wherein the ion-implanted portion includes less than an entire thickness of the topmost semiconductor channel layer” together with all the limitations of claims 1 and 7 as claimed.
Claim 11 recites the method of claim 10, further comprising: after performing the semiconductor channel release process, performing an anneal process, wherein the anneal process causes the dopant species to diffuse across an entire thickness of the topmost semiconductor channel layer.
Ong teaches the method of claim 10.
However, the prior art fails to teach or reasonably suggest “further comprising:
after performing the semiconductor channel release process, performing an anneal process, wherein the anneal process causes the dopant species to diffuse across an entire thickness of the topmost semiconductor channel layer” together with all the limitations of claims 1 and 10-11 as claimed.
Claims 13-18 are allowed.
The following is an examiner’s statement of reasons for allowance:
Claim 13 recites
FIGS. 3-4C & 8 of Ong teach a method, comprising: providing a first fin (130) including a first plurality of channel layers (first instances of 260A-260N in 130) interposed by a first plurality of silicon germanium (SiGe) layers (sacrificial layers in 130 ¶ [0072]) and a second fin (125) adjacent to the first fin (130), the second fin (125) including a second plurality of channel layers (second instances of 260A-260N in 125) interposed by a second plurality of SiGe layers (sacrificial layers in 125 ¶ [0072]); performing a first ion implantation process (815) into the first fin (130) to introduce an anti-type implant species (“impurities”) into a topmost channel layer of the first plurality of channel layers of the first fin (405/260N in 130 ¶ [0074]); and wherein the first ion implantation process (815) deactivates the topmost channel layer of the first plurality of channel layers (405/260N of 130 ¶ [0074]).
FIG. 7 of Leobandung teaches a semiconductor device comprising multiple fins (102a-102f) including different numbers of nanowire channels (108, 112, 120 ¶ [0077]).
Ong in view of Leobandung teaches performing a second ion implantation process (process identical to 815 performed on 125 of Ong) into the second fin (125) to introduce the anti-type implant species (“impurities”); and wherein the second ion implantation process (process identical to 815 performed on 125 of Ong) deactivates the two topmost channel layer of the second plurality of channel layers (second instances of 260A-260N in 125). Since Leobandung teaches a first fin comprising a removed topmost channel (e.g. 102e-f) and a second fin comprising two removed topmost channels (e.g. 102d-c).
However, the prior art fails to teach or reasonably suggest “performing a second ion implantation process into the second fin to introduce a second anti-type implant species into two topmost channel layers of the second plurality of channel layers of the second fin” together with all the limitations of claim 13 as claimed. Claims 14-18 are allowable insofar as they depend upon and require all the limitations of claim 13.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nora T Nix whose telephone number is (571)270-1972. The examiner can normally be reached Monday - Friday 9:00 am - 5:00 pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nora T. Nix/Assistant Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891