DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The present amendment, filed on or after 11/3/2025, has been entered. The Applicant has amended claims 1, 11, 16-17, and 20. Accordingly, claims 1-20 remain pending in the application.
Applicant’s amendments to the specification and the title have overcome each and every objection previously set forth in the Non-Final Office Action mailed on 7/2/2025.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims are 1, 4-5, and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Xie-101 (US 2023/0093101 A1) in view of Yeoh (US 2023/0260909 A1).
Regarding claim 1, Xie-101 teaches a method (fabrication of a semiconductor assembly, Figs. 2A-11A, [0037]), comprising:
forming a plurality of semiconductor sheets (nanosheet stack 305, Fig. 3A and Illustrative Fig. 1, which is an annotated and modified version of Fig. 5A, [0043]) on a front-side of a semiconductive layer (semiconductive layer, Illustrative Fig. 1, [0049]: the semiconductive layer is the top portion of the substrate 100 above the bottom surface 815 as defined in [0061] and Fig. 8A) that is on a front-side of a substrate (substrate 100, Illustrative Fig. 1, [0049]), the plurality of semiconductor sheets (nanosheet stack 305, Illustrative Fig. 1) being stacked along a first direction (first direction, Illustrative Fig. 1);
forming a gate strip (dummy gates 405-1, 405-2, 405-3; Illustrative Fig. 1 and Fig. 4A, [0047]; later, dummy gates 405-1, 405-2, 405-3 are replaced by gates 715-1, 715-2, 715-3 (Fig. 7A, [0055])) surrounding each of the semiconductor sheets (nanosheet stack 305, Illustrative Fig. 1 and Fig. 4A, [0047]; gates surround the nanosheets at the top and at the sides along the Y direction as shown in Fig. 1);
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forming a plurality of dielectric layers (sacrificial material 605-1 and 605-2, see illustrative Fig. 2, which is a modified version of Fig. 6A, [0052]: “… the sacrificial material 605-1, 605-2 comprises a dielectric material, …”) on the semiconductive layer (semiconductive layer, Illustrative Fig. 2) and at opposite sides of the gate strip (dummy gates 405-1, 405-2, 405-3; Illustrative Fig. 2),
forming a plurality of source/drain structures (source/drain regions 620-1, 620-2, Illustrative Fig. 2, [0051]) on the dielectric layers (sacrificial material 605-1, Illustrative Fig. 2) and on either side of each of the semiconductor sheets (nanosheet stack 305, Illustrative Fig. 2);
performing a planarization process (Fig. 8A, [0061]: the device in Fig. 8A is flipped upside down for back-side processing) on a back-side of the substrate (substrate 100, Fig. 8A) to expose the semiconductive layer (semiconductive layer as shown In Illustrative Fig. 2, Fig. 8A, [0061]: substrate 100 is thinned until the bottom surface 815);
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etching ([0063]) the semiconductive layer (remaining portion of the substrate 100 after planarization (thinning) process, Fig. 9A: this portion will be referred as semiconductive layer 100) from a back-side of the semiconductive layer (semiconductive layer 100, Fig. 9A, [0063]) to form a first opening exposing (opening 905, Fig. 9A, [0063]) a first one of the dielectric layers (sacrificial material 605-1, Fig. 9A), while a second one of the dielectric layers (sacrificial material 605-2, Fig. 9A (see Fig. 6A for the label of the sacrificial material 605-2)) remains covered by the semiconductive layer (semiconductive layer 100, Fig. 9A);
selectively removing ([0064]-[0065]) the first one of the dielectric layers (sacrificial material 605-1, Fig. 10A, [0065]) through the first opening (opening 905, Figs. 10A) to form a second opening (opening 1005, Fig. 10A, [0065]) exposing one of the source/drain structures (source/drain regions 620-1, Fig. 10A, [0065]);
forming a contact (electric contact 1105, see Illustrative Fig. 3, which is an annotated version of Fig. 11A, [0066]) having a back-side portion (back-side portion, Illustrative Fig. 3) in the first opening (space occupied by the back-side portion, Illustrative Fig. 3 (opening 905 in Fig. 10A)) and a front-side portion (front-side portion, Illustrative Fig. 3) in the second opening (space occupied by the front-side portion, Illustrative Fig. 3 (opening 1005 in Fig. 10A)); and
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forming a power supply voltage line (buried power rail 1125, Illustrative Fig. 3, [0067]) on a back-side of the contact (back-side portion, Illustrative Fig. 3).
Xie-101, however, does not teach that the method comprises
forming a dielectric gate offset from the gate strip; and
at least one dielectric layer of the plurality of dielectric layers being positioned between the dielectric gate and the plurality of semiconductor sheets, a bottommost surface of the at least one dielectric layer being above a bottommost surface of the dielectric gate in the first direction.
Yeoh, on the other hand, teaches a method for manufacturing a semiconductor device comprising gate-all-around transistors with a backside power rail contact (Figs. 2A-J and 4A-J, [0002]), wherein the method comprises
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forming a dielectric gate (diffusion break fill material 150, Figs. 4B-E, [0070]-[0074]) offset from the gate strip (see the gate strip and the diffusion break in Illustrative Fig. 4 which is an annotated version of Yeoh’s Fig. 4E, [0070]); and
at least one dielectric layer of the plurality of dielectric layers (bottom dielectric isolation (BDI) layer 120, Fig. 2I, [0050]) being positioned between the dielectric gate (dielectric gate, Illustrative Fig. 4) and the plurality of semiconductor sheets (semiconductor sheets in the gate strip area, Illustrative Fig. 4; BDI layer 120 in Illustrative Fig 4 is between the dielectric gate and the semiconductor sheets in the gate strip), a bottommost surface (bottommost surface of one dielectric layer, Illustrative Fig. 4) of the at least one dielectric layer (BDI layer 120, Illustrative Fig. 4) being above a bottommost surface of the dielectric gate (bottommost surface of the dielectric gate, Illustrative Fig. 4) in the first direction (first direction, Illustrative Fig. 4).
Yeoh further discloses that the inclusion of the dielectric gate in the semiconductor device manufactured by the method of Yeoh provides the benefit of preventing over-polishing of the substrate during forming the backside power rail ([0005]) by acting as an effective etch stop layer ([0029]), besides also providing also an isolation structure for electrical isolation between active regions in the device ([0031]). A person of ordinary skill in the art before the effective filing date of the claimed invention would realize that the semiconductor devices manufactured by the methods of Xie-101 and Yeoh, and the corresponding methods are analogous (both geared towards nanosheet transistor devices with backside power rail connections), and therefore would be motivated to include steps for forming a dielectric gate, as taught by Yeoh, in the method of Xie-101 to obtain the benefit of preventing over-polishing of the substrate during performing the planarization process, and also providing electrical isolation between the active regions on the device.
Thus, the combination of Xie-101 and Yeoh leads to a method comprising the steps of
forming a dielectric gate offset from the gate strip; and
at least one dielectric layer of the plurality of dielectric layers being positioned between the dielectric gate and the plurality of semiconductor sheets, a bottommost surface of the at least one dielectric layer being above a bottommost surface of the dielectric gate in the first direction.
Regarding claim 4, Xie-101 in view of Yeoh teaches the method of claim 1, wherein
Xie-101 further teaches that when viewed in a cross section taken along a direction in parallel with a lengthwise direction the gate strip (Y-direction in Fig. 1), the back-side portion of the contact has a same dimension as the front-side portion of the contact (Xie-101 does not provide a cross section view along the direction in parallel with a lengthwise direction the gate strip, and therefore does not explicitly disclose that the back-side portion of the contact has a same dimension as the front-side portion of the contact in that cross section. However, as also evidenced by Yu (US 2022\0069117 A1, Figs. 18A and 18B) or Xie-101 (US 2024/0079446 A1, Figs. 17B and 17C) which are analogous to Xie-101, both the back-side and front-side portions cover only the tops of the source/drain regions extending in the trench along the Y-direction, and therefore the back-side portion of the contact has the same dimension as the front-side portion of the contact when viewed in a cross section taken along a direction in parallel with a lengthwise direction the gate strip).
Regarding claim 5, Xie-101 in view of Yeoh teaches the method of claim 1, wherein
Xie-101 further teaches that when viewed in a cross section taken along a lengthwise direction of one of the semiconductor sheets (Illustrative Fig. 3 (an annotated version of Fig. 11A) provides a cross section taken along a lengthwise direction of one of the semiconductor sheets), the back-side portion of the contact (back-side portion, Illustrative Fig. 3) has a greater lateral dimension than the remained second one of the dielectric layers (source drain region 620-2, Illustrative Fig. 3, [0051]: back-side portion of the contact is wider than the two source/drain regions 620-1 and 620-2 which have equal widths).
Regarding claim 8, Xie-101 in view of Yeoh teaches the method of claim 1, wherein
Xie-101 further teaches that the method comprises:
before forming the contact (electric contact 1105, [0066]), conformally forming a dielectric layer on sidewalls of the first and second openings ([0066]: “… a dielectric spacer can be deposited before the metal fills.”).
Regarding claim 9, Xie-101 in view of Yeoh teaches the method of claim 1, wherein
Xie-101 also teaches that the method further comprises:
forming a back-side dielectric layer (interlayer dielectric (ILD) layer 1120, Illustrative Fig. 3, [0067]) between the semiconductive layer (semiconductive layer 100, Illustrative Fig. 3, [0066]) and the power supply voltage line (buried power rail 1125, Illustrative Fig. 3, [0067]).
Xie-101, however, does not teach that
the contact penetrates through the back-side dielectric layer.
Yeoh, on the other hand, teaches a method for manufacturing a semiconductor device comprising gate-all-around transistors (Figs. 2A-J and 4A-J, [0002]) with a backside power rail contact (metal 160, Fig. 4J, [0066]) for electrical connection to a backside power rail (backside metal line 162, Fig. 4J, [0067]) through a backside dielectric layer (dielectric material 130, Fig. 4J, [0080]). Yeoh teaches that
the contact (metal 160, Fig. 4J) penetrates through the back-side dielectric layer (dielectric material 130, Fig. 4J).
It would be obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the dielectric material 130 of Yeoh (Fig. 4J) is analogous to the interlayer dielectric layer 1110 of Xie-101 (Fig. 11A), and therefore, extending the contact trough the dielectric layer to contact the power supply voltage line directly would provide the benefits of reduced contact resistance between the contact and the power supply voltage line due to increased contact area, and simplified manufacturing process due to reduced number of steps involving etching and deposition processes. Therefore, a person of ordinary skill in the art would be motivated to modify the method of Xie-101 in view of Yeoh by extending the back-side of the contact through the dielectric layer to make a direct connection to the power supply voltage line, as taught by Yeoh, to obtain the benefits of improving the electrical connection between the contact and the power supply voltage line, and simplifying the manufacturing process.
Thus, the combination of Xie-101 and Yeoh meets the limitation that
the contact penetrates through the back-side dielectric layer.
Claims 2 is rejected under 35 U.S.C. 103 as being unpatentable over Xie-101 (US 2023/0093101 A1) in view of Yeoh (US 2022\0069117 A1) as applied to claims 1, 4-5, and 8-9 above, and further in view of Liao (US 2021/0336063 A1).
Regarding claim 2, Xie-101 in view of Yeoh teaches the method of claim 1, wherein
Xie-101further teaches that when viewed in a cross section taken along a lengthwise direction of one of the semiconductor sheets (cross-section shown in Fig. 11A), the contact (electric contact 1105, see Illustrative Fig. 5 which is an annotated version of Fig. 11A, [0066]) is a stepped sidewall
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structure (step on the sidewall, Illustrative Fig. 5) having a first sidewall (first sidewall, Illustrative Fig. 5), a second sidewall (second sidewall, Illustrative Fig. 5) connecting the first one of the source/drain structures (source/drain region 620-1, Illustrative Fig. 5) and laterally set back from the first sidewall (first sidewall, Illustrative Fig. 5: the second sidewall is narrower than the first sidewall), and a horizontal surface (horizontal surface, Illustrative Fig. 5) connecting the first sidewall (first sidewall, Illustrative Fig. 5) to the second sidewall (second sidewall, Illustrative Fig. 5).
Xie-101 and Yeoh do not teach that the first sidewall connecting the power supply voltage line.
Liao, on the other hand, teaches a method for manufacturing gate-all-around nanosheet FETs (nano-FET, Figs. 15-21, [0074]), which are analogous to the devices manufactured by Xie-101’s method, including a back-side contact (source/drain contacts 112C, Fig. 21, [0089]) for electrical connection to a power supply voltage line (power rail 144P, Fig. 21, [0094]). Liao teaches that the back-portion of the contact (source/drain contacts 112C) extends through the semiconductive layer (fins 54, Fig. 21, [0014]: “… the fins 54 and/or the substrate 50 may include a single material … “, therefore fins 54 are analogous to Xie-101’s semiconductive layer shown in Illustrative Fig. 3) and the dielectric layer (dielectric layer 128, Fig. 21, [0083]: dielectric layer 128 is analogous to Xie-101’s interlayer dielectric (ILD) layer 1110 shown in Illustrative Fig. 3), and the sidewall of the contact connects to the power supply line (power rail 144P, Fig. 21). It would be obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the back-side power supply line connection is a design choice, and extending the contact trough the dielectric layer to contact the power supply voltage line directly would provide the benefits of reduced contact resistance between the contact and the power supply voltage line (due to increased contact area), and a simplified manufacturing process (due to reduced number of steps involving etching and deposition). Therefore, a person of ordinary skill in the art would be motivated to modify the method of Xie-101 in view of Yeoh by extending the back-side of the contact through the dielectric layer to make a direct connection to the power supply voltage line, to obtain the benefits of improving the electrical connection between the contact and the power supply voltage line, and simplifying the manufacturing process.
Thus, the combination of Xie-101 and Liao meets the limitation that
the first sidewall connects to the power supply voltage line.
Claims 3 is rejected under 35 U.S.C. 103 as being unpatentable over Xie-101 (US 2023/0093101 A1) in views of Yeoh (US 2022/0069117 A1) and Liao (US 2021/0336063 A1) as applied to claim 2 above, and further in view of Yu (US 2022/0069117 A1).
Regarding claim 3, while Xie-101 in views of Yeoh and Liao teaches the method of claim 2,
Xie-101, Yeoh and Liao are silent about the length of the horizontal surface.
Yu, on the other hand, teaches a method of manufacturing a semiconductor device (workpiece 200, Fig. 18A-C, [0035]) analogous to the semiconductor device manufactured by the method of Xie-101 in view of Liao. Yu’s method also includes a contact (backside source contact 270, Fig. 18A, [0043]) comprising a first sidewall (sidewall of the second portion 270-2, Fig. 18a, [0045]), a second sidewall (sidewall of the first portion 270-1, Fig. 18A, [0045]), and a horizontal surface (connection between the sidewalls of the first portion 270-1 and the second portion 270-2, Fig. 18A) connecting the first sidewall (sidewall of the second portion 270-2, Fig. 18A) and second sidewalls (sidewall of the first portion 270-1, Fig. 18A), wherein
the horizontal surface (connection between the sidewalls of the first portion 270-1 and the second portion 270-2, Fig. 18A) has a length greater than about 2 nm ([0043]: “… a ratio of the second width W2 to the first width W1 is between about 1.1 and about 2.5. In these instances, the second width W2 may be between about 6 nm and about 20 nm and the first width W1 may be between about 5 nm and about 15 nm.” where W-1 is the width of the first portion and W2 is the width of second portion. These limitations result in a range of horizontal surface lengths from about 0.3nm to 6nm) when viewed in the cross section (cross section shown in Fig. 18A).
Therefore, the range of lengths provided by Yu overlaps with the range of lengths provided in the claimed invention, and a prima facie case of obviousness exists (see MPEP 2144.05(I)), as the range of lengths of the horizontal surface in Xie-101 in views of Yeoh and Liao can be optimized by routine experimentation, using the range provided by Yu to guide the selection of initial lengths, to achieve a desired manufacturing reliability and a device performance (see MPEP 2144.05(II)). Therefore, the range of values provided does not hold an inventive subject matter.
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Xie-101 (US 2023/0093101 A1) in view of Yeoh (US 2022/0069117 A1) as applied to claim 1, 4-5, and 8-9 above, and further in view of Yu (US 2022/0069117 A1).
Regarding claim 6, while Xie-101 in view of Yeoh teaches the method of claim 1,
Xie-101 and Yeoh do not teach that before forming the contact, forming a silicide layer on a back-side of the one of the source/drain structures.
Yu, on the other hand, teaches a method of manufacturing a semiconductor device (workpiece 200, Fig. 18A-C, [0035]) analogous to the semiconductor device manufactured by the method of Xie-101, comprising
before forming the contact (source plug 268, Figs. 14A-15A, [0041]), forming a silicide layer (source silicide feature 266, Figs. 15A, [0041]) on a side back-side (Z direction in Fig. 15A) of the one of the source/drain structures (source feature 242S, Fig. 15A, [0041]).
Including a silicide layer between a source/drain region and a metal contact is known to improve the contact resistance between the metal contact and the source/drain region as also evidence by Smith (US 2021/0098306 A1, [0010] and [0055]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to include additional steps in the method of Xie-101 in view of Yeoh to form a silicide layer, as taught by Yu, on a back-side of the one of the source/drain structures before forming the contact, which would provide the benefit of improving the contact resistance between the contacts and the one of the source/drain regions.
Regarding claim 7, Xie-101 in views of Yeoh and Yu teaches the method of claim 6, wherein
Xie-101 further teaches that silicide layer (not shown in figures) is further conformally formed on sidewalls of the first and second openings ([0066]: “The metallization material of the electric contact 1105 (e.g., a backside contact) includes a silicide liner …”.).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Xie-101 (US 2023/0093101 A1) in view of Yeoh (US 2022/0069117 A1) as applied to claim 1, 4-5, and 8-9 above, and further in views of Liao (US 2021/0336063 A1) and Jiang (US Patent No. 9502265 B1).
Regarding claim 10, while Xie-101 in view of Yeoh teaches the method of claim 1,
Xie-101 does not teach that the method further comprises
performing an implantation process on the semiconductive layer with a dopant, wherein the dopant has a same conductivity type as the source/drain structures.
Yeoh, on the other hand, teaches a method for manufacturing a semiconductor device comprising gate-all-around transistors (Figs. 2A-J and 4A-J, [0002]) which is analogous to the semiconductor device manufactured by the method of Xie-101 in view of Yeoh. Yeoh teaches that the method further comprises
performing an implantation process ([0035]: “ion implantation process”) on the semiconductive layer (substrate 102, Fig. 4J, [0034]) with a dopant ([0035]: “boron (B)”), wherein the dopant has a same conductivity type ([0052]: also “boron (B)” for source/drain structures, therefore p-type) as the source/drain structures (source/drain 121a, 121b region, [0052]).
Therefore, a person of ordinary skill in the art before effective filing date of the claimed invention who is aiming to form p-type transistors using the method of Xie-101 in view of Yeoh would be motivated to form a p-type substrate and p-type source/drain regions by using an ion implantation process, as taught by Yeoh, which would provide the benefit of reliably doping the substrate and the source/drain regions independently (Yeoh, [0052]).
Allowable Subject Matter
Claims 11-20 are allowed, where claim 11 and claim 17 are independent claims.
Regarding claim 11-16, the amended independent claim 11, now also disclosing the limitations “forming a dielectric gate offset from the plurality of nanostructures, the dielectric gate extending from above the plurality of nanostructures in the first direction to below an uppermost surface of the semiconductor strip in the first direction” and “the power supply voltage line having an uppermost surface contiguous with a bottommost surface of the dielectric gate”, overcame the 35 U.S.C. 102(a)(2) based on Xie-101 (US 2023/0093101 A1) made in the non-final office action. A further search did not lead to a prior art that can by itself or in combination with Xie render the invention disclosed in claim 11 anticipated or obvious.
Regarding the closest prior art, Xie-101 teaches a method, comprising:
forming a plurality of nanostructures (nanosheet stack 305, Fig. 3A and Illustrative Fig. 6, which is an annotated version of Fig. 5A, [0043]) arranged in a first direction (first direction, Illustrative Fig. 6) on a semiconductor strip (semiconductor strip, Illustrative Fig. 6, [0049]) upwardly (front-side direction, Illustrative Fig. 6) extending from a front-side of a substrate (substrate 100, Fig. 3A and Illustrative Fig. 6, [0049]);
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forming a plurality of leakage barriers (sacrificial material 605-1, 605-2, see Illustrative Fig. 7, which is an annotated version of Fig. 6A, [0052]) on the semiconductor strip (semiconductor strip, Illustrative Fig. 7 and Fig. 6A);
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growing a plurality of epitaxial patterns (source/drain regions 620-1, 620-2, Illustrative Fig. 7, [0051], S/D regions are epitaxial ([0066]) on opposite sides of the nanostructures (nanosheet stack 305, Illustrative Fig. 7) and on the leakage barriers (sacrificial material 605-1, 605-2, Illustrative Fig. 7);
forming a gate pattern (dummy gates 405-1, 405-2, 405-3; Fig. 4A, and Illustrative Fig. 7, [0047]; later, dummy gates 405-1, 405-2, 405-3 are replaced by gates 715-1, 715-2, 715-3 (Fig. 7A, [0055])) across the nanostructures (nanosheet stack 305, Figs. 3A, 4A, and Illustrative Fig. 7) and between the epitaxial patterns (source/drain regions 620-1, 620-2, Illustrative Fig. 7);
performing a planarization process (Fig. 8A, [0061]: the device in Fig. 8A is flipped upside down for back-side processing) on a back-side of the substrate (substrate 100, Fig. 8A) to expose the semiconductor strip (semiconductor strip as shown in Illustrative Fig. 7, Fig. 8A, [0061]: substrate 100 is thinned until the bottom surface 815);
etching ([0063]) the semiconductor strip (remaining portion of the substrate 100 after planarization (thinning) process, Fig. 9A: this portion will be referred as semiconductor strip 100) to expose one of the leakage barriers (sacrificial material 605-1, Fig. 10A);
removing ([0064]-[0065]) the one of the leakage barriers (sacrificial material 605-1, Fig. 10A) to expose one of the epitaxial patterns (source/drain regions 620-1, Fig. 10A, [0065]);
after removing the one of the leakage barriers (sacrificial material 605-1, Fig. 10A), forming ([0066]) a power conductive contact (electric contact 1105, see Illustrative Fig. 8, which is an annotated version of Fig. 11A, [0066]) extending through the semiconductor strip (semiconductor strip, Illustrative Fig. 8) and on the one of the epitaxial patterns (source/drain regions 620-1, Illustrative Fig. 8), the power conductive contact (electric contact 1105, Illustrative Fig. 8) being a stepped sidewall structure (step on the sidewall, Illustrative Fig. 8), and a back-side of the power conductive contact (back-side portion, Illustrative Fig. 8) having a greater lateral dimension than a front-side of the power conductive contact (front-side portion, Illustrative Fig. 8: back-side portion is wider than the front-side portion); and
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forming a power supply voltage line (buried power rail 1125, Illustrative Fig. 8, [0067]) on the back-side of the power conductive contact (back-side of the electric contact 1105, Illustrative Fig. 8).
Xie-101, however, does not teach that the method comprises
forming a dielectric gate offset from the plurality of nanostructures, the dielectric gate extending from above the plurality of nanostructures in the first direction to below an uppermost surface of the semiconductor strip in the first direction;
the power supply voltage line having an uppermost surface contiguous with a bottommost surface of the dielectric gate.
Yeoh, on the other hand, teaches a method for manufacturing a semiconductor device comprising gate-all-around transistors with a backside power rail contact (Figs. 2A-J and 4A-J, [0002]), wherein the method comprises
forming a dielectric gate (diffusion break fill material 150, Figs. 4B-E (see also the dielectric gate in Illustrative Fig. 9 which is an annotated version of Fig. 4E, [0070]-[0074]) offset from the plurality of nanostructures (superlattice structure 101 comprising a plurality of semiconductor material layers 104 and a corresponding plurality of horizontal channel layers 106, see nanostructures in Illustrative Fig. 9, which is an annotated version of Fig. 4E, [0038]), the dielectric gate (dielectric gate, Illustrative Fig. 9) extending from above the plurality of nanostructures (nanostructures, Illustrative Fig. 9) in the first direction (first direction, Illustrative Fig. 9) to below an uppermost surface of the semiconductor strip (uppermost surface of the semiconductor strip, Illustrative Fig. 8) in the first direction (first direction, Illustrative Fig. 9).
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Yeoh further discloses that the inclusion of the dielectric gate in the semiconductor device manufactured by the method of Yeoh provides the benefit of preventing over-polishing of the substrate during forming the backside power rail ([0005]) by acting as an effective etch stop layer ([0029]), besides also providing also an isolation structure for electrical isolation between active regions in the device ([0031]). A person of ordinary skill in the art before the effective filing date of the claimed invention would realize that the semiconductor devices manufactured by the methods of Xie-101 and Yeoh, and the corresponding methods are analogous, and therefore, would be motivated to include steps for forming a dielectric gate, as taught by Yeoh, in the method of Xie-101 to obtain the benefit of preventing over-polishing of the substrate during performing the planarization process, and also providing electrical isolation between the active regions on the device.
Because the one of the reasons of including a dielectric gate is to control the polishing depth during the step of planarization, a person of ordinary skill in the art before the effective date of the claimed invention form the dielectric gate in the method of Xie-101 in view of Yeoh such that the bottom surface of the dielectric gate is aligned horizontally with the thinning level of the substrate (bottom surface 815, Fig. 10A) which corresponds to the uppermost surface of the power supply voltage (Fig. 11A). Therefore, the combination of Xie-101 and Yeoh meets the limitations that the method comprises
forming a dielectric gate offset from the plurality of nanostructures, the dielectric gate extending from above the plurality of nanostructures in the first direction to below an uppermost surface of the semiconductor strip in the first direction.
However, the combination of Xie-101 and Yeoh, fails to teach the limitation that
the power supply voltage line having an uppermost surface contiguous with a bottommost surface of the dielectric gate.
Therefore, claim 11 is allowable, as the references of the prior art of record and considered pertinent to the applicant's disclosure and examiner's knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding the limitation that "the power supply voltage line having an uppermost surface contiguous with a bottommost surface of the dielectric gate.”, when this limitation is accompanied by the remaining structural and methodological limitations of the claim 11.
Consequently, claims 12-16 are also allowed because they inherit allowable subject matter from allowed claim 11.
Regarding claim 17-20, the amended independent claim 17, now also disclosing the limitations “forming a dielectric gate offset from the plurality of nanostructures, the dielectric gate extending from above the plurality of nanostructures in the first direction to below an uppermost surface of the semiconductor strip in the first direction” and “the back-side power supply voltage line having an upper surface contiguous with a bottommost surface of the contact and contiguous with a bottommost surface of the dielectric gate”, overcame the 35 U.S.C. 102(a)(2) based on Xie-101 (US 2023/0093101 A1) made in the non-final office action. A further search did not lead to a prior art that can by itself or in combination with Xie render the invention disclosed in claim 17 anticipated or obvious.
Regarding the relevant prior art, the combination of Xie-101 and Yeoh is still the closest prior art identified as in the case of claim 11 above. Because claim 11 represents the method for manufacturing the semiconductor device of claim 17, the structural limitations of these claim 11 and 17 remain identical, and using similar arguments made for claim 11 above, Xie-101 and Yeoh teach all the limitations of claim 17, except that “the back-side power supply voltage line having an upper surface … contiguous with a bottommost surface of the dielectric gate”.
Therefore, claim 17 is allowed, as the references of the prior art of record considered pertinent to the applicant’s disclosure and examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding the limitation “the back-side power supply voltage line having an upper surface … contiguous with a bottommost surface of the dielectric gate”, when this limitation is accompanied by the remaining structural limitations of the claim 17.
Consequently, claims 18-20 are also allowed because they inherit allowable subject matter from allowed claim 17.
Response to Arguments
It has been acknowledged that the applicant amended claims 1, 11, 16-17, and 20 per response dated on 11/3/2025. Applicant's arguments with respect to claims have been fully considered.
The Examiner agrees with the Applicant on that the amendments to independent claims 1, 11, and 17 have overcame claim rejections made previously based on the prior art Xie-101 (US 2023/0093101 A1) on these claims. Further search did not lead to a prior art that renders independent claims 11 and 17 anticipated or obvious. Therefore, as detailed above in the current office action, claims 11-20 are allowed.
However, amended independent claim 1 is now rejected under new grounds based on a new prior-art, Yeoh (US 2023/0260909 A1), combined with Xie-101 in the current office action. Rejections are also made on all claims that are dependent on claim 1 based on this new prior-art or its combination with prior-art from the non-final office action.
For the purpose of compact prosecution, the Examiner notes, however, that incorporation of structural limitations related to the dielectric gate and its relation to other structures in claim 1 might render independent claim 1 inventive and non-obvious.
The Examiner is available for an interview at Applicant’s convenience if the Applicant would like to discuss the application.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812