DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/23/2026 has been entered.
Priority
Acknowledgment is made of applicant’s claim for priority to U.S. Prov. App. Ser. No. 63/377,685, filed September 29, 2022.
Response to Amendment
Applicant's amendments on 3/23/2026 have been reviewed and entered. Claims 1, 4-7, 9, 11, 18, and 20 have been amended by the applicant. Claims 1-20 is present for examination.
Applicant’s amendments to claims 1, 4-7, 9, and 11 have overcome the 35 U.S.C. 112(b) rejections made on claims 1-11 in the Final Office Action mailed on 1/21/2026.
Allowable Subject Matter
Claim 1-17 are allowed, where claim 1 and claim 12 are the independent claims.
Regarding claims 1-11, independent claim 1 is allowed, because the references of the prior art of record and considered pertinent to the applicant's disclosure and examiner's knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding the limitation that "conformally depositing a dielectric layer to completely fill the first gap between the adjacent semiconductor channel layers, wherein the conformally deposited dielectric layer defines V-shaped recesses having a first depth.”, when this limitation is accompanied by the remaining structural and methodological limitations of the claim 1.
Regarding the relevant prior art for the invention disclosed in claim 1, the combination of Wang (US 2021/0376119 A1) of the non-final office action and Subramanian (US 2023/0187528 A1) are identified as the closest prior art. Specifically, Wang teaches a method of fabricating a semiconductor device (semiconductor FET device, Figs. 3-25, [0007]-[0009]: embodiment with V-shaped cavities 24 (Figs. 2I and 14, [0048])), comprising:
providing a fin (fin structure 11 and overlying first semiconductor layers 20 and second semiconductor layers 25, Figs. 9-11, [0045]) including an epitaxial layer stack (stack of first semiconductor layers 20 and second semiconductor layers 25, Fig. 11A, [0032]: “The first semiconductor layers 20 and the second semiconductor layers 25 are epitaxially formed …”) having a plurality of semiconductor channel layers (second semiconductor layers 25, Fig. 11A) interposed by a plurality of dummy layers (first semiconductor layers 20, Fig. 11A);
removing the plurality of dummy layers (first semiconductor layer 20, Fig. 14A, [0046]-[0048]: lateral edges of semiconductor layers 20 are removed in a V-shape) to form a first gap (cavity 24, Fig. 14A, [0048]) between adjacent semiconductor channel layers of the plurality of semiconductor channel layers (second semiconductor layers 25, Fig. 14A);
conformally depositing a dielectric layer (first insulating layer 33, Figs. 15A, [0050]; [0066]: the first insulating layer is silicon oxynitride which is a dielectric material; while the edges of the first semiconductor layer 20 is rectangular in Fig. 15A, the method applies to the embodiment with V-shaped cavities as shown in Fig. 14A ([0049])) to fill the first gap (cavity 24, Figs. 14A and 15A) between the adjacent semiconductor channel layers (second semiconductor layer 25), wherein the conformally deposited dielectric layer (first insulating layer 33, Figs. 15A) defines V-shaped recesses (in the case of the embodiment with V-shaped cavities 24, the conformally deposited dielectric would form a V-shaped recess in Fig. 15A) having a first depth (the depth of the recess 22 in Fig. 15A when the recess is V-shaped);
etching ([0051]) exposed lateral surfaces of the dielectric layer (first insulating layer 33, Fig. 16A, [0051]; the embodiment considered leads to a V-shaped profile as shown in Fig. 2I ([0026])) to form an etched-back dielectric layer (first insulating layer 33, Fig. 18A with the shape shown in Fig. 2I without the second insulating layer 35, [0051]) that increases the first depth of the V-shaped recesses (cavity 22, [0052]: cavity 24 in Fig. 14A becomes a smaller cavity 22) to a second depth greater than the first depth (the etch process is expected to etch the dielectric layer in the V-shaped recesses, but to a smaller extend, thereby increasing the first depth to a second depth); and
forming a V-shaped inner spacer (second insulating layer 35, Fig. 2I, [0052]) within the V-shaped recesses (cavity 22, Fig. 18A for a V-shaped cavity) having a second depth.
Wang, however, does not teach
completely removing the plurality of dummy layers to form a first gap between adjacent semiconductor channel layers of the plurality of semiconductor channel layers; and
conformally depositing a dielectric layer to completely fill the first gap between the adjacent semiconductor channel layers, wherein the conformally deposited dielectric layer defines substantially V-shaped recesses having a first depth.
Subramanian, on the other hand, teaches a method for forming a precursor semiconductor structure (semiconductor device structure 200, Figs. 10-14, [0082]) for manufacturing gate-all-around type field-effect transistor devices (Fig. 15, [0092]), wherein the precursor semiconductor device with an initial fin structure (fin structure 110, Figs. 11a-c, [0092]) including an epitaxial layer stack (channel layers 114 and sacrificial layers 112, Figs. 11a-c, [0067]) having a plurality of semiconductor channel layers (channel layers 114, Fig. 11a-c) interposed by a plurality of dummy layers (sacrificial layers 112, Fig. 11a-c). Subramanian’s method comprises completely removing the plurality of dummy layers (sacrificial layers 112, Figs. 11-14, [0085]) to form a first gap (cavity 116, Fig. 12, [0077]) between adjacent semiconductor channel layers (channel layers 114, Figs. 11 and 12) of the plurality of semiconductor channel layers (channel layers 114, Figs. 11 and 12).
Subramanian further discloses that replacing the semiconductor sacrificial layers with dielectric layers may lead to a more thermally stable structure ([0015]) and facilitate selective processing of the insulating layers and semiconductor channel layers ([0014]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to incorporate Subramanian’s teachings in the method of Wang by including steps for completely replacing the plurality of dummy layers with a conformally deposited dielectric layer for obtaining a more thermally stable structure and facilitating an improved selective processing of the layers in the subsequent steps of the method.
However, the combination of Wang and Subramanian fail to teach that “conformally depositing a dielectric layer to completely fill the first gap between the adjacent semiconductor channel layers, wherein the conformally deposited dielectric layer defines V-shaped recesses having a first depth”. A further search did not lead to a prior art that teaches, by itself or in combination with others, completely filling the gaps between adjacent semiconductor channel layers by a conformally deposited a dielectric layer, wherein the conformally deposited dielectric layer defines V-shaped recesses having a first depth. Therefore, Wang and Subramanian remain the closest prior art for the invention disclosed in claim 1.
Accordingly, claim 1 and claims 2-11, which depend directly or indirectly are allowed
Regarding claims 12-17, independent claim 12 is allowed, because, as in the case of claim 1, the references of the prior art of record and considered pertinent to the applicant’s disclosure and examiner’s knowledge does not teach or render obvious, as least to the skilled artisan, the instant invention regarding the limitation “replacing the epitaxial layers of the second composition with a conformally deposited dielectric layer, wherein the conformally deposited dielectric layer defines recesses including a first V-shaped sidewall profile having a first depth” as recited in claim 12 in combination with the remaining structural and methological limitations of the claim. As also detailed in the final office action and above for claim 1 (claim 12 discloses a method for making the same device with similar methodological steps as the one disclosed in claim 1), the combination Wang and Subramanian is identified as the closest prior art, but fails to disclose the limitation above.
Accordingly, claims 13-17 are also allowed, because these claims inherit the allowable subject matter from claim 12.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 18-20 is rejected under 35 U.S.C. 103 as being unpatentable over Chiang (US 2020/0381545 A1) in view of Wang (US 2021/0376119 A1).
Regarding claim 18, Chiang teaches a semiconductor device (semiconductor device 200, Figs. 13A-B), comprising:
a fin (see the fin as shown in Illustrative Fig. 1, which is an annotated version of Figs. 13B and 21) extending from a substrate (substrate 202 (shown in Fig. 2B), labeled as substrate in Illustrative Fig. 1, [0025]), wherein the fin (fin, Illustrative Fig. 1) includes a plurality of semiconductor channel layers (channel members 208, Illustrative Fig. 1, [0044]);
inner spacers (first inner spacer layer 240, Illustrative Fig. 1, [0046]) disposed between adjacent semiconductor channel layers (channel members 208, Illustrative Fig. 1) of the plurality of semiconductor channel layers (channel members 208, Illustrative Fig. 1) and on either side of a channel region (left and right sides of channel members 208, Illustrative Fig. 1), wherein the inner spacers (first inner spacer layer 240, Illustrative Fig. 1) include a first lateral end (see first lateral end as labeled in Illustrative Fig. 1) having a first sidewall profile (first sidewall, Illustrative Fig. 1) facing the channel region (region occupied by channel members 208, Illustrative Fig. 1);
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a source/drain feature (epitaxial source/drain features 244, Illustrative Fig. 1, [0045]) disposed within a source/drain region (region occupied by epitaxial source/drain features 244, Illustrative Fig. 1) and in contact with a second lateral end (second lateral end as the right surface of the first inner spacer 240, Illustrative Fig. 1: upper and lower portions of the second lateral end are in contact with the source/drain features 244) of the inner spacers (first inner spacer layer 240, Illustrative Fig. 1) opposite the first lateral end (first lateral end, Illustrative Fig. 1) and with end portions (left and right ends) of the plurality of semiconductor channel layers (channel members 208, Illustrative Fig. 1); and
a portion of a gate structure (metal gate stack 252 between adjacent channel members 208, Illustrative Fig. 1, [0049]) disposed between the adjacent semiconductor channel layers (channel members 208, Illustrative Fig. 1), wherein the portion of the gate structure (metal gate stack 252 between adjacent channel members 208, Illustrative Fig. 1) includes at least an interfacial layer that interfaces the adjacent semiconductor channel layers (channel members 208, Illustrative Fig. 1) and a high-K dielectric layer disposed over the interfacial layer (while not illustrated in any of the figures, [0042]: “the metal gate stack 252 (or high-K metal gate stack 252) includes an interfacial layer, a high-K gate dielectric layer formed over the interfacial layer, and/or a gate electrode layer formed over the high-K gate dielectric layer.”, and therefore interfacial layer is the outside layer of the gate structure that interfaces the adjacent channel layers), wherein the inner spacers (first inner spacer layer 240, Illustrative Fig. 1) are disposed on either side of the portion of the gate structure (metal gate stack 252 between adjacent channel members 208, Illustrative Fig. 1), and wherein topmost portions (topmost portions, Illustrative Fig. 1) of the inner spacers (first inner spacer layer 240, Illustrative Fig. 1) on either side of the portion of the gate structure (metal gate stack 252 between adjacent channel members 208, Illustrative Fig. 1) define a horizontal plane (horizontal plane, Illustrative Fig. 1) that is disposed above a topmost surface (topmost surface, Illustrative Fig. 1) of the portion of the gate structure (metal gate stack 252 between adjacent channel members 208, Illustrative Fig. 1).
Chiang does not teach that the first sidewall profile is a first V-shaped sidewall profile (sidewall profile of Chiang has a U-shape). However, a person of ordinary skill in the art before the effective filing date of the claimed invention would know that V-shape, U-shape, dome-shape and square-shape are alternative shapes for first sidewall profiles of inner spacers as evidenced by Wang (US 2021/0376119 A1, Fig. 2A-K, [0021]: “the cross-sectional shape of the inner spacers 31 can be designed for specific purposes in various embodiments”), and a specific shape is chosen according to device design and manufacturing requirements. Therefore, the shape of the first sidewall profile being a V-shape does not carry an inventive weight (see MPEP 2144.04 (IV)), and Chiang meets all the limitations of claim 18.
Regarding claim 19, Chiang teaches the semiconductor device of claim 18, wherein a first width (see first width corresponding the width of the middle of the inner spacer in Illustrative Fig. 1) of a middle portion of the inner spacers (comprising first inner spacer layer 240 and second inner spacer layer 242, Illustrative Fig. 1) is greater than a second width (the width at the top and bottom portions reduces to zero) of top/bottom portions (topmost portion, Illustrative Fig. 1) of the inner spacers (comprising first inner spacer layer 240 and second inner spacer layer 242, Illustrative Fig. 1).
Regarding claim 20, Chiang teaches the semiconductor device of claim 18, wherein lateral ends of the portion of the gate structure have a second sidewall profile (U-shaped profile of the second lateral end, Illustrative Fig. 1) in contact with the first V-shaped sidewall profile.
Chiang does not teach that the second sidewall profile is a second V-shaped sidewall profile (sidewall profile of Chiang has a U-shape). However, a person of ordinary skill in the art before the effective filing date of the claimed invention would know that V-shape, U-shape, dome-shape and square-shape are alternative shapes for the second sidewall profiles of inner spacers as evidenced by Wang (US 2021/0376119 A1, Fig. 2A-K, [0021]: “the cross-sectional shape of the inner spacers 31 can be designed for specific purposes in various embodiments”), and a specific shape is chosen according to device design and manufacturing requirements. Therefore, the shape of the second sidewall profile being a V-shape does not carry an inventive weight (see MPEP 2144.04 (IV)), and Chiang meets all the limitations of claim 20.
Response to Arguments
It has been acknowledged that the applicant amended claims 1, 4-7, 9, 11, 18, and 20 per response dated on 3/23/2026. Applicant's arguments with respect to claims have been fully considered.
Applicant’s amendments to claims 1, 4-7, 9, and 11 have overcome the 35 U.S.C. 112(b) rejections made on claims 1-11 in the final office action dated 1/21/2026. As detailed in the current office actions, claims 1-12 are now allowed.
Applicant’s amendment to independent claim 18, now also disclosing that “wherein the portion of the gate structure includes at least an interfacial layer that interfaces the adjacent semiconductor channel layers and a high-K dielectric layer disposed over the interfacial layer”, overcame the 35. U.S.C. 102 rejection made in the final office action. However, amended independent claim 18 and dependent claims 19-20 are now rejected under new grounds based on a new prior-art, Chiang (US 2020/0381545 A1), in the current office action.
For the purpose of compact prosecution, the Examiner notes that amending claim 18 to clarify the structure of the inner spacers and semiconductor channels further might render independent claim 18 inventive and non-obvious.
The Examiner is available for an interview at Applicant’s convenience if the Applicant would like to discuss the application.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hatcher (US 2016/0172358 A1) teaches a semiconductor device with inner spacers between semiconductor channels, which is relevant to claims 18-20.
Chuo (US 2020/0381546 A1) teaches a semiconductor device with inner spacers between semiconductor channels, which is relevant to claims 18-20.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ILKER OZDEN whose telephone number is (703)756-5775. The examiner can normally be reached Monday - Friday 8:30am-5:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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